Underwater LiDAR full waveform sampling method based on FPGA timing control

Abstract

The application discloses a kind of underwater LiDAR full waveform sampling methods based on FPGA timing control.This full waveform sampling method controls the timing of each module according to sampling requirements, avoids timing conflicts in the sampling process, and achieves the requirements of large data storage and high-speed read-write.The method solves the problems of slow speed and excessive delay in the sampling process controlled by single-chip microcomputer, greatly improves the collection speed and operating frequency of the laser radar collection module, and expands the application range of the laser radar, providing more possibilities for the application field of laser radar.

Description

Technical Field

[0001] This invention relates to the field of lidar, and particularly to underwater lidar echo signal sampling. It proposes an underwater LiDAR full waveform sampling method based on FPGA timing control, which mainly focuses on the timing control of the full waveform sampling process of the echo signal. Background Technology

[0002] With the rapid development of related technologies, lidar has made significant progress in many fields such as surveying, aviation, transportation, military, and meteorology. Its application in marine exploration and underwater topography mapping has also matured. Lidar is acquiring information at increasingly faster speeds and in larger volumes, resulting in more refined and accurate underwater topography detection. During operation, lidar requires the acquisition of echo signals; therefore, the waveform sampling requirements determine the structure and parameters of the lidar acquisition system. Currently, the most commonly used sampling method in acquisition systems is full waveform sampling.

[0003] Full waveform sampling involves converting the waveform of the received echo signal into data, storing it, and then reconstructing the waveform through subsequent processing and algorithms. The laser flight time is calculated from the peak value of the reconstructed waveform and the peak value of the emitted laser signal. Water depth measurement, on the other hand, calculates the actual depth by determining the time difference between the peak values ​​of the surface echo signal and the bottom echo signal after reconstructing the received echo signal. When sampling the waveform, it is not necessary to record every point on the curve; a certain number of points containing most of the signal's information are sufficient for waveform reconstruction. In data acquisition systems, a microcontroller is typically used as the control center, and the event processing employs a sequential processing structure, which significantly hinders high-speed data transmission and results in relatively long processing times. To address the demands of high data throughput and fast processing speed in acquisition systems, this invention proposes an underwater LiDAR full waveform sampling method based on FPGA timing control. This method uses a parallel structure to process data, enabling high-speed, high-volume data processing. Summary of the Invention

[0004] This invention addresses the problems of slow and unstable echo signal acquisition speed in lidar systems by proposing a full waveform acquisition method for lidar echo signals based on FPGA timing control. This method can achieve a sampling rate of 1 GSPS (Gigabit Samples Per Second) and realize functions such as simultaneous acquisition of multiple channels, information interaction with the host computer and other modules, and instantaneous data reading and writing.

[0005] FPGA-controlled AD acquisition cards can achieve high-speed AD sampling. They have 32-bit and 64-bit memory, which can be called according to functional requirements. Through the connection of FMC high-frequency daughterboard, multiple AD acquisition cards can be combined to achieve simultaneous multi-channel acquisition. Each acquisition channel can be configured independently, and different acquisition parameters can be set for different working environments.

[0006] FPGA timing control is the setup time, i.e., clock offset FT. su The calculation is as follows:

[0007] FT su =T din +T su -T clk (1)

[0008] Its holding time FT h for:

[0009] FT h =T h +T clk (2)

[0010] Data transmission time FT co for:

[0011] FT co =T clk +T co +T out (3)

[0012] T din The delay time T between the data input and the input of the register. din T is the delay time to the clock input of the register. su / T h T represents the setup and hold time of the FPGA's internal registers. co T is the FPGA internal register transfer time. out This is the delay time from the FPGA register output to the data output port.

[0013] The formula for calculating input delay is as follows:

[0014] IN = T pcb -(T clk2 -T clk1 )+T co (4)

[0015] In the formula, T clk1 It's due to external device clock skew, T clk2 It is the delay from the external clock to the FPGA, T co It is the device data output delay.

[0016] After the data is calculated by formula (4) from the transmitted clock signal, the calculation of its maximum input delay and minimum input delay is different:

[0017]

[0018] As can be seen from formula (5), the minimum input delay is calculated by taking the trace delay T as the value. pcb The minimum value of the delay T from the external clock to the FPGA. clk2 The maximum value, external device clock skew T clk1 Minimum value and data transmission delay T co The minimum value. The direction of the value is reversed when calculating the maximum input delay. Attached Figure Description

[0019] Figure 1 System sampling timing diagram;

[0020] Figure 2 System overall structure;

[0021] Figure 3 Physical structure of AD acquisition module;

[0022] Figure 4 Indoor testing;

[0023] Figure 5 Indoor test sampling waveform diagram;

[0024] Figure 6 Overall outdoor test diagram;

[0025] Figure 7 Test related signal description;

[0026] Figure 8 Waveforms collected during outdoor testing; Detailed Implementation

[0027] The specific implementation of the present invention will be further described below with reference to the accompanying drawings and embodiments.

[0028] Combination Figure 1When the AD high-speed sampling module is working, after receiving the start signal from the central control system and being powered on, the laser emits an analog signal synchronized with the emitted pulsed laser, which is the main wave signal, with an amplitude of approximately 2.5V. Simultaneously, after the main wave signal is emitted, the laser also sends a trigger signal to command the AD to start acquisition, with an amplitude of approximately 3V. The repetition frequency of both the main wave signal and the trigger signal is 2kHz. After receiving the rising edge signal, the AD acquisition card waits for the delay time set by the host computer before starting acquisition. The pulse width of the acquisition channel can be set from 5-2000ns. The acquisition card is 1GSPS, meaning that one point is acquired every 1ns. The larger the channel width, the larger the amount of data acquired with each trigger. After completing the set number of acquisitions, acquisition automatically ends and the data is stored in the SSD, waiting for the next rising edge to begin acquisition again, thus repeating the cycle. There are three acquisition channels: surface, shallow water, and bottom. The reception time difference between each signal represents the aircraft's altitude above the water surface and the depth of the measured location. Once the central control system issues a stop signal, the final data acquisition will end, the data acquisition process will cease, and the power will be cut off.

[0029] Example 1:

[0030] First, indoor testing was conducted. The entire indoor experimental setup was as follows: Figure 4 The setup includes a LiDAR system, power supply, acrylic water tank, plane mirror, and black baffle. The experiment was conducted according to the experimental procedure, and several experiments are described below. The acquired waveforms are shown below. Figure 5 As shown in Figure (a), the curves represent the signals received by the small field-of-view (PMT) detector in the lidar receiving optical system at a distance of 32 cm from the water surface. The first larger signal is the water surface echo signal, the second smaller signal is the underwater obstacle echo signal, and the rest are noise or interference signals received from partial backscattering, which are not the target signals. The lower curves in Figures (b), (c), and (d) represent the signals received by the large field-of-view (PMT) detector in the lidar receiving system, where the distances between the obstacle and the water surface are 84 cm, 210 cm, and 210 cm, respectively.

[0031] Example 2:

[0032] Example 2 primarily involved outdoor testing because the outdoor environment differs drastically from the indoor environment. The testing environment was as follows: Figure 6 As shown, the focus is completely different. Indoor testing primarily involves testing limits, pursuing accuracy, and qualitative and quantitative analysis, while outdoor testing requires convenient processes, lightweight equipment, and emphasizes stability and versatility. Therefore, the specific equipment and procedures for indoor and outdoor testing differ. Outdoor testing no longer uses signals generated by a signal generator as trigger signals; instead, the trigger signal is provided by the module inside the lidar. Figure 7The test uses several signals received by an oscilloscope. The main wave signal is a signal with the same parameters as the emitted laser beam, provided by the laser at the same time. The trigger signal is a square wave signal with a repetition frequency of 2kHz generated by the laser, which is connected to the AD acquisition module as the trigger signal to start its acquisition. Acquisition begins when the rising edge of the signal is encountered and the number of times it is triggered increases. The PMT and APD receive the echo signals transmitted from the large and small fields of view, respectively.

[0033] Figure 8 The waveform generated for testing had a significantly larger amplitude of echo signal, which caused oscillations during waveform acquisition. However, compared with the daytime experiment, the oscillations and noise of the received signal were significantly reduced. Therefore, under relatively close acquisition conditions, outdoor natural light has a certain impact on the reception and acquisition of echo signals. When other conditions remain unchanged, appropriately increasing the acquisition distance, i.e., the measurement depth, can slightly reduce the error caused by natural light.

[0034] Based on the verification of the above two embodiments, the method for full waveform sampling of underwater lidar echo signals based on FPGA timing control was successfully implemented, proving the correctness and feasibility of the present invention.

[0035] The above embodiments are only used to illustrate the present invention and are not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the present invention, and the patent protection scope of the present invention should be defined by the claims.

[0036] All technical contents not described in detail in this invention are publicly known technologies.

Claims

1. A full waveform sampling method for underwater LiDAR based on FPGA timing control, characterized in that: The sampling system mainly consists of a clock module, a data input / output module, a storage module, a communication module, and an AD acquisition card; it requires a square wave signal with a pulse width of 500ns, a repetition frequency of 2kHz, and an amplitude of 3V as a trigger signal, and the channel width of the acquisition module is consistent with the pulse width of the trigger signal; High-speed AD sampling is achieved by controlling the AD acquisition card through FPGA. Multiple AD acquisition cards are combined through the connection of FMC high-frequency daughter board to realize multi-channel simultaneous acquisition. Each acquisition channel is configured independently and different acquisition parameters are set for different working environments. FPGA timing control is the setup time, i.e., clock offset FT. su The calculation method is as follows: ； Its holding time FT h for: ； Data transmission time FT co for: ； T din The delay time T between the data input and the input of the register. din T is the delay time to the clock input of the register. su and FT h These represent the setup time and hold time of the FPGA's internal registers, T. co T is the FPGA internal register transfer time. out This is the delay time from the FPGA register to the data output port; The formula for calculating the input register delay is: ； In the formula, T clk1 It's due to external device clock skew, T clk2 It is the delay from the external clock to the FPGA.

2. The underwater LIDAR full waveform sampling method based on FPGA timing control according to claim 1, characterized in that: The pulse width setting of the acquisition channel determines the number of sampling points in a trigger signal. By setting the delay time, the start time of sampling can be delayed compared to the trigger signal, thereby adjusting the sampling range and acquiring the echo signal more accurately. This method avoids data redundancy caused by excessively large pulse width of the acquisition channel or delayed echo signal, thereby reducing storage pressure and facilitating data processing and analysis.

3. The underwater LIDAR full waveform sampling method based on FPGA timing control according to claim 1, characterized in that, FPGA is used for communication with lidar systems, data storage and computation, as well as controlling the sampling channel width and sampling number during the acquisition process.

4. The underwater LIDAR full waveform sampling method based on FPGA timing control according to claim 1, characterized in that, FPGA timing control of each module prevents timing conflicts during the sampling process from causing data corruption and incomplete acquisition.

Images