Instruction processing method and apparatus, electronic device, and computer-readable storage medium

Abstract

This application provides an instruction processing method, apparatus, electronic device, and computer-readable storage medium, relating to the field of computer technology. The method includes: detecting an abnormal instruction, terminating the subsequent instruction processing flow of the abnormal instruction, and performing redirection processing on the abnormal instruction; obtaining the target instruction for redirection, and executing the instruction processing flow of the target instruction. In related technologies, when an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is typically only identified, and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed, at which point it is deselected in the reordering cache, and redirection processing is performed on the abnormal instruction. Compared to related technologies, this application reduces processor power consumption, minimizes unnecessary power waste, and improves instruction processing efficiency.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more specifically, to an instruction processing method, apparatus, electronic device, and computer-readable storage medium. Background Technology

[0002] In processor design, instruction execution scenarios typically fall into two categories: sequential instruction execution and instruction redirection. In instruction redirection, the program counter (PC) jump causes pipeline flushing, hindering further processor performance improvements. In particular, the redirection handling of detected abnormal instructions results in low instruction processing efficiency and high processor power consumption. Summary of the Invention

[0003] The purpose of this application is to at least solve one of the aforementioned technical defects, particularly the technical defects of low instruction processing efficiency and high processor power consumption.

[0004] According to one aspect of this application, an instruction processing method is provided, the method comprising: detecting an abnormal instruction during instruction processing; terminating the subsequent instruction processing flow of the abnormal instruction when the abnormal instruction is detected, and triggering redirection processing on the abnormal instruction in response to the abnormal instruction; obtaining a target instruction determined by the redirection processing, and executing the instruction processing flow of the target instruction.

[0005] Optionally, the step of performing redirection processing on the abnormal instruction includes: determining the instruction exception type of the abnormal instruction; and performing the redirection processing according to the preset processing operation corresponding to the instruction exception type.

[0006] Optionally, the step of performing the redirection process according to the preset processing operation corresponding to the instruction exception type includes: determining the target address for redirection according to the preset processing operation corresponding to the instruction exception type.

[0007] Optionally, the instruction processing flow for obtaining the target instruction for redirection and executing the target instruction includes: obtaining the target instruction based on the target address; and executing the instruction processing flow for the target instruction.

[0008] Optionally, the step of detecting an abnormal instruction and performing redirection processing on the abnormal instruction includes: if at least two abnormal instructions are detected, determining the instruction generation order of the at least two abnormal instructions; and performing the redirection processing on the abnormal instructions respectively according to the instruction generation order.

[0009] Optionally, after detecting the abnormal instruction, the method further includes: stopping the instruction processing flow of subsequent instructions, wherein the subsequent instructions include instructions generated after the abnormal instruction was generated.

[0010] According to another aspect of this application, an instruction processing apparatus is provided, the apparatus comprising:

[0011] The redirection module is used to detect abnormal instructions during instruction processing; when an abnormal instruction is detected, the subsequent instruction processing flow of the abnormal instruction is terminated, and redirection processing is performed on the abnormal instruction; the instruction processing module is used to obtain the target instruction determined by the redirection processing and execute the instruction processing flow of the target instruction.

[0012] Optionally, the redirection module is specifically used to: determine the instruction exception type of the abnormal instruction; and execute the redirection processing according to the preset processing operation corresponding to the instruction exception type.

[0013] According to another aspect of this application, an instruction processing apparatus is provided, comprising: a CPU instruction pipeline that, when an abnormal instruction is detected during or before the pipeline execution phase, identifies and sends the abnormal instruction; and a redirection module that, in response to an abnormal identifier sent from the CPU instruction pipeline, identifies the abnormal type of the abnormal instruction based on the abnormal identifier, performs preset redirection processing according to the abnormal type, and prevents the abnormal instruction from entering the CPU instruction pipeline during the redirection processing to terminate the subsequent instruction processing flow for the abnormal instruction.

[0014] According to another aspect of this application, an electronic device is provided, the electronic device comprising:

[0015] One or more processors; memory; one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs being configured to: perform the instruction processing method according to any one of the first aspects of this application.

[0016] For example, in a third aspect of this application, a computing device is provided, comprising: a processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; the memory is used to store at least one executable instruction, which causes the processor to perform an operation corresponding to the instruction processing method shown in the first aspect of this application.

[0017] According to another aspect of this application, a computer-readable storage medium is provided, wherein the computer program, when executed by a processor, implements the instruction processing method described in any of the first aspects of this application. For example, a fourth aspect of the embodiments of this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the instruction processing method shown in the first aspect of this application.

[0018] According to one aspect of this application, a computer program product or computer program is provided, comprising computer instructions stored in a computer-readable storage medium. A processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the methods provided in various alternative implementations of the first aspect described above.

[0019] The beneficial effects of the technical solution provided in this application are:

[0020] In this embodiment, when an abnormal instruction is detected during instruction execution, redirection processing is immediately performed on the abnormal instruction; the target instruction for redirection is obtained, and the instruction processing flow of the target instruction is executed. In related technologies, when an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is typically only marked, and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed and then retired from the reordering cache, at which point redirection processing is performed on the abnormal instruction. Compared to the above technologies, this embodiment can reduce the processing power consumption and processing time from the detection of an abnormal instruction to the completion of the instruction processing flow of the abnormal instruction and retirement from the reordering cache, thereby reducing processor power consumption, reducing unnecessary power waste, and improving instruction processing efficiency. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments of this application will be briefly introduced below.

[0022] Figure 1 A flowchart illustrating the instruction processing of existing technologies;

[0023] Figure 2 A flowchart illustrating instruction processing provided in an embodiment of this application;

[0024] Figure 3 A flowchart illustrating an instruction processing method provided in an embodiment of this application;

[0025] Figure 4 This is one of the structural schematic diagrams of an instruction processing device provided in an embodiment of this application;

[0026] Figure 5 This is a second schematic diagram of the structure of an instruction processing device provided in an embodiment of this application;

[0027] Figure 6 This is a schematic diagram of the structure of an electronic device for instruction processing provided in an embodiment of this application. Detailed Implementation

[0028] The embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the embodiments described below with reference to the accompanying drawings are exemplary descriptions for explaining the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions of the embodiments of this application.

[0029] Those skilled in the art will understand that, unless otherwise stated, the singular forms “a,” “an,” “the,” and “the” used herein may also include the plural forms. It should be further understood that the terms “comprising” and “including” as used in embodiments of this application mean that the corresponding feature can be implemented as the presented feature, information, data, step, operation, element, and / or component, but do not exclude implementation as other features, information, data, steps, operations, elements, components, and / or combinations thereof supported by the art.

[0030] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0031] First, let's introduce and explain several terms used in this application:

[0032] Instruction redirection: Instruction redirection is the redirection of instructions. That is, when an abnormal instruction is detected, the correct instruction processing path is re-determined, such as re-determining the correct instruction address to obtain the correct instruction.

[0033] The re-order buffer (ROB) allows instructions to be submitted in their original order after being executed out of order.

[0034] Cache: Instruction cache, a high-speed buffer used to cache instructions. Cache memory is a small but very fast memory located between the CPU and main memory (DRAM, Dynamic Random Access Memory), typically composed of SRAM (Static Random Access Memory). It is a small-capacity but high-speed memory located between the CPU and main memory. The CPU is much faster than main memory. When the CPU directly accesses data from main memory, it has to wait for a certain period of time. The cache can store data that the CPU has just used or uses repeatedly. If the CPU needs to use this data again, it can directly retrieve it from the cache, thus avoiding repeated data access, reducing CPU waiting time, and improving system efficiency. Cache is further divided into L1 Cache (Level 1 cache) and L2 Cache (Level 2 cache). L1 Cache is mainly integrated inside the CPU, while L2 Cache is integrated on the motherboard or CPU.

[0035] The instruction processing method, apparatus, electronic device, and computer-readable storage medium provided in this application are intended to solve the above-mentioned technical problems of the prior art.

[0036] The technical solution of this application and how the technical solution of this application solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of this application will be described below with reference to the accompanying drawings.

[0037] First, combined Figure 1 This paper describes the instruction processing flow and redirection processing flow of the existing technology.

[0038] like Figure 1 As shown, the instruction processing flow involves seven modules: instruction cache, instruction fetch module, decode module, dispatch module, issue module, execution module, and ROB cache.

[0039] Instruction cache (icache): Used to cache instructions.

[0040] Instruction Fetch Unit (IFU): Executes the fetch instruction by retrieving it from the icache using the value of the Program Counter Register (PCR) as the address.

[0041] Decoder module: Decodes the fetched instructions and reads the register file based on the decoding results to obtain the source operands of the instructions.

[0042] Dispatcher module: Executes the decoded instructions to the dispatch module in the original order specified in the program.

[0043] Issue module: Executes instructions from the issue queue to the execution module. Specifically, during instruction pipeline execution, instructions that have undergone fetching, decoding, and dispatching are pushed onto the issue module and cached in its issue queue.

[0044] Execution module (Execute or lsu): Executes instructions based on the decoding results.

[0045] ROB cache: Used to cache instructions that have completed the instruction processing flow, so as to perform deprecation processing on instructions that have completed the instruction processing flow.

[0046] The instruction processing flow is as follows: the instruction fetch module, decode module, dispatch module, issue module, and execution module are executed sequentially.

[0047] In the prior art, if an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is usually only marked and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed. Only after the abnormal instruction is deselected in the re-order buffer (ROB) will redirection processing be performed on the abnormal instruction.

[0048] For example, exception instructions such as `ecall` and `illegal instr` are usually detected in the decoding module; division by zero exception instructions are usually detected in the execution module. However, `ecall`, `illegal instr`, and division by zero exception instructions are only redirected after the instruction processing flow is completed, that is, after the execution module has finished processing and has exited the ROB cache.

[0049] In other words, in existing technologies, during the period from detecting an abnormal instruction to its retirement from the reordering cache, the processor continues to process the abnormal instruction and other instructions generated after the abnormal instruction (for simplicity, these other instructions can be called subsequent instructions). It's understandable that continuing the instruction processing flow for the abnormal instruction and its subsequent instructions after detection is essentially wasting effort, increasing unnecessary power consumption, and reducing instruction processing efficiency.

[0050] In response to the detection of an abnormal instruction, the embodiments of this application can immediately perform redirection processing on the abnormal instruction, which can effectively reduce processor power consumption, reduce unnecessary power waste, and improve instruction processing efficiency.

[0051] Combination Figure 2 The instruction processing flow and redirection processing flow of the embodiments of this application will be described.

[0052] like Figure 2 As shown, the instruction processing flow involves eight modules: instruction cache, instruction fetch module, decoding module, redirection processing module, dispatch module, issue module, execution module, and ROB cache.

[0053] Instruction cache (icache): Used to cache instructions.

[0054] Instruction Fetch Unit (IFU): Executes the fetch instruction by retrieving the instruction from the icache using the value of the Program Counter Register (PC) as the address.

[0055] Decoder module: Decodes the fetched instructions and reads the register file based on the decoding results to obtain the source operands of the instructions.

[0056] Redirect processing module (pc redirect module): Used to perform redirect processing.

[0057] Dispatcher module: Executes the decoded instructions to the dispatch module in the original order specified in the program.

[0058] Issue module: Executes instructions from the issue queue to the execution module. Specifically, during instruction pipeline execution, instructions that have undergone fetching, decoding, and dispatching are pushed onto the issue module and cached in its issue queue.

[0059] The execution module (Execute or LSU) executes instructions based on the decoded results. LSU is the execution unit for memory access instructions, which are instructions that access memory, such as data load instructions. Execute is the execution unit for non-memory access instructions, which are instructions that do not access memory, such as instructions that perform addition or subtraction operations.

[0060] ROB cache: Used to cache instructions that have completed the instruction processing flow, so as to perform deprecation processing on instructions that have completed the instruction processing flow.

[0061] The instruction processing flow is as follows: the instruction fetch module, decode module, dispatch module, issue module, and execution module are executed sequentially.

[0062] In the above instruction processing flow, if an abnormal instruction is detected, the subsequent instruction processing flow of the abnormal instruction can be terminated, and redirection processing can be performed immediately through the redirection processing module.

[0063] For example, when the decoding module detects an abnormal instruction such as an `ecall` instruction or an `illegal instr` instruction, the instruction processing flow for that abnormal instruction is terminated. The redirection processing module immediately determines the instruction exception type and, based on the preset processing operation corresponding to that instruction exception type, determines the target address for redirection (the target address is the address for re-determining the correct instruction). Then, the instruction fetch module retrieves the target instruction from the target address and executes the instruction processing flow for that target instruction. As another example, when the execution module detects a division-by-zero exception instruction, the instruction processing flow for that instruction is terminated. The redirection processing module immediately determines the instruction exception type and, based on the preset processing operation corresponding to that instruction exception type, determines the target address for redirection. Then, the instruction fetch module retrieves the target instruction from the target address and executes the instruction processing flow for that target instruction.

[0064] See Figure 3 This application provides an instruction processing method applied to a processor, such as a CPU or a graphics processing unit (GPU). Specifically, the method may include the following steps:

[0065] S301: During instruction processing, an abnormal instruction is detected. When an abnormal instruction is detected, the subsequent instruction processing flow of the abnormal instruction is terminated, and the abnormal instruction is responded to and redirection processing is performed on the abnormal instruction.

[0066] Optionally, the embodiments of this application can be applied to the field of computer technology, specifically to the scenario of redirection processing of abnormal instructions.

[0067] Specifically, abnormal instructions include instructions that do not conform to the preset instruction rules, as well as instructions that encounter errors during instruction processing. For example, abnormal instructions may include the ecall instruction, the illegal instr instruction, the division by zero exception instruction, and so on.

[0068] In this embodiment of the application, in response to the detection of an abnormal instruction, on the one hand, the subsequent instruction processing flow of the abnormal instruction is terminated, and on the other hand, the abnormal instruction is immediately redirected.

[0069] Terminating the subsequent instruction processing flow of the abnormal instruction means that if an abnormal instruction is detected, the subsequent instruction processing flow for that abnormal instruction will no longer be executed. For example, abnormal instructions such as the ecall instruction and the illegal instr instruction are usually detected in the decoding module. When an ecall instruction or an illegal instr instruction is detected in the decoding module, the relevant processing in the modules after the decoding module will no longer be executed for that ecall instruction or illegal instr instruction. That is, the processing executed in the dispatch module, the dispatch module, the execution module, and the ROB cache will no longer be executed.

[0070] Redirecting the abnormal instruction means: re-determining the correct instruction processing path, such as re-determining the correct instruction address (the correct instruction address is the target address in this application) in order to obtain the correct instruction (the correct instruction is the target instruction in this application).

[0071] In summary, terminating the subsequent instruction processing flow of the abnormal instruction and immediately performing redirection processing on the abnormal instruction can reduce the processing power and processing time during the period from detecting the abnormal instruction to the completion of the instruction processing flow of the abnormal instruction and its retirement in the reordering cache, thereby effectively reducing processor power consumption, reducing unnecessary power waste, and improving instruction processing efficiency.

[0072] S302: Obtain the target instruction determined by the redirection process, and execute the instruction processing flow of the target instruction.

[0073] Specifically, the target instruction is the instruction at the correctly redefined instruction address (i.e., the target address). Redirection processing determines the target address so that the target instruction can be retrieved from that address.

[0074] After obtaining the target instruction, the instruction processing flow of the target instruction can be executed.

[0075] In this embodiment, when an abnormal instruction is detected during instruction execution, redirection processing is immediately performed on the abnormal instruction; the target instruction for redirection is obtained, and the instruction processing flow of the target instruction is executed. In related technologies, when an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is typically only marked, and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed and then retired from the reordering cache, at which point redirection processing is performed on the abnormal instruction. Compared to the above technologies, this embodiment can reduce the processing power consumption and processing time from the detection of an abnormal instruction to the completion of the instruction processing flow of the abnormal instruction and retirement from the reordering cache, thereby reducing processor power consumption, reducing unnecessary power waste, and improving instruction processing efficiency.

[0076] In one embodiment of this application, the redirection processing of the abnormal instruction includes:

[0077] Determine the instruction exception type of the abnormal instruction;

[0078] The redirection process is executed according to the preset processing operation corresponding to the instruction exception type.

[0079] Optionally, the step of performing the redirection processing according to the preset processing operation corresponding to the instruction exception type may include the following processing methods:

[0080] The target address for redirection is determined based on the preset processing operation corresponding to the instruction exception type.

[0081] Specifically, different types of abnormal instructions correspond to different preset processing operations. Based on the preset processing operation corresponding to the instruction abnormality type, the target address corresponding to the preset processing operation can be determined.

[0082] For example, when the instruction exception type of the exception instruction is a base address exception, the preset processing operation corresponding to the base address exception may include performing an addition operation, a multiplication operation, etc. Based on the above preset processing operation, the target address corresponding to the preset processing operation can be determined.

[0083] The target address is the correct instruction address that has been redefined; the target instruction can be obtained based on the target address.

[0084] In one embodiment of this application, the instruction processing flow of obtaining the target instruction for redirection and executing the target instruction includes:

[0085] Based on the target address, obtain the target instruction;

[0086] Instruction processing flow for executing the target instruction.

[0087] As an example two, combined with Figure 2 For example, when the decoding module detects an abnormal instruction such as an `ecall` instruction or an `illegal instr` instruction, the subsequent instruction processing flow of the abnormal instruction is terminated, and the instruction exception type is immediately determined by the redirection processing module. Based on the preset processing operation corresponding to the instruction exception type, the target address for redirection is determined. Then, the instruction fetching module obtains the target instruction based on the target address and executes the instruction processing flow of the target instruction.

[0088] In one embodiment of this application, detecting an abnormal instruction and performing redirection processing on the abnormal instruction includes:

[0089] If at least two of the abnormal instructions are detected, determine the instruction generation order of the at least two abnormal instructions;

[0090] The redirection process is performed on each of the abnormal instructions according to the order in which the instructions are generated.

[0091] As an example three, it is still combined with Figure 2 In real-world scenarios, if at least two of the aforementioned abnormal instructions are detected during the instruction processing flow, for example, in... Figure 2 In the instruction processing flow shown, when both the decoding module detects abnormal instruction A and the execution module detects abnormal instruction B, the instruction processing flow of the previously generated instruction will affect the instruction processing flow of the subsequently generated instruction. Therefore, in this embodiment, the instruction generation order of the two abnormal instructions can be determined, and the redirection processing can be performed on the abnormal instructions according to the instruction generation order. It is understood that the instruction generation order of abnormal instruction B detected by the execution module is before that of abnormal instruction A detected by the decoding module; therefore, redirection processing can be performed first based on abnormal instruction B.

[0092] In one embodiment of this application, after detecting the abnormal instruction, the method further includes:

[0093] The instruction processing flow for stopping subsequent instructions is included, wherein the subsequent instructions include instructions generated after the abnormal instruction is generated.

[0094] Specifically, since the instruction processing flow of previously generated instructions affects the instruction processing flow of subsequently generated instructions, in this embodiment, when an abnormal instruction is detected, the instruction processing flow of subsequent instructions can be stopped. This avoids unnecessary power consumption waste caused by the execution of subsequent instructions. The subsequent instructions include those generated after the abnormal instruction is generated.

[0095] In addition, it should be noted that, in Figure 2In the instruction processing flow shown, when an abnormal instruction is detected, on the one hand, redirection processing can be performed on the abnormal instruction; on the other hand, the instruction processing flow of the instructions generated before the abnormal instruction was generated (which can be referred to as the preceding instructions) can continue to be executed. In other words, the redirection processing for the abnormal instruction can be executed in parallel with the instruction processing flow of other normal preceding instructions.

[0096] In this embodiment, when an abnormal instruction is detected during instruction execution, redirection processing is immediately performed on the abnormal instruction; the target instruction for redirection is obtained, and the instruction processing flow of the target instruction is executed. In related technologies, when an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is typically only marked, and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed and then retired from the reordering cache, at which point redirection processing is performed on the abnormal instruction. Compared to the above technologies, this embodiment can reduce the processing power consumption and processing time from the detection of an abnormal instruction to the completion of the instruction processing flow of the abnormal instruction and retirement from the reordering cache, thereby reducing processor power consumption, reducing unnecessary power waste, and improving instruction processing efficiency.

[0097] This application provides an instruction processing device, such as... Figure 4 As shown, the instruction processing device 40 may include: a redirection module 401 and an instruction processing module 402, wherein,

[0098] The redirection module 401 is used to detect abnormal instructions during instruction processing; when an abnormal instruction is detected, the subsequent instruction processing flow of the abnormal instruction is terminated, and the abnormal instruction is triggered to perform redirection processing in response to the abnormal instruction.

[0099] The instruction processing module 402 is used to obtain the target instruction for redirection and execute the instruction processing flow of the target instruction.

[0100] In one embodiment of this application, the redirection module is specifically used for:

[0101] Determine the instruction exception type of the abnormal instruction;

[0102] The redirection process is executed according to the preset processing operation corresponding to the instruction exception type.

[0103] In one embodiment of this application, the redirection module is specifically used for:

[0104] The target address for redirection is determined based on the preset processing operation corresponding to the instruction exception type.

[0105] In one embodiment of this application, the instruction processing module is specifically used to obtain the target instruction based on the target address;

[0106] Instruction processing flow for executing the target instruction.

[0107] In one embodiment of this application, the redirection module is specifically used for:

[0108] If at least two of the abnormal instructions are detected, determine the instruction generation order of the at least two abnormal instructions;

[0109] The redirection process is performed on each of the abnormal instructions according to the order in which the instructions are generated.

[0110] In one embodiment of this application, the apparatus further includes a stop processing module, configured to stop the instruction processing flow of subsequent instructions after the abnormal instruction is detected, wherein the subsequent instructions include instructions generated after the abnormal instruction is generated.

[0111] This application provides an instruction processing device, such as... Figure 5 As shown, the instruction processing device 50 may include: a CPU instruction pipeline 501 and a redirection module 502, wherein,

[0112] The CPU instruction pipeline identifies and sends out abnormal instructions when it detects abnormal instructions during or before the pipeline execution phase.

[0113] The redirection module responds to an exception identifier sent from the CPU instruction pipeline, identifies the exception type of the exception instruction based on the exception identifier, performs preset redirection processing according to the exception type, and prevents the exception instruction from entering the CPU instruction pipeline during the redirection processing to terminate the subsequent instruction processing flow for the exception instruction.

[0114] The apparatus in this application embodiment can execute the method provided in this application embodiment, and the implementation principle is similar. The actions performed by each module in the apparatus of each embodiment of this application correspond to the steps in the method of each embodiment of this application. For detailed functional descriptions of each module of the apparatus, please refer to the descriptions in the corresponding methods shown above, which will not be repeated here.

[0115] In this embodiment, when an abnormal instruction is detected during instruction execution, redirection processing is immediately performed on the abnormal instruction; the target instruction for redirection is obtained, and the instruction processing flow of the target instruction is executed. In related technologies, when an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is typically only marked, and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed and then retired from the reordering cache, at which point redirection processing is performed on the abnormal instruction. Compared to the above technologies, this embodiment can reduce the processing power consumption and processing time from the detection of an abnormal instruction to the completion of the instruction processing flow of the abnormal instruction and retirement from the reordering cache, thereby reducing processor power consumption, reducing unnecessary power waste, and improving instruction processing efficiency.

[0116] This application provides an electronic device, comprising: a memory and a processor; at least one program stored in the memory, which, when executed by the processor, can achieve the following compared to the prior art: In this application, upon detecting an abnormal instruction, redirection processing is performed on the abnormal instruction; a target instruction for redirection is obtained, and the instruction processing flow of the target instruction is executed. Compared to related technologies, where, upon detecting an abnormal instruction in the instruction processing flow, the abnormal instruction is typically only identified and its instruction processing flow continues to execute until the instruction processing flow of the abnormal instruction is completed and then exited in the reordering cache, the present application immediately performs redirection processing on the abnormal instruction upon detection. This reduces the processing power consumption and time during the period from detecting the abnormal instruction to the completion of the instruction processing flow and exiting in the reordering cache, thereby reducing processor power consumption, minimizing unnecessary power waste, and improving instruction processing efficiency.

[0117] In one alternative embodiment, an electronic device is provided, such as Figure 6 As shown, Figure 6 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of this application.

[0118] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0119] Bus 4002 may include a pathway for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 5 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0120] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0121] The memory 4003 stores application code (computer program) that executes the solution of this application, and its execution is controlled by the processor 4001. The processor 4001 executes the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0122] Electronic devices include, but are not limited to: mobile phones, laptops, multimedia players, desktop computers, etc.

[0123] This application provides a computer-readable storage medium storing a computer program that, when run on a computer, enables the computer to execute the corresponding content in the aforementioned method embodiments.

[0124] In this embodiment, an abnormal instruction is detected, and redirection processing is performed on the abnormal instruction. The target instruction for redirection is obtained, and the instruction processing flow of the target instruction is executed. Compared to related technologies, where, when an abnormal instruction is detected in the instruction processing flow, the abnormal instruction is usually only marked and the instruction processing flow of the abnormal instruction continues to be executed until the instruction processing flow of the abnormal instruction is completed and then retired from the reordering cache, the present embodiment performs redirection processing immediately after detecting an abnormal instruction. This reduces the processing power consumption and processing time during the period from detecting an abnormal instruction to the completion of the instruction processing flow of the abnormal instruction and retirement from the reordering cache, thereby reducing processor power consumption, reducing unnecessary power waste, and improving instruction processing efficiency.

[0125] The terms "first," "second," "third," "fourth," "1," "2," etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in a sequence other than that shown in the figures or text.

[0126] It should be understood that although arrows indicate various operation steps in the flowcharts of this application's embodiments, the order in which these steps are implemented is not limited to the order indicated by the arrows. Unless explicitly stated herein, in some implementation scenarios of this application's embodiments, the implementation steps in each flowchart can be executed in other orders as required. Furthermore, some or all steps in each flowchart, based on the actual implementation scenario, may include multiple sub-steps or multiple stages. Some or all of these sub-steps or stages can be executed at the same time, and each sub-step or stage can also be executed at different times. In scenarios where execution times differ, the execution order of these sub-steps or stages can be flexibly configured according to requirements, and this application's embodiments do not limit this.

[0127] The above description is only an optional implementation method for some implementation scenarios of this application. It should be noted that for those skilled in the art, other similar implementation methods based on the technical concept of this application without departing from the technical concept of this application also fall within the protection scope of the embodiments of this application.

Claims

1. An instruction processing method, characterized by, include: During instruction processing, abnormal instructions are detected; When the decoding module detects an abnormal instruction, it terminates the subsequent instruction processing flow of the abnormal instruction and triggers redirection processing for the abnormal instruction in response to the abnormal instruction; wherein, the subsequent instruction processing flow includes: the processing of the abnormal instruction by the distribution module, the emission module, the execution module and the reordering buffer after the decoding module; Obtain the target instruction determined by the redirection process, and execute the instruction processing flow of the target instruction; the target instruction is the instruction in the correctly determined instruction address; The redirection process for the abnormal instruction includes: Determine the instruction exception type of the abnormal instruction; According to the preset processing operation corresponding to the instruction exception type, the redirection process is executed, which includes: re-determining the correct instruction address to obtain the correct instruction.

2. The instruction processing method of claim 1, wherein, The step of executing the redirection process according to the preset processing operation corresponding to the instruction exception type includes: The target address for redirection is determined based on the preset processing operation corresponding to the instruction exception type.

3. The instruction processing method of claim 2, wherein, The instruction processing flow for obtaining the target instruction for redirection and executing the target instruction includes: Based on the target address, obtain the target instruction; Instruction processing flow for executing the target instruction.

4. The instruction processing method according to claim 1, characterized in that, The detected abnormal command, and the redirection processing of the abnormal command, includes: If at least two of the abnormal instructions are detected, determine the instruction generation order of the at least two abnormal instructions; The redirection process is performed on each of the abnormal instructions according to the order in which the instructions are generated.

5. The instruction processing method according to claim 1, characterized in that, After detecting the abnormal command, the method further includes: The instruction processing flow for stopping subsequent instructions is included, wherein the subsequent instructions include instructions generated after the abnormal instruction is generated.

6. An instruction processing device, characterized in that, include: The redirection module is used to detect abnormal instructions during instruction processing. When the decoding module detects an abnormal instruction, it terminates the subsequent instruction processing flow of the abnormal instruction and triggers redirection processing for the abnormal instruction in response to the abnormal instruction; wherein, the subsequent instruction processing flow includes: the processing of the abnormal instruction by the distribution module, the emission module, the execution module and the reordering buffer after the decoding module; The instruction processing module is used to obtain the target instruction determined by the redirection process and execute the instruction processing flow of the target instruction; the target instruction is the instruction in the correctly determined instruction address; The redirection module is specifically used for: Determine the instruction exception type of the abnormal instruction; According to the preset processing operation corresponding to the instruction exception type, the redirection process is executed, which includes: re-determining the correct instruction address to obtain the correct instruction.

7. An instruction processing apparatus, wherein, The device includes: The CPU instruction pipeline identifies and sends out abnormal instructions when it detects abnormal instructions during or before the pipeline execution phase. A redirection module responds to an exception identifier sent from the CPU instruction pipeline, identifies the exception type of the exception instruction based on the exception identifier, and performs preset redirection processing to determine the target instruction according to the exception type. During the redirection processing, it prevents the exception instruction from entering the CPU instruction pipeline to terminate the subsequent instruction processing flow for the exception instruction. The target instruction is an instruction at a correctly redefined instruction address. The redirection processing includes: re-determining the correct instruction address to obtain the correct instruction. Preventing the exception instruction from entering the CPU instruction pipeline to terminate the subsequent instruction processing flow for the exception instruction includes: when the decoding module detects the exception instruction, terminating the processing of the exception instruction by the dispatch module, issue module, execution module, and reordering buffer following the decoding module.

8. An electronic device, characterized in that, The electronic device includes: One or more processors; Memory; One or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications being configured to: perform the instruction processing method according to any one of claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the instruction processing method according to any one of claims 1 to 5.

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