Antifuse Array Architecture and Memory

Abstract

Embodiments of the present disclosure relate to the field of semiconductor circuit design, and in particular, to an anti-fuse array architecture and a memory. The anti-fuse array architecture includes: a plurality of anti-fuse memory arrays, wherein different anti-fuse memory arrays are driven based on different clock signals; a first control module, coupled to the plurality of anti-fuse memory arrays, configured to generate a sub-clock signal based on an initial clock signal and a plurality of selection signals, and the sub-clock signal is used to drive a corresponding anti-fuse memory array. By designing a new anti-fuse array architecture, embodiments of the present disclosure can introduce more anti-fuse memory cells with less modification to the logic circuit in the anti-fuse circuit, and are applicable to DRAM chips with increasing integration.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and particularly to an anti-fuse array architecture and a memory. Background Art

[0002] An anti-fuse memory cell is composed of a switching transistor and a fuse transistor. The anti-fuse memory cell includes two states, one is the un-fused state in the normal state, and the other is the fused state after the fuse transistor is broken down. The anti-fuse memory cell constitutes the stored information through different states.

[0003] For the anti-fuse memory cells in a Dynamic Random Access Memory (DRAM), the information stored in the anti-fuse memory cells mainly has three uses: (1) for repairing DRAM columns; (2) for repairing DRAM rows; (3) for DFT (Design for Tesability) testing of the chip.

[0004] Due to the increasing integration of DRAM chips, the requirements for DRAM column repair, DRAM row repair, and chip DFT testing are also continuously increasing, resulting in an increasing demand for the number of anti-fuse memory cells in current DRAM chips.

[0005] Currently, in order to increase the number of anti-fuse memory cells, usually the number of anti-fuse memory cells in the anti-fuse memory array is directly increased. However, for the number of anti-fuse memory cells increased in this way, huge modifications need to be made to the logic circuit in the anti-fuse circuit, which is not suitable for DRAM chips with increasing integration. Summary of the Invention

[0006] Embodiments of the present disclosure provide an anti-fuse array architecture and a memory. By designing a new anti-fuse array architecture, more anti-fuse memory arrays and anti-fuse memory cells are introduced, and the modification to the logic circuit in the anti-fuse circuit is small, which is suitable for DRAM chips with increasing integration.

[0007] Embodiments of the present disclosure provide an anti-fuse array architecture, including: a plurality of anti-fuse memory arrays, wherein different anti-fuse memory arrays are driven based on different clock signals; a first control module, coupled to the plurality of anti-fuse memory arrays, configured to generate a sub-clock signal based on an initial clock signal and a plurality of selection signals, and the sub-clock signal is used to drive a corresponding anti-fuse memory array.

[0008] By increasing the number of antifuse memory arrays and selectively providing sub-clock signals to the antifuse memory arrays to drive them; introducing multiple antifuse memory arrays increases the number of antifuse memory cells, which can be achieved only by controlling the transmission of the sub-clock signals required by the antifuse memory arrays, and is suitable for DRAM chips with increasing integration.

[0009] In addition, the first control module includes: a plurality of cascaded signal selection units, each level of signal selection unit respectively receives a selection signal; wherein, each level of signal selection unit is used to transmit the signal received at the clock signal input end to the clock signal input end of the next-level signal selection unit through the first output end according to the selection signal, and the second output end of each level of signal selection unit is used to output a sub-clock signal according to the selection signal. The clock signal input end of the first-level signal selection unit receives the initial clock signal, and the first output end and the second output end of the last-level signal selection unit are used to output the sub-clock signal; the first control module generates N + 1 sub-clock signals (the first sub-clock signal to the N + 1 sub-clock signal) according to N selection signals (the first selection signal to the Nth selection signal), and each sub-clock signal is used to turn on the corresponding antifuse memory array. Since the N + 1 sub-clock signals are respectively used to control whether the programming of the N + 1 antifuse memory arrays is enabled or not, only one of these N + 1 sub-clock signals is transmitted to the corresponding antifuse memory array at the same time, so as to realize the programming control of a plurality of antifuse arrays, introduce a large number of antifuse memory cells, and only need to control the transmission of the sub-clock signals required by different antifuse memory arrays, which is suitable for DRAM chips with increasing integration.

[0010] In addition, each selection signal includes a first sub-selection signal and a second sub-selection signal that are in opposite phases; the signal selection unit includes: a first selection sub-unit, one input end is used to receive the first sub-selection signal, the other input end is used as the clock signal input end of the signal selection unit, and the output end is used as the first output end of the signal selection unit; a second selection sub-unit, one input end is used to receive the second sub-selection signal, the other input end is used as the clock signal input end of the signal selection unit, and the output end is used as the second output end of the signal selection unit; since the first sub-selection signal and the second sub-selection signal are in opposite-phase signals, that is, only one of the first sub-selection signal and the second sub-selection signal is a valid signal, that is, at the same time, only one of the first selection sub-unit and the second selection sub-unit in the same signal selection unit is selected, so as to realize the selection and transmission of the clock signal.

[0011] In addition, the first selection subunit includes a first NAND gate. One input terminal of the first NAND gate receives the first sub-selection signal. The other input terminal of the first NAND gate serves as the clock signal input terminal of the signal selection unit. The output terminal of the first NAND gate serves as the first output terminal of the signal selection unit clock. The second selection subunit includes a second NAND gate. One input terminal of the second NAND gate receives the second sub-selection signal. The other input terminal of the second NAND gate serves as the clock signal input terminal of the signal selection unit. The output terminal of the second NAND gate serves as the second output terminal of the signal selection unit clock.

[0012] In addition, each anti-fuse memory array includes a second control unit. The second control unit is configured to generate an internal enable signal based on a programming enable signal, a positioning signal, and a sub-clock signal. Among them, the programming enable signal is used to start programming of the anti-fuse memory array. The positioning signal is used to locate the position of the target anti-fuse memory cell in the anti-fuse memory array. The internal enable signal is used to enable the anti-fuse memory array to start programming.

[0013] In addition, the internal enable signal includes: a repair packet enable signal, which is used to enable the repair packet to provide the function of user self-programming; an external command enable signal, which is used to enable an external pin to input a command signal to the anti-fuse memory array; a logic circuit enable signal, which is used to enable the internal logic circuit of the anti-fuse memory array; a positioning check enable signal, which is used to enable the positioning matching check circuit.

[0014] In addition, the number of anti-fuse memory arrays is one less than the number of signal selection units; so that each generated sub-clock signal can be selected to drive the corresponding anti-fuse memory array.

[0015] In addition, the number of anti-fuse memory arrays is 3, and the number of signal selection units is 2.

[0016] The embodiments of the present disclosure also provide a memory. The anti-fuse memory arrays in the memory are set based on the anti-fuse array architecture provided in the above embodiments. By designing a new anti-fuse array architecture, more anti-fuse memory arrays and anti-fuse memory cells are introduced, and the modification of the logic circuit in the anti-fuse circuit is small, which is suitable for DRAM chips with increasing integration.

[0017] In addition, the memory includes a first pin and a second pin. The first pin is used to receive the first sub-selection signal, and the second pin is used to receive the second sub-selection signal. Brief Description of the Drawings

[0018] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplary illustrations do not constitute a limitation on the embodiments. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. To more clearly illustrate the technical solutions in the embodiments of the present disclosure or in the prior art, the drawings required to be used in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 FIG. is a schematic structural diagram of an anti-fuse array architecture provided by an embodiment of the present disclosure;

[0020] Figure 2 FIG. is a schematic structural diagram of a first control module provided by an embodiment of the present disclosure;

[0021] Figure 3 FIG. is a schematic structural diagram of a signal selection unit provided by an embodiment of the present disclosure;

[0022] Figure 4 FIG. is a specific schematic structural diagram of a signal selection unit provided by an embodiment of the present disclosure;

[0023] Figure 5 FIG. is a schematic structural diagram of a second control module provided by an embodiment of the present disclosure;

[0024] Figure 6 FIG. is a schematic structural diagram of an anti-fuse storage array in a memory provided by another embodiment of the present disclosure. Detailed Embodiments

[0025] As known from the background art, for the anti-fuse storage cells in a Dynamic Random Access Memory (DRAM), the information stored in the anti-fuse storage cells mainly has three uses: (1) for repairing DRAM columns; (2) for repairing DRAM rows; (3) for DFT (Design for Tesability) testing of the chip. Due to the increasing integration of DRAM chips, the requirements for DRAM column repair, DRAM row repair, and chip DFT testing are also continuously increasing, resulting in an increasing demand for the number of anti-fuse storage cells in DRAM chips currently. Currently, in order to increase the number of anti-fuse storage cells, usually, the number of anti-fuse storage cells in the anti-fuse storage array is directly increased. However, for the number of anti-fuse storage cells increased by this method, a huge modification to the logic circuit in the anti-fuse circuit is required, which is not suitable for DRAM chips with increasing integration.

[0026] One embodiment of the present disclosure provides an anti-fuse array architecture. By designing a new anti-fuse array architecture, more anti-fuse memory arrays and anti-fuse memory cells are introduced, and the modification to the logic circuit in the anti-fuse circuit is relatively small, which is applicable to DRAM chips with increasing integration.

[0027] Those of ordinary skill in the art can understand that in various embodiments of the present disclosure, many technical details are presented to help readers better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation on the specific implementation manner of the present disclosure. Each embodiment can be combined with each other and cross-referenced on the premise of no contradiction.

[0028] Figure 1 is a schematic structural diagram of the anti-fuse array architecture provided in this embodiment. Figure 2 is a schematic structural diagram of the first control module provided in this embodiment. Figure 3 is a schematic structural diagram of the signal selection unit provided in this embodiment. Figure 4 is a specific schematic structural diagram of the signal selection unit provided in this embodiment. Figure 5 is a schematic structural diagram of the second control module provided in this embodiment. The anti-fuse array architecture provided in this embodiment will be described in detail below with reference to the accompanying drawings as follows:

[0029] Refer to Figure 1 , the anti-fuse array architecture includes:

[0030] A plurality of anti-fuse memory arrays 100, wherein different anti-fuse memory arrays are driven based on different clock signals.

[0031] A first control module 101, coupled to the plurality of anti-fuse memory arrays 100, configured to generate a sub-clock signal based on an initial clock signal and a plurality of selection signals, and the sub-clock signal is used to drive a corresponding anti-fuse memory array.

[0032] It should be noted that the above-mentioned "coupled" can be set as a direct connection or an indirect connection in specific applications. This embodiment does not constitute a limitation on whether the first control module 101 is directly connected to the plurality of anti-fuse memory arrays 100 or the first control module 101 is indirectly connected to the plurality of anti-fuse memory arrays 100.

[0033] In this embodiment, by increasing the number of antifuse memory arrays and selectively providing sub-clock signals to the antifuse memory arrays to drive them; introducing multiple antifuse memory arrays increases the number of antifuse memory cells in a time-sharing manner, which can be achieved only by controlling the transmission of the sub-clock signals required by the antifuse memory arrays, and is applicable to DRAM chips with increasing integration levels.

[0034] Reference Figure 1 and in combination with Figure 2 , the first control module 100 includes: a plurality of cascaded signal selection units, and each stage of the signal selection units respectively receives a selection signal.

[0035] Specifically, each stage of the signal selection unit is configured to transmit the signal received at the clock signal input end to the clock signal input end of the next stage of the signal selection unit through the first output end according to the selection signal. The second output end of each stage of the signal selection unit is configured to output a sub-clock signal according to the selection signal. The clock signal input end of the first stage of the signal selection unit receives an initial clock signal, and the first output end and the second output end of the last stage of the signal selection unit are configured to output a sub-clock signal.

[0036] It should be noted that the above-mentioned "cascaded" means that a plurality of signal selection units are respectively used as the first-stage signal selection unit, the second-stage signal selection unit... the (N-1)-th stage signal selection unit and the N-th stage signal selection unit, and the first-stage signal selection unit, the second-stage signal selection unit... the (N-1)-th stage signal selection unit and the N-th stage signal selection unit are connected in sequence.

[0037] In one example, reference Figure 2, the clock signal input terminal of the first-level signal selection unit 201 is used to receive the initial clock signal, and the first output terminal is connected to the clock signal input terminal of the second-level signal selection unit 202; the first-level signal selection unit 201 is configured to select and output the first sub-clock signal based on the first selection signal, or transmit the clock signal to the second-level signal selection unit 202. The first sub-clock signal is used as the clock signal of an anti-fuse memory array to drive the corresponding anti-fuse memory array; the first output terminal of the second-level signal selection unit 202 is connected to the clock signal input terminal of the third-level signal selection unit 203; the second-level signal selection unit 202 is configured to select and output the second sub-clock signal based on the second selection signal, or transmit the clock signal to the third-level signal selection unit 203. The second sub-clock signal is used as the clock signal of an anti-fuse memory array to drive the corresponding anti-fuse memory array; the first output terminal of the third-level signal selection unit 203 is connected to the signal input terminal of the fourth-level signal selection unit (not shown); the first output terminal of the (N-1)-th level signal selection unit (not shown) is connected to the signal input terminal of the N-th level signal selection unit 20N; the N-th level signal selection unit 20N is configured to select and output the N-th sub-clock signal or the (N+1)-th sub-clock signal based on the N-th selection signal. The N-th sub-clock signal and the (N+1)-th sub-clock signal are respectively used as the clock signals of an anti-fuse memory array to drive the corresponding anti-fuse memory array.

[0038] As can be seen from the above, the first control module 100 generates N+1 sub-clock signals (the first sub-clock signal to the (N+1)-th sub-clock signal) according to N selection signals (the first selection signal to the N-th selection signal). Each sub-clock signal is used to drive the corresponding anti-fuse memory array. The N+1 sub-clock signals are respectively used to control whether to program and enable the N+1 anti-fuse memory arrays. And at the same moment, only one of the N+1 sub-clock signals is transmitted to the corresponding anti-fuse memory array, so as to realize the programming control of a plurality of anti-fuse arrays, and only by controlling the transmission of the sub-clock signals required by the anti-fuse memory arrays, it is applicable to DRAM chips with increasing integration.

[0039] Based on the above discussion, in some embodiments, the number of anti-fuse memory arrays is one less than the number of signal selection units, so that each generated sub-clock signal can be selected to drive the corresponding anti-fuse memory array.

[0040] Specifically, in some embodiments, the number of anti-fuse memory arrays is 3, and the number of signal selection units is 2.

[0041] For the selection signals of the signal selection unit, specifically refer to Figure 3, each selection signal includes a first sub-selection signal and a second sub-selection signal that are in anti-phase with each other. The signal selection unit includes: a first selection unit 301, one input terminal for receiving the first sub-selection signal, the other input terminal being the clock signal input terminal of the signal selection unit, and the output terminal being the first output terminal of the signal selection unit; a second selection unit 302, one input terminal for receiving the second sub-selection signal, the other input terminal being the clock signal input terminal of the signal selection unit, and the output terminal being the second output terminal of the signal selection unit.

[0042] The first sub-selection signal and the second sub-selection signal are in anti-phase with each other. At the same moment, only one of the first selection sub-unit and the second selection sub-unit in the same signal selection unit is selected, so as to realize the selection and transmission of the clock signal.

[0043] In some embodiments, referring to Figure 4 , the first selection sub-unit includes a first NAND gate 311. One input terminal of the first NAND gate 311 receives the first sub-selection signal, the other input terminal of the first NAND gate 311 is used as the clock signal input terminal of the signal selection unit, and the output terminal of the first NAND gate 311 is used as the first output terminal of the signal selection unit; the second selection unit includes a second NAND gate 312. One input terminal of the second NAND gate 312 receives the second sub-selection signal, the other input terminal of the second NAND gate 312 is used as the book signal input terminal of the signal selection unit, and the output terminal of the second NAND gate 312 is used as the second output terminal of the signal selection unit.

[0044] Specifically, when the first sub-selection signal of one-level signal selection unit is at a high level, the second sub-selection signal is at a low level. At this time, the output terminal of the first NAND gate of this signal selection unit outputs a word clock signal to the corresponding antifuse memory array, and the output terminal of the second NAND gate only outputs a high-level signal. The first sub-selection signals of the remaining signal selection units are at a low level, and the second sub-selection signals are at a high level. That is, the first selection sub-unit that receives the low-level first sub-selection signal does not output a clock signal, and the second NAND gate that receives the high-level second sub-selection signal outputs the clock signal it receives or outputs a low-level signal to the next level, so that the clock signal output by the second selection sub-unit of the previous-level signal selection unit can be transmitted to the next-level signal selection unit, thereby performing the selection of the sub-clock signal.

[0045] Based on the above principle, in some other embodiments, the first selection unit and the second selection unit can also be implemented based on an AND gate. Specifically, the first selection sub-unit includes a first AND gate. One input terminal of the first AND gate receives the first sub-selection signal, another input terminal of the first AND gate serves as the clock signal input terminal of the signal selection unit, and the output terminal of the first AND gate serves as the first output terminal of the signal selection unit; the second selection unit includes a second AND gate. One input terminal of the second AND gate receives the second sub-selection signal, another input terminal of the second AND gate serves as the book signal input terminal of the signal selection unit, and the output terminal of the second AND gate serves as the second output terminal of the signal selection unit.

[0046] In some embodiments, referring to Figure 5 , in the anti-fuse array architecture, each anti-fuse memory array further includes a second control unit, and the second control unit is configured to generate an internal enable signal based on a programming enable signal, a positioning signal, and a sub-clock signal, where the programming enable signal is used to start programming the anti-fuse memory array, the positioning signal is used to locate the position of the target anti-fuse memory cell in the anti-fuse memory array, and the internal enable signal is used to enable the anti-fuse memory array to start programming.

[0047] In some embodiments, the internal enable signal includes: a repair package enable signal for enabling the repair package to provide the function of user self-programming; an external command enable signal for enabling an external pin to input a command signal to the anti-fuse memory array; a logic circuit enable signal for enabling the internal logic circuit of the anti-fuse memory array; a positioning check enable signal for enabling the positioning matching check circuit.

[0048] In this embodiment, by increasing the number of anti-fuse memory arrays and selectively providing sub-clock signals to the anti-fuse memory arrays to drive the anti-fuse memory arrays; introducing multiple anti-fuse memory arrays increases the number of anti-fuse memory cells and is only achieved by controlling the transmission of the sub-clock signals required by the anti-fuse memory arrays, which is applicable to DRAM chips with increasing integration.

[0049] All units involved in this embodiment are logical units. In practical applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of the present disclosure, units not closely related to solving the technical problems proposed by the present disclosure are not introduced in this embodiment, but this does not mean that there are no other units in this embodiment.

[0050] It should be noted that the features disclosed in the anti-fuse array architecture provided in the above embodiments can be arbitrarily combined without conflict to obtain new embodiments of the anti-fuse array architecture.

[0051] Another embodiment of the present disclosure provides a memory. The antifuse memory array in the memory is arranged based on the antifuse array architecture provided in the above embodiment. By designing a new antifuse array architecture, more antifuse memory arrays and antifuse memory cells can be introduced, and the modification to the logic circuit in the antifuse circuit is relatively small, which is suitable for DRAM chips with increasing integration.

[0052] Figure 6 FIG. 4 is a schematic structural diagram of the antifuse memory array in the memory provided in this embodiment. The memory provided in this embodiment will be described in detail below with reference to the accompanying drawings, specifically as follows:

[0053] The memory can be a storage unit or device based on semiconductor devices or components. For example, the memory device can be a volatile memory, such as a dynamic random access memory DRAM, a synchronous dynamic random access memory SDRAM, a double data rate synchronous dynamic random access memory DDR SDRAM, a low power double data rate synchronous dynamic random access memory LPDDR SDRAM, a graphics double data rate synchronous dynamic random access memory GDDR SDRAM, a double data rate type double synchronous dynamic random access memory DDR2 SDRAM, a double data rate type three synchronous dynamic random access memory DDR3 SDRAM, a double data rate fourth generation synchronous dynamic random access memory DDR4 SDRAM, a thyristor random access memory TRAM, etc.; or it can be a non-volatile memory, such as a phase change random access memory PRAM, a magnetic random access memory MRAM, a resistive random access memory RRAM, etc.

[0054] It should be noted that this embodiment takes the number of antifuse memory arrays as 3 and the number of signal selection units as 2 as an example for specific illustration, which does not constitute a limitation to this embodiment. In other embodiments, the number of antifuse memory arrays can be extended to N + 1, and the number of signal selection units can be extended to N.

[0055] Specifically, the memory includes a first pin and a second pin. The first pin is used to receive a first sub-selection signal, and the second pin is used to receive a second sub-selection signal.

[0056] Among them, the first pin and the second pin can be the BA0 pin and the BA0_N pin, or can be composed of the A17 pin and the A17 pin connected to an inverter.

[0057] Specifically, refer to Figure 6, the memory receives an initial clock signal based on the ACTB pin and the CSB pin, and the initial clock signal is transmitted to the first-stage signal selection unit; the first-stage signal selection unit is configured to receive the initial clock signal, and based on the BA0 pin, receive a first sub-selection signal, and based on the BA0_N pin, receive a second sub-selection signal. The first-stage signal selection unit outputs an intermediate clock signal CLK_LC based on the first sub-selection signal, or outputs a first sub-clock signal CLK_R based on the second sub-selection signal. The first sub-clock signal CLK_R is a clock signal for turning on the first antifuse memory array; the second-stage signal selection unit is configured to receive the intermediate clock signal CLK_LC, and based on the A17 pin, receive a first sub-selection signal, and based on the A17 pin, connect to an inverter to receive a second sub-selection signal. The second-stage signal selection unit outputs a second sub-clock signal CLK_L based on the first sub-selection signal, and outputs a third sub-clock signal CLK_C based on the second sub-selection signal. The second sub-clock signal CLK_L is a clock signal for turning on the second antifuse memory array, and the third sub-clock signal CLK_C is a clock signal for turning on the third antifuse memory array.

[0058] Since the first sub-clock signal CLK_R, the second sub-clock signal CLK_L, and the third sub-clock signal CLK_C are respectively used to control whether the first antifuse memory array, the second antifuse memory array, and the third antifuse memory array are programmed to be turned on or off, only one of these three signals is valid at the same time, that is, only one clock signal is transmitted to the corresponding antifuse memory array at the same moment, so as to realize the programming of a plurality of antifuse arrays, introduce a large number of antifuse memory cells, and it is only necessary to control the transmission of the sub-clock signals required by the antifuse memory arrays, which is applicable to DRAM chips with increasing integration.

[0059] In some embodiments, each antifuse memory array further includes a second control unit, which is configured to generate an internal enable signal based on a programming enable signal, a positioning signal, and a sub-clock signal, where the programming enable signal is used to start programming the antifuse memory array, the positioning signal is used to locate the position of the target antifuse memory cell in the antifuse memory array, and the internal enable signal is used to enable the antifuse memory array to start programming.

[0060] Specifically, the antifuse memory array generates an internal enable signal for controlling various logics inside the antifuse circuit based on the corresponding sub-clock signal, in combination with the positioning signal and the programming enable signal.

[0061] In some embodiments, the internal enable signal includes: a repair packet enable signal for enabling the repair packet to enhance the user-programmable function; an external command enable signal for enabling an external pin to input a command signal to the antifuse memory array; a logic circuit enable signal for enabling the internal logic circuit of the antifuse memory array; and a positioning check enable signal for enabling the positioning matching check circuit.

[0062] In this embodiment, by increasing the number of antifuse memory arrays and selectively providing sub-clock signals to the antifuse memory arrays to drive them; introducing multiple antifuse memory arrays increases the number of antifuse memory cells, which can be achieved only by controlling the transmission of the sub-clock signals required by the antifuse memory arrays, and is applicable to DRAM chips with increasing integration.

[0063] It should be noted that the features disclosed in the memories provided in the above embodiments can be arbitrarily combined without conflict to obtain new memory embodiments.

[0064] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present disclosure, and in practical applications, various changes can be made in form and details without departing from the spirit and scope of the present disclosure.

Claims

1. An anti-fuse array architecture, characterized in that Comprising: A plurality of antifuse memory arrays, wherein different ones of the antifuse memory arrays are driven based on different clock signals; A first control module, coupled to the plurality of antifuse memory arrays, configured to generate a sub-clock signal based on an initial clock signal and a plurality of selection signals, the sub-clock signal being used to drive a corresponding one of the antifuse memory arrays; The first control module includes: a plurality of cascaded signal selection units, each stage of the signal selection units respectively receiving one of the selection signals; Wherein, each stage of the signal selection unit is configured to transmit the signal received at the clock signal input terminal to the clock signal input terminal of the next stage of the signal selection unit through the first output terminal according to the selection signal, the second output terminal of each stage of the signal selection unit is configured to output the sub-clock signal according to the selection signal, the clock signal input terminal of the first stage of the signal selection unit receives the initial clock signal, and the first output terminal and the second output terminal of the last stage of the signal selection unit are configured to output the sub-clock signal according to the selection signal; the sub-clock signal output by each stage of the signal selection unit corresponds to one of the antifuse memory arrays.

2. The anti-fuse array architecture according to claim 1, wherein Each of the selection signals includes a first sub-selection signal and a second sub-selection signal that are in inverse phase to each other; The signal selection unit includes: A first selection sub-unit, one input terminal for receiving the first sub-selection signal, the other input terminal serving as the clock signal input terminal of the signal selection unit, and the output terminal serving as the first output terminal of the signal selection unit; A second selection sub-unit, one input terminal for receiving the second sub-selection signal, the other input terminal serving as the clock signal input terminal of the signal selection unit, and the output terminal serving as the second output terminal of the signal selection unit.

3. The anti-fuse array architecture according to claim 2, wherein Comprising: The first selection sub-unit includes a first NAND gate, one input terminal of the first NAND gate receives the first sub-selection signal, the other input terminal of the first NAND gate serves as the clock signal input terminal of the signal selection unit, and the output terminal of the first NAND gate serves as the first output terminal of the signal selection unit; The second selection sub-unit includes a second NAND gate, one input terminal of the second NAND gate receives the second sub-selection signal, the other input terminal of the second NAND gate serves as the clock signal input terminal of the signal selection unit, and the output terminal of the second NAND gate serves as the second output terminal of the signal selection unit.

4. The anti-fuse array architecture according to any one of claims 1 to 3, characterized in that, Each of the antifuse memory arrays includes a second control unit, the second control unit being configured to generate an internal enable signal based on a programming enable signal, a positioning signal, and the sub-clock signal; Wherein, the programming enable signal is used to start programming of the antifuse memory array, the positioning signal is used to locate the position of a target antifuse memory cell in the antifuse memory array, and the internal enable signal is used to enable the antifuse memory array to start programming.

5. The anti-fuse array architecture according to claim 4, wherein The internal enable signal includes: A repair package enable signal, used to enable the repair package to provide the function of user self-programming; An external command enable signal, used to enable an external pin to input a command signal to the antifuse memory array; A logic circuit enable signal, which is used to enable the internal logic circuit of the antifuse memory array; A positioning check enable signal, which is used to enable the positioning matching check circuit.

6. The anti-fuse array architecture according to claim 1, wherein The number of the antifuse memory arrays is one less than the number of the signal selection units.

7. The anti-fuse array architecture according to claim 6, wherein Comprising: The number of the antifuse memory arrays is 3, and the number of the signal selection units is 2.

8. A memory, characterized in that, The antifuse memory arrays in the memory are arranged based on the antifuse array architecture according to any one of claims 1 to 7.

9. The memory according to claim 8, wherein The memory includes a first pin and a second pin. The first pin is used to receive a first sub-selection signal, and the second pin is used to receive a second sub-selection signal.

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