Semiconductor device and method of forming the same

Abstract

The present application discloses a semiconductor device and a method for forming the same. The forming method includes: providing a substrate, the substrate including a laterally arranged LDMOS region and a CMOS region, and a first isolation layer covering the LDMOS region and the CMOS region, the LDMOS region including a first isolation structure, the CMOS region including a second isolation structure, both the first isolation structure and the second isolation structure being higher than the first isolation layer; growing a first barrier layer on the surfaces of the first isolation layer, the first isolation structure, and the second isolation structure; etching the first barrier layer and a part of the first isolation layer to expose a first corner of the first isolation structure, and part of the LDMOS region and part of the first isolation structure on both sides of the first corner; performing an arc treatment on the first corner so that the first corner forms a corresponding rounded corner. The present application can improve the reliability of the obtained semiconductor device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor device and a method for forming the same. Background Art

[0002] The laterally diffused metal-oxide field effect transistor (LDMOS) is a relatively important transistor among power field effect transistors (powerMOSFETs). During the LDMOS design process, the optimization of the surface lateral voltage region is crucial, which directly affects the performance of the corresponding transistor. The LDMOS should have a laterally resistant voltage region with a sufficiently long length and a low doping concentration to obtain the required high breakdown voltage, but this will increase the cell size of the device and the on-resistance during current conduction. One of the keys to optimizing the surface lateral resistant voltage region is to suppress the curvature effect of the PN junction. In actual power semiconductor devices, not all PN junctions are planar junctions. The junction surface of the PN junction is usually a curved surface. According to Gauss's theorem, the smaller the radius of curvature, the higher the electric field strength. There is an electric field peak at the position with a small radius of curvature on the junction surface, where avalanche breakdown is likely to occur. The inventor conducted research on related transistors and found that in some LDMOSs formed by certain solutions, although the lateral resistant voltage region is optimized to a certain extent, the leakage current in the corresponding CMOS (Complementary Metal Oxide Semiconductor) region is likely to increase, resulting in low reliability. Summary of the Invention

[0003] In view of this, this application provides a semiconductor device and a method for forming the same to solve the problem that the leakage current in the corresponding CMOS region of the LDMOS formed by some solutions is likely to increase.

[0004] This application provides a method for forming a semiconductor device, including:

[0005] Providing a substrate, the substrate includes a laterally arranged LDMOS region and a CMOS region, and a first isolation layer covering the LDMOS region and the CMOS region. The LDMOS region includes a first isolation structure, the CMOS region includes a second isolation structure, and both the first isolation structure and the second isolation structure are higher than the first isolation layer;

[0006] Growing a first barrier layer on the surfaces of the first isolation layer, the first isolation structure, and the second isolation structure;

[0007] Etching the first barrier layer and a part of the first isolation layer to expose the first corner of the first isolation structure, and part of the LDMOS region and part of the first isolation structure on both sides of the first corner;

[0008] Perform an arcuation process on the first corner to form a corresponding rounded corner at the first corner; the method for performing the arcuation process on the first corner further includes: etching the exposed first isolation structure to make the exposed first isolation structure lower than the LDMOS region, and the LDMOS region has a second corner higher than the etched first isolation structure; diffusing from the etched first isolation structure into the LDMOS region to form a rounded corner covering the second corner, and the rounded corner also extends to the first isolation layer.

[0009] Optionally, the method for providing the substrate further includes: providing a substrate, the substrate including an LDMOS region and a CMOS region; forming a first isolation layer on the surface of the substrate; forming a second barrier layer on the first isolation layer, the second barrier layer including a first opening for forming the first isolation structure and a second opening for forming the second isolation structure; etching the first isolation layer and the substrate using the second barrier layer as a mask to obtain a first groove corresponding to the first opening and a second groove corresponding to the second opening; forming a first isolation structure in the first groove and a second isolation structure in the second groove; removing the second barrier layer.

[0010] Optionally, forming the first isolation structure in the first groove and the second isolation structure in the second groove includes: depositing isolation materials in the first groove and the second groove respectively to obtain the first isolation structure and the second isolation structure.

[0011] Optionally, the first barrier layer includes a first protrusion above the first isolation structure and a second protrusion above the second isolation structure, and two ends of the first protrusion respectively extend above the LDMOS region, and two ends of the second protrusion respectively extend above the CMOS region.

[0012] Optionally, the method for etching the first barrier layer and a part of the first isolation layer further includes: forming a mask layer on the surface of the first barrier layer, and the mask layer exposes a part of the first barrier layer above the first corner; etching the first barrier layer and the first isolation layer using the mask layer as a mask.

[0013] Optionally, etching the exposed LDMOS region includes: etching the exposed first isolation structure using DHF acid.

[0014] Optionally, the DHF acid is also used to etch the second corner into a rounded corner when etching the first isolation structure.

[0015] Optionally, the first isolation layer includes an oxide layer; the materials of the first barrier layer and the second barrier layer are the same.

[0016] Optionally, after the first corner is rounded, the forming method further includes: removing the first barrier layer.

[0017] Optionally, the first corner includes two corners of the first isolation structure adjacent to the LDMOS region respectively.

[0018] The present application also provides a semiconductor device formed by using the forming method of the semiconductor device according to any one of the above embodiments. The semiconductor device includes:

[0019] A substrate, the substrate includes an LDMOS region and a CMOS region. The LDMOS region includes a first isolation structure, and the CMOS region includes a second isolation structure. The second isolation structure is higher than the CMOS region;

[0020] A first isolation layer located on the surface of the substrate, the first isolation layer is lower than the second isolation structure. The first isolation structure includes a rounded corner, and the rounded corner extends towards the LDMOS region to the first isolation layer.

[0021] For the above semiconductor device and its forming method, by providing a substrate including a laterally arranged LDMOS region and a CMOS region, and a first isolation layer covering the LDMOS region and the CMOS region, growing a first barrier layer on the surfaces of the first isolation layer, the first isolation structure and the second isolation structure, etching the first barrier layer and a part of the first isolation layer to expose the first corner of the first isolation structure, and part of the LDMOS region and part of the first isolation structure on both sides of the first corner, rounding the first corner so that the first corner forms a corresponding rounded corner, making the angle between the first isolation structure and the LDMOS region smooth, forming the required field plate structure, achieving the purpose of optimizing the breakdown voltage performance of the first isolation structure; during the above rounding process, there is no need to etch the second isolation structure, and the second isolation structure in the corresponding semiconductor structure is also higher than the CMOS regions on both sides of it, which can reduce the risk of excessive leakage current in the CMOS region and improve the reliability of the obtained LDMOS transistor. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0023] Figure 1a , Figure 1b , Figure 1c , Figure 1d , Figure 1e and Figure 1fSchematic diagram of the structure during the formation process of related semiconductor devices;

[0024] Figure 2 Flowchart of the method for forming a semiconductor device in an embodiment of the present application;

[0025] Figure 3a 、 Figure 3b 、 Figure 3c and Figure 3d Schematic diagrams of the structures obtained in each step in an embodiment of the present application;

[0026] Figure 4a 、 Figure 4b 、 Figure 4c 、 Figure 4d and Figure 4e Schematic diagrams of the structures obtained in related steps in an embodiment of the present application;

[0027] Figure 5 The schematic diagram shown is the schematic diagram of the structure obtained in related steps in an embodiment of the present application;

[0028] Figure 6 The schematic diagram shown is the schematic diagram of the structure obtained in related steps in an embodiment of the present application;

[0029] Figure 7 The schematic diagram shown is the schematic diagram of the structure obtained in related steps in an embodiment of the present application. Detailed implementation manners

[0030] The inventors' research found that an LDMOS (laterally-diffused metal-oxide semiconductor) transistor can be formed through the following S11 to S16. S11, first form a substrate (P-sub) and an oxide layer (Pad oxide). As Figure 1a shown, the substrate includes an LDMOS region and a CMOS (Complementary Metal Oxide Semiconductor) region. A first isolation structure needs to be set in the LDMOS region, and a second isolation structure needs to be set in the CMOS region. S12, form a first barrier layer (such as a SIN layer) for forming the first isolation structure and the second isolation structure on the surface of the substrate. Using the first barrier layer as a mask, etch the oxide layer and the substrate downward to obtain a first groove for forming the first isolation structure and a second groove for forming the second isolation structure. Form the first isolation structure in the first groove and the second isolation structure in the second groove, and continue to etch the first isolation structure and the second isolation structure until part of the first isolation structure and the second isolation structure are removed. Refer to Figure 1bAs shown, the etched first isolation structure and second isolation structure are respectively lower than the oxide layer, with a certain step height between them and the oxide layer. S13, refer to Figure 1c As shown, remove the remaining first barrier layer. S14, refer to Figure 1d As shown, deposit a second barrier layer (such as a SIN layer) covering the oxide layer, the LDMOS region, and the CMOS region. The thickness of the second barrier layer on the surfaces of the oxide layer, the first isolation structure, and the second isolation structure is the same. S15, refer to Figure 1e As shown, etch downward at the junction of the LDMOS region and the active region to expose the corner between the LDMOS region and the first isolation structure, as well as the surfaces of the active region and the LDMOS region on both sides of the corner. S16, refer to Figure 1f As shown, diffuse to form a rounded corner at the above-mentioned corner, making the angle between the LDMOS region and the active region smoother, thereby obtaining the corresponding LDMOS transistor. The inventor found that the above solution is likely to reduce the step height of the CMOS region as well. Due to the large deviation of the electrical parameters in the CMOS region, the leakage current is likely to increase, thus affecting the reliability of the LDMOS transistor.

[0031] To address the above problems, in the process of this application without adding a photolithography layer, only the step height of the first isolation structure in the LDMOS region is etched off, making the angle (Corner) at the junction of the formed bird's beak and the LDMOS region smoother, and the step of the second isolation structure in the CMOS region is protected, reducing the risk of excessive leakage current in the CMOS region and improving the reliability of the obtained LDMOS transistor.

[0032] Next, in conjunction with the accompanying drawings, the technical solutions in the embodiments of this application will be described clearly and completely. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application. Without conflict, the following various embodiments and their technical features can be combined with each other.

[0033] This application provides a method for forming a semiconductor device in a first aspect, refer to Figures 2 to 3d As shown, the forming method includes S210 to S240.

[0034] S210, provide a substrate, refer to Figure 3aAs shown, the horizontally arranged LDMOS regions 310 and CMOS regions 320, and the first isolation layer 330 covering the LDMOS regions 310 and CMOS regions 320. The LDMOS region 310 includes a first isolation structure 311, the CMOS region 320 includes a second isolation structure 321, and both the first isolation structure 311 and the second isolation structure 321 are higher than the first isolation layer 330.

[0035] The above LDMOS region 310 is used to form an LDMOS device. The operating voltage of the LDMOS device is relatively high, and the isolation performance requirements for the first isolation structure 311 are relatively high. The above CMOS region 320 is used to form a CMOS device. The obtained second isolation structure 321 is higher than the first isolation layer 330, that is, higher than the corresponding CMOS region 320, which can reduce the risk of excessive leakage current in the CMOS region 320.

[0036] Optionally, the first isolation structure 311 can be used to provide isolation functions in a high-voltage environment. Optionally, the first isolation layer 330 includes a layer structure with isolation functions such as an oxide layer. The first barrier layer can be made of materials such as SIN (silicon nitride).

[0037] In one example, the method for providing the substrate further includes S211 to S216.

[0038] S211, as Figure 4a shown, provide a substrate 300, and the substrate 300 includes an LDMOS region 310 and a CMOS region 320.

[0039] S212, as Figure 4b shown, form a first isolation layer 330 on the surface of the substrate 300.

[0040] S213, as Figure 4c shown, form a second barrier layer 340 on the first isolation layer 330. The second barrier layer 340 includes a first opening 341 for forming the first isolation structure 311 and a second opening 342 for forming the second isolation structure 321. Optionally, the second barrier layer 340 can include materials such as SIN (silicon nitride) that can form a corresponding mask layer.

[0041] S214, using the second barrier layer 340 as a mask to etch the first isolation layer 330 and the substrate 300, as Figure 4d shown, to obtain a first groove 341a corresponding to the first opening 341 and a second groove 342a corresponding to the second opening 342.

[0042] S215, as Figure 4eAs shown, a first isolation structure 311 is formed in the first groove 341a, and a second isolation structure 321 is formed in the second groove 342a.

[0043] S216, removing the second barrier layer 340 to obtain Figure 3a the substrate shown.

[0044] Optionally, the LDMOS region 310 and the CMOS region 320 can be formed by injecting corresponding ions into the corresponding regions of the semiconductor layer and other methods.

[0045] Optionally, in S215, forming the first isolation structure 311 in the first groove 341a and the second isolation structure 321 in the second groove 342a includes: depositing isolation materials in the first groove 341a and the second groove 342a respectively to obtain the first isolation structure 311 and the second isolation structure 321 whose surfaces are higher than the first isolation layer 330, so as to ensure the quality of the obtained first isolation structure 311 and second isolation structure 321. Optionally, the isolation material includes materials with isolation functions such as oxides.

[0046] S220, referring to Figure 3b As shown, a first barrier layer 410 is grown on the surface of the first isolation layer 20, the first isolation structure 311 and the second isolation structure. The first barrier layer 410 can include materials such as SIN that can form corresponding mask layers. Optionally, the material of the first barrier layer 410 can be the same as that of the second barrier layer 340. For example, both can use materials such as SIN.

[0047] Optionally, the first barrier layer 410 includes a first protrusion 311a above the first isolation structure 311 and a second protrusion 321a above the second isolation structure 321. The two ends of the first protrusion 311a respectively extend above the LDMOS region 310, and the two ends of the second protrusion 321a respectively extend above the CMOS region 320, so as to simplify the process of growing the first barrier layer 410.

[0048] S230, referring to Figure 3c As shown, etching the first barrier layer 410 and a part of the first isolation layer 330 exposes the first corner 311b of the first isolation structure 311, and a part of the LDMOS region 310 and a part of the first isolation structure 311 on both sides of the first corner 311b.

[0049] Optionally, in step S230, a process such as dry etching can be used to etch the first barrier layer 410 to improve the etching accuracy. Optionally, the first corner 311b includes corners where the corresponding breakdown voltage performance needs to be optimized. For example, the first corner 311b includes the corner on one side of the first isolation structure 311; or for another example, the first corner 311b can also include two corners respectively close to the LDMOS region 311 on both sides of the first isolation structure 311, so as to perform arc-shaped processing on the corners on both sides of the first isolation structure 311 respectively, and simultaneously improve the breakdown voltage performance at the corners on both sides of the first isolation structure 311.

[0050] In one example, the method for etching the first barrier layer 410 and a part of the first isolation layer 330 further includes S231 and S232.

[0051] S231, as shown in Figure 5 shown, a mask layer 420 is formed on the surface of the first barrier layer 410, and the mask layer 420 exposes a part of the first barrier layer 410 above the first corner 311b; specifically, the mask layer 420 includes a third opening 421, and the third opening 421 exposes a part of the first barrier layer 410 above the first corner 311b. Optionally, the size of the third opening 421 can be set according to the performance characteristics of the corresponding semiconductor device, so that after subsequent related processes, the first corner 311b can be fully exposed, and the size of the exposed LDMOS region 310 is not too large, achieving the purpose of controlling the size of the corresponding semiconductor device.

[0052] S232, using the mask layer 420 as a mask to etch the first barrier layer 410 and the first isolation layer 330, exposing the first corner 311b of the first isolation structure 311, as well as part of the LDMOS region 310 and part of the first isolation structure 311 on both sides of the first corner 311b, to obtain Figure 3d the structure shown.

[0053] S240, as shown in Figure 3d shown, arc-shaped processing is performed on the first corner 311b so that the first corner 311b forms a corresponding rounded corner to optimize the breakdown voltage performance of the first corner 311b.

[0054] Optionally, step S240 can be implemented by processes such as diffusion process, oxidizing the LDMOS region 310 or oxidizing exogenous silicon to perform arc-shaped processing so that the first corner 311b forms a corresponding rounded corner.

[0055] In one example, the method for performing arc-shaped processing on the first corner 311b so that the first corner 311b forms a corresponding rounded corner further includes S241 and S242.

[0056] S241, as shown inFigure 6 As shown, etch the exposed first isolation structure 311 so that the exposed first isolation structure 311 is lower than the LDMOS region 310, and the LDMOS region 310 has a second corner 310a higher than the etched first isolation structure 310.

[0057] S242, diffuse from the etched first isolation structure 311 into the LDMOS region 310 to form a rounded corner covering the second corner 310a, and the rounded corner also extends to the first isolation layer 330 to achieve the rounding process of the first corner 311b.

[0058] Optionally, the temperature range of the above diffusion process may include 800°C to 1000°C. For example, the temperature of the diffusion process may be 800°C, 850°C, 875°C, or 1000°C, etc.

[0059] Optionally, etching the exposed LDMOS region 310 includes: etching the exposed first isolation structure 311 with DHF acid to simplify the etching process and reduce the etching cost.

[0060] Optionally, the DHF acid is also used to etch the second corner 310a into a rounded corner when etching the first isolation structure 311, so that the finally formed rounded corner has a larger radian and stronger voltage withstand performance.

[0061] In one embodiment, after the rounding process at the first corner 11b, the forming method further includes: referring to Figure 7 As shown, remove the first barrier layer 410 to perform other processes on the corresponding semiconductor device to obtain the corresponding LDMOS transistor.

[0062] The method for forming the above semiconductor device includes providing a substrate including laterally arranged LDMOS regions 310 and CMOS regions 320, and a first isolation layer 330 covering the LDMOS regions 310 and CMOS regions 320. A first barrier layer 410 is grown on the surfaces of the first isolation layer 330, the first isolation structure 311, and the second isolation structure 321. The first barrier layer 410 and a part of the first isolation layer 330 are etched to expose the first corner 311b of the first isolation structure 311, and part of the LDMOS regions 310 and part of the first isolation structure 311 on both sides of the first corner 311b. The first corner 311b is rounded to form a corresponding rounded corner, so that the angle between the first isolation structure 311 and the LDMOS region 311 is smoothed, forming the required field plate structure, achieving the purpose of optimizing the breakdown voltage performance of the first isolation structure 311. During the above rounding process, the second isolation structure 321 does not need to be etched, and the second isolation structure 321 in the corresponding semiconductor structure is also higher than the CMOS regions 320 on both sides thereof, which can reduce the risk of excessive leakage current in the CMOS regions 320 and improve the reliability of the obtained LDMOS transistors.

[0063] In a second aspect, the present application provides a semiconductor device formed by using the method for forming a semiconductor device according to any of the above embodiments. The semiconductor device includes:

[0064] A substrate, the substrate includes LDMOS regions and CMOS regions, the LDMOS regions include a first isolation structure, the CMOS regions include a second isolation structure, and the second isolation structure is higher than the CMOS regions;

[0065] A first isolation layer located on the surface of the substrate, the first isolation layer is lower than the second isolation structure, and the first isolation structure includes a rounded corner that extends into the LDMOS regions to the first isolation layer.

[0066] The above semiconductor device is formed by using the method for forming a semiconductor device according to any of the above embodiments, and has all the beneficial effects of the method for forming a semiconductor device according to any of the above embodiments, which will not be elaborated here.

[0067] Although the present application has been shown and described with respect to one or more implementations, those skilled in the art will envision equivalent variations and modifications based on reading and understanding this specification and the drawings. The present application includes all such modifications and variations and is limited only by the scope of the appended claims. In particular, with respect to the various functions performed by the above components, the terms used to describe such components are intended to correspond to any component that performs the specified function of the component (e.g., it is functionally equivalent), unless otherwise indicated, even if the structure is not necessarily identical to the disclosed structure that performs the function in the exemplary implementations of the present specification shown herein.

[0068] That is to say, the above description is only an embodiment of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made by using the content of the specification and drawings of the present application, such as the mutual combination of technical features between various embodiments, or directly or indirectly applied in other related technical fields, shall be equally included in the patent protection scope of the present application.

[0069] In addition, in the description of the present application, it should be understood that the orientation or positional relationship indicated by terms such as "center", "longitudinal", "transverse", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus cannot be understood as a limitation to the present application. In addition, for structural elements with the same or similar characteristics, the present application may use the same or different reference numerals for identification. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "a plurality" is two or more, unless otherwise specifically defined.

[0070] In the present application, the term "exemplary" is used to mean "serving as an example, illustration, or explanation". Any embodiment described as "exemplary" in the present application is not necessarily to be construed as more preferred or more advantageous than other embodiments. The above description is given in order to enable any person skilled in the art to implement and use the present application. In the above description, various details are set forth for purposes of explanation. It should be understood by those of ordinary skill in the art that the present application can be implemented without using these specific details. In other embodiments, well-known structures and processes will not be elaborated in detail so as not to obscure the description of the present application with unnecessary details. Therefore, the present application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope that conforms to the principles and features disclosed in the present application.

Claims

1. A method for forming a semiconductor device, characterized in that, The forming method includes: Providing a substrate, the substrate including a laterally arranged LDMOS region and a CMOS region, and a first isolation layer covering the LDMOS region and the CMOS region, the LDMOS region including a first isolation structure, the CMOS region including a second isolation structure, both the first isolation structure and the second isolation structure being higher than the first isolation layer; Growing a first barrier layer on the surfaces of the first isolation layer, the first isolation structure and the second isolation structure; Etching the first barrier layer and a part of the first isolation layer to expose a first corner of the first isolation structure, and a part of the LDMOS region and a part of the first isolation structure on both sides of the first corner; Performing a rounding process on the first corner so that the first corner forms a corresponding rounded corner; the method for performing the rounding process on the first corner further includes: etching the exposed first isolation structure to make the exposed first isolation structure lower than the LDMOS region, the LDMOS region having a second corner higher than the etched first isolation structure; diffusing from the etched first isolation structure into the LDMOS region to form a rounded corner covering the second corner, and the rounded corner also extending to the first isolation layer.

2. The method for forming a semiconductor device according to claim 1, wherein The method for providing the substrate further includes: Providing a substrate, the substrate including an LDMOS region and a CMOS region; Forming a first isolation layer on the surface of the substrate; Forming a second barrier layer on the first isolation layer, the second barrier layer including a first opening for forming the first isolation structure and a second opening for forming the second isolation structure; Etching the first isolation layer and the substrate using the second barrier layer as a mask to obtain a first groove corresponding to the first opening and a second groove corresponding to the second opening; Forming a first isolation structure in the first groove and a second isolation structure in the second groove; Removing the second barrier layer.

3. The method for forming a semiconductor device according to claim 2, wherein, The forming the first isolation structure in the first groove and the second isolation structure in the second groove includes: Depositing isolation materials in the first groove and the second groove respectively to obtain the first isolation structure and the second isolation structure.

4. The method for forming a semiconductor device according to claim 1, wherein, The first barrier layer includes a first protrusion above the first isolation structure and a second protrusion above the second isolation structure, two ends of the first protrusion extending above the LDMOS region respectively, and two ends of the second protrusion extending above the CMOS region respectively.

5. The method for forming a semiconductor device according to claim 1, wherein, The method for etching the first barrier layer and a part of the first isolation layer further includes: Forming a mask layer on the surface of the first barrier layer, the mask layer exposing a part of the first barrier layer above the first corner; Etching the first barrier layer and the first isolation layer using the mask layer as a mask.

6. The method for forming a semiconductor device according to claim 1, wherein, Etching the exposed LDMOS region includes: Etching the exposed first isolation structure using DHF acid.

7. The method for forming a semiconductor device according to claim 6, wherein, The DHF acid is also used to etch the second corner into a rounded corner when etching the first isolation structure.

8. The method for forming a semiconductor device according to claim 2, wherein, The first isolation layer includes an oxide layer; The materials of the first barrier layer and the second barrier layer are the same.

9. The method for forming a semiconductor device according to claim 1, wherein, After the first corner is rounded, the forming method further includes: Removing the first barrier layer.

10. The method for forming a semiconductor device according to claim 1, wherein, The first corner includes two corners of the first isolation structure adjacent to the LDMOS region respectively.

11. A semiconductor device, characterized in that, Formed by the method for forming a semiconductor device according to any one of claims 1 to 10, the semiconductor device includes: A substrate, the substrate includes an LDMOS region and a CMOS region, the LDMOS region includes a first isolation structure, the CMOS region includes a second isolation structure, and the second isolation structure is higher than the CMOS region; A first isolation layer located on the surface of the substrate, the first isolation layer is lower than the second isolation structure, the first isolation structure includes a rounded corner, and the rounded corner extends to the first isolation layer towards the LDMOS region.

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