Semiconductor structure and method for forming the same, and stacked structure

Abstract

The present invention relates to a semiconductor structure and a method for forming the same. The semiconductor structure comprises: a substrate and a dielectric layer, wherein the substrate has a front side and a back side arranged opposite to each other, and the dielectric layer is formed on the front side; a connecting hole, which penetrates the substrate and extends to the dielectric layer; an insulating layer, which is located on the inner wall surface of the connecting hole; and a connecting structure, which comprises a first barrier layer, a second barrier layer and a conductive structure, wherein the first barrier layer is located on the surface of the insulating layer, and the second barrier layer is located between the first barrier layer and the conductive structure, and has an air gap between the first barrier layer and the second barrier layer. The present application can effectively prevent the barrier layer from breaking.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a semiconductor structure and a method for forming the same, and a stacking structure. Background Art

[0002] TSV technology used in three-dimensional packaging can effectively shorten the length of interconnect lines, reduce signal transmission delay and loss, and is one of the effective ways to achieve high-performance and high-reliability semiconductor devices.

[0003] The TSV structure usually includes a conductive structure of a metal material (such as copper). After the conductive structure is formed, it needs to be annealed to improve the dimensional uniformity of the conductive structure, thereby reducing the resistivity and improving the resistance to electromigration. However, annealing will cause the metal particles in the conductive structure to expand and generate thermal stress, which may cause interface cracks. In order to inhibit the expansion of metal particles, a barrier layer is usually provided outside the conductive structure.

[0004] However, in the actual process, the barrier layer often breaks due to the expansion of metal particles, thus causing defects in the semiconductor structure. Summary of the invention

[0005] Based on this, it is necessary to provide a semiconductor structure and a formation method and a stacking structure that can effectively prevent the barrier layer from breaking.

[0006] A semiconductor structure comprising:

[0007] The substrate comprises a substrate and a dielectric layer, wherein the substrate has a front side and a back side which are arranged opposite to each other, and the dielectric layer is formed on the front side;

[0008] A communication hole, penetrating the substrate and extending to the dielectric layer;

[0009] An insulating layer, located on the inner wall surface of the communicating hole;

[0010] The connecting structure comprises a first barrier layer, a second barrier layer and a conductive structure, wherein the first barrier layer is located on the surface of the insulating layer, and the second barrier layer is located between the first barrier layer and the conductive structure and has an air gap between the first barrier layer and the second barrier layer.

[0011] In one embodiment, the air gap penetrates the interface between the substrate and the dielectric layer.

[0012] In one of the embodiments, a width of a portion of the air gap opposite to the dielectric layer is smaller than a width of a portion of the air gap opposite to the substrate.

[0013] In one embodiment, the connecting structure further includes an isolation layer, wherein the isolation layer is located between the first barrier layer and the second barrier layer, and the first barrier layer, the isolation layer, the second barrier layer and the conductive structure together form the air gap, and the conductive structure closes the air gap.

[0014] In one embodiment, the connecting structure further includes an isolation layer, and the isolation layer is located between the first barrier layer and the second barrier layer. The first barrier layer, the isolation layer and the second barrier layer are jointly arranged to form the air gap.

[0015] In one embodiment, the second barrier layer includes a first sublayer and a second sublayer connected to each other, the air gap is located between the first barrier layer and the first sublayer, and the second sublayer closes the air gap.

[0016] In one embodiment, the conductive structure includes a first conductive layer and a second conductive layer, the first conductive layer is connected to the first sublayer, the first sublayer is located between the first conductive layer and the first blocking layer, the second conductive layer is connected to the second sublayer, and the second sublayer is located between the second conductive layer and the first blocking layer.

[0017] In one embodiment, the second conductive layer fills up the connecting hole and is separated from the first conductive layer by the second sub-layer.

[0018] In one embodiment, the second conductive layer fills up the connecting hole and is connected to the first conductive layer.

[0019] In one embodiment, the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

[0020] A method for forming a semiconductor structure, comprising:

[0021] Providing a substrate, the substrate comprising a substrate and a dielectric layer, the substrate having a front side and a back side arranged opposite to each other, the dielectric layer being formed on the front side;

[0022] forming a connecting hole in the substrate, wherein the connecting hole penetrates the substrate and extends to the dielectric layer;

[0023] forming an insulating layer on the inner wall surface of the communicating hole;

[0024] A connecting structure is formed on the surface of the insulating layer, and the connecting structure includes a first blocking layer, a second blocking layer and a conductive structure. The first blocking layer is located on the surface of the insulating layer, and the second blocking layer is located between the first blocking layer and the conductive structure and has an air gap between the first blocking layer and the second blocking layer.

[0025] In one embodiment, forming the connecting hole in the substrate includes:

[0026] The base is etched from the back side of the substrate to form a communication hole.

[0027] In one embodiment, the air gap penetrates the interface between the substrate and the dielectric layer.

[0028] In one of the embodiments, a width of a portion of the air gap opposite to the dielectric layer is smaller than a width of a portion of the air gap opposite to the substrate.

[0029] In one embodiment, the interconnection structure further includes an isolation layer, and forming the interconnection structure on the surface of the insulation layer includes:

[0030] forming a first barrier layer on the surface of the insulating layer;

[0031] forming a primary isolation layer on the surface of the first barrier layer, wherein the primary isolation layer includes a sidewall portion;

[0032] forming a primary barrier layer on the surface of the primary isolation layer;

[0033] forming a primary conductive layer on the surface of the primary barrier layer;

[0034] removing part of the primary conductive layer and part of the primary barrier layer to expose part of the sidewall portion, the remaining primary conductive layer constituting the first conductive layer, and the remaining primary barrier layer constituting the second barrier layer;

[0035] Removing part of the side wall portion, the remaining primary isolation layer constitutes an isolation layer, and the distance between the isolation layer and the opening of the communicating hole is greater than the distance between the second barrier layer and the opening of the communicating hole;

[0036] forming a second conductive layer on the surface of the first barrier layer, the surface of the second barrier layer, and the surface of the first conductive layer, wherein the second conductive layer and the first conductive layer constitute the conductive structure;

[0037] The first blocking layer, the isolation layer, the second blocking layer and the second conductive layer are jointly arranged to form the air gap, and the second conductive layer closes the air gap.

[0038] In one embodiment, the interconnection structure further includes an isolation layer, and forming the interconnection structure on the surface of the insulation layer includes:

[0039] forming a first barrier layer on the surface of the insulating layer;

[0040] forming a primary isolation layer on the surface of the first barrier layer, wherein the primary isolation layer includes a sidewall portion;

[0041] forming a primary barrier layer on the surface of the primary isolation layer;

[0042] forming a primary conductive layer on the surface of the primary barrier layer;

[0043] removing part of the primary conductive layer and part of the primary barrier layer to expose part of the sidewall portion, the remaining primary conductive layer constituting a first conductive layer, and the remaining primary barrier layer constituting a first sublayer;

[0044] Removing part of the side wall portion, the remaining primary isolation layer constitutes an isolation layer, and the distance between the isolation layer and the opening of the communicating hole is greater than the distance between the primary barrier layer and the opening of the communicating hole;

[0045] forming a second base layer on the surface of the first barrier layer, the surface of the first sub-layer and the surface of the first conductive layer, wherein the second sub-layer and the first sub-layer are used to form the second barrier layer;

[0046] forming a second conductive layer, wherein the second conductive layer and the first conductive layer constitute the conductive structure;

[0047] The first barrier layer, the isolation layer, the first sublayer and the second sublayer are jointly arranged to form the air gap, the air gap is located between the first barrier layer and the first sublayer, and the second sublayer closes the air gap.

[0048] In one embodiment, the forming the second conductive layer includes:

[0049] The second conductive layer is formed on the surface of the second sub-layer, and the second sub-layer and the first sub-layer constitute the second barrier layer.

[0050] In one embodiment, forming the second conductive layer comprises:

[0051] removing at least a portion of the second base layer on the surface of the first conductive layer, and the remaining second base layer constitutes a second sub-layer;

[0052] A second conductive layer is formed on the remaining surface of the second sub-layer and the exposed surface of the first conductive layer, wherein the first sub-layer and the second sub-layer constitute the second barrier layer:

[0053] In one embodiment, the second base layer serves as a second sub-layer, and the thickness of the second sub-layer is greater than the thickness of the first sub-layer.

[0054] The semiconductor structure and the method for forming the same are provided with two barrier layers (a first barrier layer and a second barrier layer) between the insulating layer and the conductive structure, thereby effectively increasing the strength of the barrier layers and preventing them from breaking during annealing of the conductive structure.

[0055] At the same time, an air gap is formed between the second barrier layer connected to the conductive structure and the first barrier layer. Therefore, even if the second barrier layer on one side of the air gap is cracked due to the expansion of the conductive structure, the air gap can effectively prevent the crack from continuing to extend, thereby effectively protecting the first barrier layer on the other side of the air gap from breaking.

[0056] Therefore, the present application can effectively prevent the barrier layer from breaking, thereby effectively suppressing the grain size of the conductive structure, thereby reducing the surface roughness of the conductive structure after annealing, and further reducing the generation of interface stress. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0058] Figure 1 is a flow chart of a method for forming a semiconductor structure provided in one embodiment;

[0059] Figure 2 A flowchart of a method for forming a semiconductor structure provided in another embodiment;

[0060] Figure 3 is a flow chart of a method for forming a semiconductor structure provided in yet another embodiment;

[0061] Figure 4-Figure 16 It is a structural schematic diagram of the semiconductor structure during its formation process;

[0062] Figure 17-Figure 19 Schematic diagrams of semiconductor structures in different embodiments. DETAILED DESCRIPTION

[0063] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0064] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0065] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0066] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0067] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0068] Embodiments of the invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention, and variations from the illustrated shapes as a result, for example, of manufacturing techniques and / or tolerances are to be expected. Thus, embodiments of the invention should not be limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing techniques.

[0069] In one embodiment, see Figure 1 , providing a method for forming a semiconductor structure, comprising:

[0070] Step S100, providing a substrate 100, the substrate 100 includes a substrate 110 and a dielectric layer 120, the substrate 110 has a front side 110a and a back side 110b opposite to each other, and the dielectric layer 120 is formed on the front side 110a, see Figure 4 ;

[0071] Step S200, forming a connecting hole 100a in the substrate 100, the connecting hole 100a penetrates the substrate 110 and extends to the dielectric layer 120, see Figure 5 ;

[0072] Step S300, forming an insulating layer 200 on the inner wall surface of the connecting hole 100a, see Figure 6 ;

[0073] Step S400, forming a connecting structure 300 on the surface of the insulating layer 200, the connecting structure 300 includes a first barrier layer 310, a second barrier layer 320 and a conductive structure 330, the first barrier layer 310 is located on the surface of the insulating layer 200, the second barrier layer 320 is located between the first barrier layer 310 and the conductive structure 330, and there is an air gap between the first barrier layer 310, see Figure 17-Figure 19 .

[0074] In step S100, the substrate 110 may include but is not limited to a silicon substrate. A shallow trench isolation structure 400 may be formed on the side of the substrate 110 close to the dielectric layer 120. The shallow trench isolation structure 400 isolates the substrate 110 into multiple active regions. The active regions are used to form various semiconductor devices.

[0075] The dielectric layer 120 may include but is not limited to an oxide dielectric layer (such as silicon dioxide, etc.) The dielectric layer 120 may have an interconnection via structure and a metal layer electrically connected to the active region, thereby leading out the signal of the semiconductor device or providing an external signal to the semiconductor device.

[0076] In step S200, the connecting holes 100a are used to form the connecting structures 300. When multiple chips formed by semiconductor structures are stacked, the corresponding connecting holes 100a of each chip are aligned, so that the connecting structures 300 in each connecting hole 100a are electrically connected, thereby realizing interconnection between each chip.

[0077] In step S300, the insulating layer 200 is located between the connecting structure 300 and the inner wall of the connecting hole 100a, thereby achieving electrical isolation between the connecting structure 300 and the substrate 110. The insulating layer 200 may be made of silicon dioxide, etc. The insulating layer 200 may be the same as or different from the dielectric layer 120.

[0078] When the material of the insulating layer 200 can be silicon dioxide, specifically, a silicon dioxide film layer can be deposited on the inner wall of the connecting hole 100a by a chemical vapor deposition (CVD) method based on silane (SiH4) or tetraethyl orthosilicate (TEOS) as the insulating layer 200. The thickness of the silicon dioxide film layer can be 0.2 μm-2 μm.

[0079] In step S400 , the first barrier layer 310 , the second barrier layer 320 , and the conductive structure 330 of the connection structure 300 are all structures capable of conductive connection.

[0080] The first barrier layer 310 may be made of tantalum (Ta) or tantalum nitride (TaN), etc., and may have a thickness of 0.05 μm-0.1 μm, which can effectively reduce the thermal expansion coefficient of the conductive structure 330 when the conductive structure 330 undergoes thermal expansion.

[0081] The second barrier layer 320 may be made of tantalum (Ta) or tantalum nitride (TaN), etc., and may have a thickness of 0.05 μm-0.1 μm. It may also effectively reduce the thermal expansion coefficient of the conductive structure 330 when the conductive structure 330 undergoes thermal expansion.

[0082] It is understood that the materials and / or thicknesses of the first barrier layer 310 and the second barrier layer 320 may be the same or different. Furthermore, the materials and / or thicknesses of different sections of the first barrier layer 310 and / or the second barrier layer 320 may be the same or different, and the present application has no limitation thereto.

[0083] The material of the conductive structure 330 may be a metal material with good conductive properties (such as metal copper (Cu)).

[0084] In this embodiment, two barrier layers (a first barrier layer 310 and a second barrier layer 320 ) are disposed between the insulating layer 200 and the conductive structure 330 , thereby effectively increasing the strength of the barrier layers and preventing them from being broken during annealing of the conductive structure 330 .

[0085] At the same time, an air gap 100b is formed between the second barrier layer 320 connected to the conductive structure 330 and the first barrier layer 310. Therefore, even if the second barrier layer 320 on one side of the air gap 100b is cracked due to the expansion of the conductive structure 330, the air gap 100b can effectively prevent the crack from continuing to extend, thereby effectively protecting the first barrier layer 310 on the other side of the air gap 100b from breaking.

[0086] Therefore, the present application can effectively prevent the barrier layer from breaking, thereby effectively suppressing the grain size of the conductive structure 330, thereby reducing the surface roughness of the conductive structure after annealing, and further reducing the generation of interface stress.

[0087] Furthermore, since air has poor thermal conductivity, the present application can also effectively prevent the heat generated by the conductive structure from diffusing to the surrounding substrate 110 and / or dielectric layer 120 .

[0088] In one embodiment, see Figure 5 , step S200 includes: etching the base 100 from the back side 110 b of the substrate 110 to form a connecting hole 100 a.

[0089] As an example, the substrate 110 and the dielectric layer 120 may be etched in sequence from the back side 110b of the substrate 110 by dry etching to form the connecting hole 100a. The depth of the connecting hole 100 may be 20 μm-150 μm, and the depth of the connecting hole 100 extending into the dielectric layer 120 may be 0.5 μm-1 μm. The diameter of the connecting hole 100 may be 3 μm-50 μm. The aspect ratio (i.e., the ratio of depth to diameter) of the connecting hole 100 may be 0.4-50.

[0090] Since the back side 110b of the substrate 110 is far away from the semiconductor devices formed in the active area and the circuit structures connecting the semiconductor devices, this embodiment can effectively prevent the semiconductor devices formed in the active area and the related circuit structures from being damaged when forming the connecting hole 100a.

[0091] In one embodiment, see Fig.17 or Fig.18 or Fig.19 The air gap 100 b formed in step S400 penetrates the interface between the substrate 110 and the dielectric layer 120 .

[0092] Semiconductor devices are densely distributed around the interface between the substrate 110 and the dielectric layer 120 , and the semiconductor device structure usually penetrates both sides of the interface between the substrate 110 and the dielectric layer 120 .

[0093] In this embodiment, the air gap 100b penetrates the interface between the substrate 110 and the dielectric layer 120, thereby effectively preventing the cracks of the barrier layer from extending to the substrate 110 and / or the dielectric layer 120 near the interface. Therefore, this embodiment can also effectively protect the semiconductor devices around the air gap 100b.

[0094] In one embodiment, the width of a portion of the air gap 100 b opposite to the dielectric layer 120 is smaller than the width of a portion of the air gap 100 b opposite to the substrate 110 .

[0095] The dielectric layer 120 is a film layer formed on the substrate 110, and its thickness is much smaller than that of the substrate 110. Therefore, in this embodiment, the width of the portion of the air gap 100b opposite to the dielectric layer 120 is smaller, thereby effectively preventing the air gap 100b from causing the dielectric layer 120 to be unstable.

[0096] Furthermore, when the device is working, the dielectric layer 120 generates a large amount of heat. At this time, the width of the air gap 100b opposite to the substrate 110 is large, which will cause the heat to flow to the position with a large gap, thereby being more conducive to heat dissipation and preventing the impact on surrounding devices.

[0097] In one embodiment, the communication structure 300 further includes an isolation layer 340. Figure 2 , step S400 includes:

[0098] Step S411, forming a first barrier layer 310 on the surface of the insulating layer 200, see Figure 7 ;

[0099] Step S412, forming a primary isolation layer 341 on the surface of the first barrier layer 310, the primary isolation layer including a sidewall portion 3411, see Figure 8 ;

[0100] Step S413, forming a primary barrier layer 3211 on the surface of the primary isolation layer 341, see Fig. 9 ;

[0101] Step S414, forming a primary conductive layer 3311 on the surface of the primary barrier layer 3211, see Fig.10 ;

[0102] Step S415, removing part of the primary conductive layer 3311 and part of the primary barrier layer 3211 to expose part of the sidewall portion 3411, the remaining primary conductive layer 3311 constitutes the first conductive layer 331, and the remaining primary barrier layer 3211 constitutes the second barrier layer 320, see Fig.11 ;

[0103] Step S416, removing part of the side wall portion 3411, the remaining primary isolation layer 341 forms an isolation layer 340, and the distance H1 between the isolation layer 340 and the opening of the connecting hole 100a is greater than the distance H2 between the second barrier layer 320 and the opening of the connecting hole 100a, see Fig.12 ;

[0104] Step S417, forming a second conductive layer 332 on the surface of the first barrier layer 310, the surface of the second barrier layer 320 and the surface of the first conductive layer 331, the second conductive layer 332 and the first conductive layer 331 constitute a conductive structure 330, see Fig.13 ;

[0105] The first barrier layer 310 , the isolation layer 340 , the second barrier layer 320 and the second conductive layer 332 of the conductive structure 330 are jointly arranged to form an air gap 100 b , and the second conductive layer 332 of the conductive structure 330 closes the air gap 100 b .

[0106] In step S411, the first barrier layer 310 may be formed by a physical vapor deposition (PVD) method. The material of the primary barrier layer 2111 may be tantalum (Ta) and tantalum nitride (TaN), and the thickness thereof may be 0.05 μm-0.1 μm.

[0107] In step S412, the material of the primary isolation layer 341 may be an insulating material, thereby facilitating the formation of the air gap 100b. Of course, the material of the primary isolation layer 341 may also be a conductive material, etc., and the present application has no limitation on this.

[0108] As an example, the material of the primary isolation layer 341 is silicon dioxide. Specifically, a 0.2 μm-2 μm thick silicon dioxide film layer can be deposited on the inner wall of the communication hole 100 a by a chemical vapor deposition (CVD) method based on silane (SiH4) or tetraethyl orthosilicate (TEOS) as the primary isolation layer 341 .

[0109] In step S413, similar to the first barrier layer 310, the primary barrier layer 3211 can also be formed by physical vapor deposition (PVD) method. The primary barrier layer 3211 can be made of tantalum (Ta) and tantalum nitride (TaN), and its thickness can be 0.05 μm-0.1 μm.

[0110] In step S414, the material of the primary conductive layer 3311 may be metal copper (Cu) or the like. Specifically, a copper seed layer may be formed on the surface of the primary barrier layer 2111 by a PVD method. Then, copper is electroplated on the surface of the copper seed layer by electroplating growth, and the copper seed layer and the electroplated copper together constitute the primary conductive layer 3311.

[0111] More specifically, since the subsequent step S415 will further remove part of the primary conductive layer 3311 to form the air gap 100b, the primary conductive layer 3311 grown on the surface of the primary barrier layer 2111 may not fill the connecting hole 100a. As an example, the filling thickness of the central portion of the primary conductive layer 3311 may be 20%-70% of the depth of the connecting hole 100a.

[0112] In step S415, part of the primary barrier layer 3211 and part of the primary conductive layer 3311 covering the side wall portion 3411 can be removed by a mixed acid solution, thereby partially exposing the side wall portion 3411 of the primary isolation layer 341, and forming the second barrier layer 320 and the first conductive layer 331 at the same time.

[0113] After the sidewall portion 3411 of the primary isolation layer 341 is partially exposed, step S416 is performed, so that the isolation layer 340 having a surface lower than the surface of the second barrier layer 320 can be formed more easily, thereby making it easier to realize the air gap 100b.

[0114] In step S416 , the sidewall portion 3411 of the primary isolation layer 341 (eg, silicon dioxide film layer) in the communication hole 100 a may be etched by hydrofluoric acid or dry etching to form an isolation layer 340 .

[0115] Specifically, after removing part of the primary isolation layer 341, the distance H1 between the surface of the isolation layer 340 formed by the remaining primary isolation layer 341 and the opening of the connecting hole 100a is greater than the distance H2 between the surface of the second barrier layer 320 and the opening of the connecting hole 100a. Fig.12 In the middle direction, after a portion of the primary isolation layer 341 is removed, the surface of the isolation layer 340 formed by the remaining primary isolation layer 341 is lower than the surface of the second barrier layer 320 .

[0116] In step S417 , specifically, the material of the second conductive layer 332 may be the same as that of the first conductive layer 331 , or may be different, and the present application has no limitation on this.

[0117] As an example, when the material of the second conductive layer 332 and the material of the first conductive layer 331 are both copper, the formation process thereof can be similar to the formation process of the first conductive layer 331. A copper seed layer can be formed first, and then copper is electroplated on the copper seed layer, and further processed to form the second conductive layer 332.

[0118] Specifically, the air gap 100 b may be closed by the copper seed layer of the second conductive layer 332 .

[0119] In this embodiment, by forming the primary isolation layer 341 and then partially removing the sidewall portion 3411 thereof, an air gap can be conveniently and effectively formed between the barrier layers on both sides (the first barrier layer 310 and the second barrier layer 320 ).

[0120] Furthermore, in this embodiment, the first conductive layer 331 and the second conductive layer 332 of the conductive structure 330 are formed in two sections, so that the second barrier layer 320 can be easily formed while the first conductive layer 331 is formed, thereby facilitating the formation of the air gap 100b. Furthermore, when the first conductive layer 331 and the second conductive layer 332 of the conductive structure 330 are formed in two sections, the height of the formed air gap 100b can be conveniently adjusted by controlling the etching height of the primary conductive layer 3311 and the primary barrier layer 3211 during the formation of the first conductive layer 331.

[0121] Of course, the formation method of the conductive structure 330 is not limited thereto. In other embodiments, the conductive structure 330 can also be formed at one time, so that the first barrier layer 310, the isolation layer 340, the second barrier layer 320 and the conductive structure 330 are together formed to form the air gap 100b, and the conductive structure 330 closes the air gap 100b.

[0122] In one embodiment, the communication structure 300 further includes an isolation layer 340. Figure 3 , step S400 includes:

[0123] Step S421, forming a first barrier layer 310 on the surface of the insulating layer 200, see Figure 7 ;

[0124] Step S422, forming a primary isolation layer 341 on the surface of the first barrier layer 310, the primary isolation layer including a sidewall portion 3411, see Figure 8 ;

[0125] Step S423, forming a primary barrier layer 3211 on the surface of the primary isolation layer 341, see Fig. 9 ;

[0126] Step S424, forming a primary conductive layer 3311 on the surface of the primary barrier layer 3211, see Fig.10 ;

[0127] Step S425, removing part of the primary conductive layer 3311 and part of the primary barrier layer 3211 to expose part of the sidewall portion 3411, the remaining primary conductive layer 3311 constitutes the first conductive layer 331, and the remaining primary barrier layer 3211 constitutes the first sub-layer 321, see Fig.14 ;

[0128] Step S426, removing part of the side wall portion 3411, the remaining primary isolation layer 341 forms an isolation layer 340, and the distance H1 between the isolation layer 340 and the opening of the connecting hole 100a is greater than the distance H2 between the second barrier layer 320 and the opening of the connecting hole 100a, see Fig.15 ;

[0129] Step S427, forming a second base layer 3221 on the surface of the first barrier layer 310, the surface of the first sub-layer 321 and the surface of the first conductive layer 331, see Fig.16 ;

[0130] Step S428, forming a second conductive layer 332, the second conductive layer 332 and the first conductive layer 331 constitute a conductive structure 330, see Fig.17 or Fig.18 or Fig.19 .

[0131] The process from step 421 to step S426 may be similar to step 411 to step S416 in the above embodiment.

[0132] The difference is that after removing part of the primary conductive layer 3311 and part of the primary barrier layer 3211 in step S425, the remaining primary barrier layer 3211 constitutes the first sublayer 321 of the second barrier layer 320, see Fig.14 The first conductive layer 331 is connected to the first sub-layer 321 , and the first sub-layer 321 is located between the first conductive layer 331 and the first barrier layer 321 .

[0133] In step S427 , the material of the second base layer 3221 may be the same as that of the first sub-layer 321 , or they may be different.

[0134] Meanwhile, the material of the first sub-layer 321 may be the same as the material of the first barrier layer 310 , or they may be different.

[0135] In step S428, the material of the second conductive layer 332 may be the same as or different from the material of the first conductive layer 331. As an example, when the material of the second conductive layer 332 and the material of the first conductive layer 331 are both copper, the formation process may be similar to the formation process of the first conductive layer 331, and a copper seed layer may be formed first, and then copper is electroplated on the copper seed layer, and further processed to form the second conductive layer 332.

[0136] In one embodiment, see Fig.17 , the second base layer 3221 serves as the second sublayer 322.

[0137] Step S428 includes: forming a second conductive layer 332 on the surface of the second sub-layer 322 .

[0138] Therefore, in this embodiment, the second sub-layer 322 and the first sub-layer 321 constitute the second barrier layer 320, see Fig.17 .

[0139] At this time, the second conductive layer 332 fills up the via hole 100 a , and the second conductive layer 332 is connected to the second sub-layer 322 , and is separated from the first conductive layer 331 by the second sub-layer 322 .

[0140] That is, the second sublayer 322 is provided between the second conductive layer 332 and the first conductive layer 331. Therefore, the second sublayer 322 can effectively prevent the second conductive layer 332 and the first conductive layer 331 formed in two stages from being inconsistent in grain size and the like, and from being affected by thermal stress and causing cracks at the interface during the subsequent annealing process.

[0141] In another embodiment, step S428 includes:

[0142] Step S4281, removing at least a portion of the second base layer 3221 on the surface of the first conductive layer 331, and the remaining second base layer 3221 constitutes the second sub-layer 322;

[0143] Step S4282, forming a second conductive layer 332 on the surface of the second sub-layer 322 and the exposed surface of the first conductive layer 331, the first sub-layer 321 and the second sub-layer 322 constitute a second barrier layer 320, see Fig.18 or Fig.19 .

[0144] In step S4281 , the second base layer 3221 covering the surface of the first conductive layer 331 may be completely removed, or the second base layer 3221 covering the surface of the first conductive layer 521 may be partially removed.

[0145] In step S4282 , the second conductive layer 332 fills the connecting hole and connects the second sub-layer 322 and the first conductive layer 331 .

[0146] In this embodiment, the second conductive layer 332 is in contact with and connected to the first conductive layer 331 , thereby reducing the contact resistance between the second conductive layer 332 and the first conductive layer.

[0147] See also Fig.19 When the second base layer 3221 covering the surface of the first conductive layer 331 is partially removed, the contact resistance can be reduced and the thermal stress between the second conductive layer 332 and the first conductive layer 331 formed in two sections can be prevented.

[0148] At the same time, if the central portion of the second base layer 3221 covering the surface of the first conductive layer 521 is removed and the edge portion is retained, the retained edge portion can also help prevent the connection between the second sub-layer 322 and the first sub-layer from affecting the thermal expansion of the internal conductive structure 330 (including the first conductive layer 331 and the second conductive layer 332) due to poor contact.

[0149] In the above embodiment, the second barrier layer 320 and the conductive structure 330 are formed in two sections, thereby facilitating the formation of the air gap 100b. The first barrier layer 310, the isolation layer 340 and the second barrier layer 320 are jointly formed to form the air gap 100b, and the conductive structure 330 closes the air gap 100b.

[0150] Of course, in other embodiments, the first barrier layer 310 , the isolation layer 340 and the second barrier layer 320 are jointly formed to enclose the air gap 100 b , and when the conductive structure 330 encloses the air gap 100 b , the forms of the conductive structure 330 and the second barrier layer 320 may also be different.

[0151] As an example, the conductive structure 330 may be formed at one time, and the second barrier layer 320 may also be formed at one time.

[0152] Alternatively, when the first sublayer 321 and the second sublayer 322 of the second barrier layer 320 are formed in two sections, the conductive structure 330 can also be formed at one time, and the present application has no limitation thereto.

[0153] In one embodiment, the thickness of the second sub-layer 322 is greater than the thickness of the first sub-layer 321, see Fig.17 or Fig.18 or Fig.19 .

[0154] At this time, the second sub-layer 322 can be effectively prevented from having a poor contact with the first sub-layer 321 and thus affecting the thermal expansion of the internal conductive layer structure (including the first conductive layer 331 and the second conductive layer 332 ).

[0155] It should be understood that although Figures 1 to 3 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figures 1 to 3At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0156] In one embodiment, a semiconductor structure is also provided. Figures 17 to 19 , including a substrate 100 , a connecting hole 100 a , an insulating layer 200 and a connecting structure 300 .

[0157] The substrate 100 includes a substrate 110 and a dielectric layer 120. The substrate 110 has a front side 110a and a back side 110b that are oppositely disposed. The dielectric layer 120 is formed on the front side 110a. The connecting hole 100a passes through the substrate 110 and extends to the dielectric layer 120. The insulating layer 200 is located on the inner wall surface of the connecting hole 100a. The connecting structure 300 includes a first barrier layer 310, a second barrier layer 320 and a conductive structure 330. The first barrier layer 310 is located on the surface of the insulating layer 200, and the second barrier layer 320 is located between the first barrier layer 310 and the conductive structure 330, and has an air gap 100b between the first barrier layer 310 and the second barrier layer 320.

[0158] In one embodiment, the air gap 100 a penetrates the interface between the substrate 110 and the dielectric layer 120 .

[0159] In one embodiment, the width of a portion of the air gap 100 b opposite to the dielectric layer 120 is smaller than the width of a portion of the air gap 100 b opposite to the substrate 110 .

[0160] In one embodiment, the connecting structure 300 further includes an isolation layer 340. The isolation layer 340 is located between the first barrier layer 310 and the second barrier layer 320. The first barrier layer 310, the isolation layer 340, the second barrier layer 320 and the conductive structure 330 together form an air gap 100b, and the conductive structure 330 closes the air gap.

[0161] Further, in this embodiment, the conductive structure 330 may include a first conductive layer 331 and a second conductive layer 332 connected to each other. The first conductive layer 331 and the second conductive layer 332 are formed in two processes. The first conductive layer 331 is connected to the second barrier layer 320. The second barrier layer 320 is located between the first conductive layer 331 and the first barrier layer 310. The second conductive layer 332 is connected to the first barrier layer 310, the second barrier layer 320 and the first conductive layer 331.

[0162] At this time, the first barrier layer 310 , the isolation layer 340 , the second barrier layer 320 and the second conductive layer 332 are jointly arranged to form an air gap 100 b , and the second conductive layer 332 closes the air gap.

[0163] Of course, the conductive structure 330 may also be formed in one process, and the present application has no limitation on this.

[0164] In one embodiment, the communication structure 300 further includes an isolation layer 340. The isolation layer 340 is located between the first barrier layer 310 and the second barrier layer 320. The first barrier layer 310, the isolation layer 340 and the second barrier layer 320 are jointly arranged to form an air gap 100b.

[0165] In one embodiment, the second barrier layer 320 includes a first sublayer 321 and a second sublayer 322 connected to each other. The air gap 100b is located between the first barrier layer 310 and the first sublayer 321, and the second sublayer 322 closes the air gap.

[0166] In one embodiment, the conductive structure 330 includes a first conductive layer 331 and a second conductive layer 332. The first conductive layer 331 is connected to the first sublayer 321. The first sublayer 321 is located between the first conductive layer 331 and the first barrier layer 310. The second conductive layer 332 is connected to the second sublayer 332. The second sublayer 332 is located between the second conductive layer 332 and the first barrier layer 310.

[0167] In one embodiment, the second sub-layer 322 is formed on the surface of the first barrier layer 310 , the surface of the first sub-layer 321 , and the surface of the first conductive layer 331 .

[0168] In one embodiment, the thickness of the second sub-layer 322 is greater than the thickness of the first sub-layer 321 .

[0169] In one embodiment, see Fig.17 The second conductive layer 332 fills up the connecting hole 100 a and is separated from the first conductive layer 331 by the second sub-layer 322 .

[0170] In one embodiment, the second conductive layer 332 fills the connecting hole 100a and connects to the first conductive layer 331. Fig.18 or Fig.19 .

[0171] At this time, part of the second sublayer 322 may be provided between the first conductive layer 331 and the second conductive layer 332. For example, the edge of the second conductive layer 332 may also include the second sublayer 322 between the first conductive layers 331, see Fig.19 .

[0172] For the specific limitations and technical effects of the semiconductor structure, please refer to the limitations on the method for forming the semiconductor structure in the above text, which will not be repeated here.

[0173] Of course, it is understandable that the semiconductor structure of the present application is not limited to being formed by the semiconductor structure forming method in the above embodiment.

[0174] In one embodiment, a stacked structure is further provided, wherein the stacked structure is formed based on any one of the above semiconductor structures.

[0175] Specifically, when forming a stacked structure, the above-mentioned semiconductor structure needs to undergo processing techniques such as etching or planarization to expose the conductive structure 330 in the dielectric layer 120 (not shown), so that when it is stacked with an adjacent semiconductor structure, the conductive structure 330 in the connecting hole 100a can be conductively connected to perform signal transmission.

[0176] In the description of this specification, the description with reference to the terms "one embodiment", "ideal embodiment", etc. means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0177] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0178] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: include: The substrate comprises a substrate and a dielectric layer, wherein the substrate has a front side and a back side which are arranged opposite to each other, and the dielectric layer is formed on the front side; A communication hole, penetrating the substrate and extending to the dielectric layer; An insulating layer, located on the inner wall surface of the communicating hole; A connecting structure, comprising a first barrier layer, a second barrier layer and a conductive structure, wherein the first barrier layer is located on the surface of the insulating layer, and the second barrier layer is located between the first barrier layer and the conductive structure, and has an air gap between the first barrier layer and the second barrier layer; The connecting structure further includes an isolation layer, and the isolation layer is located between the first barrier layer and the second barrier layer. The first barrier layer, the isolation layer, the second barrier layer and the conductive structure are jointly arranged to form the air gap.

2. The semiconductor structure according to claim 1, characterized in that: The air gap penetrates the interface between the substrate and the dielectric layer.

3. The semiconductor structure according to claim 2, characterized in that: A width of a portion of the air gap facing the dielectric layer is smaller than a width of a portion of the air gap facing the substrate.

4. The semiconductor structure according to claim 1, characterized in that: The conductive structure closes the air gap.

5. The semiconductor structure according to claim 1, characterized in that: The second barrier layer includes a first sublayer and a second sublayer connected to each other, the air gap is located between the first barrier layer and the first sublayer, and the second sublayer closes the air gap.

6. The semiconductor structure according to claim 5, characterized in that: The conductive structure includes a first conductive layer and a second conductive layer, the first conductive layer is connected to the first sublayer, the first sublayer is located between the first conductive layer and the first blocking layer, the second conductive layer is connected to the second sublayer, and the second sublayer is located between the second conductive layer and the first blocking layer.

7. The semiconductor structure according to claim 6, characterized in that: The second conductive layer fills up the communicating hole and is separated from the first conductive layer by the second sub-layer.

8. The semiconductor structure according to claim 6, characterized in that: The second conductive layer fills the via hole and is connected to the first conductive layer.

9. The semiconductor structure according to claim 7 or 8, characterized in that: The thickness of the second sub-layer is greater than the thickness of the first sub-layer.

10. A method for forming a semiconductor structure according to any one of claims 1 to 9, characterized in that: include: Providing a substrate, the substrate comprising a substrate and a dielectric layer, the substrate having a front side and a back side arranged opposite to each other, the dielectric layer being formed on the front side; forming a connecting hole in the substrate, wherein the connecting hole passes through the substrate and extends to the dielectric layer; forming an insulating layer on the inner wall surface of the communicating hole; A connecting structure is formed on the surface of the insulating layer, and the connecting structure includes a first blocking layer, a second blocking layer and a conductive structure. The first blocking layer is located on the surface of the insulating layer, and the second blocking layer is located between the first blocking layer and the conductive structure and has an air gap between the first blocking layer and the second blocking layer.

11. The method for forming a semiconductor structure according to claim 10, characterized in that: The forming of the connecting hole in the substrate comprises: The base is etched from the back side of the substrate to form a communication hole.

12. The method for forming a semiconductor structure according to claim 10, wherein: The air gap penetrates the interface between the substrate and the dielectric layer.

13. The method for forming a semiconductor structure according to claim 12, wherein: A width of a portion of the air gap facing the dielectric layer is smaller than a width of a portion of the air gap facing the substrate.

14. The method for forming a semiconductor structure according to claim 10, wherein: The forming of a connecting structure on the surface of the insulating layer comprises: forming a first barrier layer on the surface of the insulating layer; forming a primary isolation layer on the surface of the first barrier layer, wherein the primary isolation layer includes a sidewall portion; forming a primary barrier layer on the surface of the primary isolation layer; forming a primary conductive layer on the surface of the primary barrier layer; removing a portion of the primary conductive layer and a portion of the primary barrier layer to expose a portion of the sidewall portion, wherein the remaining primary conductive layer constitutes a first conductive layer, and the remaining primary barrier layer constitutes a second barrier layer; Removing part of the side wall portion, the remaining primary isolation layer constitutes an isolation layer, and the distance between the isolation layer and the opening of the communicating hole is greater than the distance between the second barrier layer and the opening of the communicating hole; forming a second conductive layer on the surface of the first barrier layer, the surface of the second barrier layer, and the surface of the first conductive layer, wherein the second conductive layer and the first conductive layer constitute the conductive structure; The first blocking layer, the isolation layer, the second blocking layer and the second conductive layer are jointly arranged to form the air gap, and the second conductive layer closes the air gap.

15. The method for forming a semiconductor structure according to claim 10, wherein: The forming of a connecting structure on the surface of the insulating layer comprises: forming a first barrier layer on the surface of the insulating layer; forming a primary isolation layer on the surface of the first barrier layer, wherein the primary isolation layer includes a sidewall portion; forming a primary barrier layer on the surface of the primary isolation layer; forming a primary conductive layer on the surface of the primary barrier layer; removing part of the primary conductive layer and part of the primary barrier layer to expose part of the sidewall portion, the remaining primary conductive layer constituting a first conductive layer, and the remaining primary barrier layer constituting a first sublayer; Removing part of the side wall portion, the remaining primary isolation layer constitutes an isolation layer, and the distance between the isolation layer and the opening of the communicating hole is greater than the distance between the primary barrier layer and the opening of the communicating hole; forming a second base layer on the surface of the first barrier layer, the surface of the first sub-layer and the surface of the first conductive layer; A second conductive layer is formed, wherein the second conductive layer and the first conductive layer constitute the conductive structure.

16. The method for forming a semiconductor structure according to claim 15, characterized in that: The second base layer is used as a second sub-layer, and the forming of the second conductive layer includes: The second conductive layer is formed on the surface of the second sub-layer, and the second sub-layer and the first sub-layer constitute the second barrier layer.

17. The method for forming a semiconductor structure according to claim 15, wherein: The forming of the second conductive layer comprises: removing at least a portion of the second base layer on the surface of the first conductive layer, and the remaining second base layer constitutes a second sub-layer; A second conductive layer is formed on the surface of the second sub-layer and the exposed surface of the first conductive layer. The first sub-layer and the second sub-layer constitute the second barrier layer.

18. The method for forming a semiconductor structure according to claim 16 or 17, characterized in that: The thickness of the second sub-layer is greater than the thickness of the first sub-layer.

19. A stacking structure, characterized in that: The semiconductor structure is formed by processing based on any one of claims 1 to 9.

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