A back-illuminated pixel anti-total dose reinforcement structure and preparation method

Abstract

The present invention discloses a back-illuminated pixel total dose reinforcement structure and preparation method, comprising a gate region of an NMOS1 transistor and a gate region of an NMOS2 transistor; the gate regions of the NMOS1 transistor and the NMOS2 transistor each form a ⌚-shaped structure, are symmetrically arranged, and have openings directed away from a shared active area. This structure addresses the problem of radiation resistance reinforcement within the constraints of a relatively small pixel-level circuit area. Designed for small-sized back-illuminated pixel circuit structures, it meets the radiation resistance requirements of ultra-large-scale back-illuminated image sensors for space applications.

Description

Technical Field

[0001] The present invention belongs to the technical field of image sensors, and in particular to a back-illuminated pixel anti-total dose reinforcement structure and a preparation method thereof. Background Art

[0002] Ultra-large-scale image sensors are widely used in fields such as Earth observation, deep space exploration, and space monitoring. Due to the large number of high-energy particles in outer space, a total dose effect of bird's beak edge leakage occurs. This total dose effect of bird's beak edge leakage increases the gate-induced drain-source current. Trapped charge in the lateral oxide isolation region (field oxide structure) increases the edge leakage current of the transistor and changes the junction breakdown voltage. As feature sizes scale down, and oxide thickness decreases below 10nm, most hole traps in the oxide are neutralized by tunneling from the gate and substrate, significantly reducing the trap density. Furthermore, when the oxide thickness decreases below approximately 12nm, the radiation-induced interface traps also decrease.

[0003] However, in advanced CMOS technology, the typical STI thickness is 300-450nm. Oxide trap charges, interface traps, and boundary traps (or switch-state charges) generated by total-dose radiation still induce significant leakage channels, making this region a key focus of radiation hardening. To address radiation-induced edge leakage at the junction of gate oxide and isolation oxide, specialized gate structures (such as H-type gates and ring gates) have traditionally been used to reduce or prevent this. Therefore, efforts to mitigate the increased leakage current caused by total-dose radiation effects primarily focus on reducing this edge leakage.

[0004] The H-gate structure utilizes the gate oxide's excellent radiation resistance and ease of reinforcement to prevent inversion of the silicon surface in the thin oxide region beneath the polysilicon gate, effectively cutting off the path between the parasitic channel at the edge of the field region and the source and drain regions. This structure can thus suppress parasitic leakage at the edge of the field region and improve the circuit's resistance to ionizing radiation. However, the presence of this stripe region also sacrifices chip area and impacts circuit performance. However, compared to ring gates and guard rings, the H-gate structure increases chip area and sacrifices less circuit performance.

[0005] Because the drain of the device is surrounded by the gate, avoiding the field region, the ring gate structure can completely eliminate parasitic leakage caused by radiation edge radiation in MOS devices. The subthreshold characteristics of the device are essentially unaffected, and its radiation resistance is determined solely by the gate oxide layer. Taking the NMOS ring gate transistor as an example, the layout structure eliminates the parasitic transistor at the edge of the original MOS device, eliminating the leakage path between the source and drain terminals within the MOS device. Furthermore, the addition of a P+ guard ring can absorb the electron leakage caused by inversion under the field oxide layer due to the total dose effect between different NMOS devices. The ring gate area is much larger than that of the H-type gate. Therefore, for pixel-level circuits with limited area, the H-type gate structure is often used for radiation hardening.

[0006] Under the condition of limited pixel size, ultra-large-scale back-illuminated image sensors can significantly improve resolution by using small pixel sizes. However, the pixel-level readout circuit area corresponding to the small pixel size is relatively small. The traditional H-type gate and ring gate radiation-resistant reinforcement structures will increase the circuit area and cannot meet the radiation-resistant reinforcement requirements of small pixel sizes. Summary of the Invention

[0007] To address the challenges of the prior art, the present invention provides a back-illuminated pixel total dose hardening structure and fabrication method, addressing the radiation hardening challenges within the constraints of a relatively small pixel-level circuit area. This design addresses the radiation hardening requirements of ultra-large-scale back-illuminated image sensors for space applications, specifically small-scale back-illuminated pixel circuit structures.

[0008] To achieve the above object, the present invention provides the following technical solutions:

[0009] A back-illuminated pixel total dose resistance reinforcement structure includes a gate region of an NMOS1 tube and a gate region of an NMOS2 tube;

[0010] The gate regions of the NMOS1 tube and the NMOS2 tube are in a ⊂-shaped structure, the gate regions of the NMOS1 tube and the NMOS2 tube are symmetrically arranged, and the opening directions of the gate regions of the NMOS1 tube and the NMOS2 tube are away from the common active area.

[0011] Preferably, the drain regions of NMOS1 and NMOS2 are arranged between the gate regions of NMOS1 and NMOS2, the source region of NMOS1 is arranged at the opening of the gate region of NMOS1, and the source region of NMOS2 is arranged at the opening of the gate region of NMOS1.

[0012] Preferably, the source regions of NMOS1 and NMOS2 are arranged between the gate regions of NMOS1 and NMOS2, the drain region of NMOS1 is arranged at the opening of the gate region of NMOS1, and the drain region of NMOS2 is arranged at the opening of the gate region of NMOS2.

[0013] Preferably, a P-type doping implantation region of the active region is provided outside the gate region of the NMOS1 tube and the gate region of the NMOS2 tube.

[0014] Preferably, the portions where the gate regions of the NMOS1 tube and the gate regions of the NMOS2 tube overlap with the active regions are thin oxide regions.

[0015] Preferably, the source region and the drain region of the NMOS1 transistor and the NMOS2 transistor are N-type doped implanted regions of the active region.

[0016] A method for preparing a back-illuminated pixel anti-total dose reinforcement structure includes the following steps:

[0017] forming an active area AA layer on a silicon wafer;

[0018] N+ type doping and P+ type doping are respectively injected into the active area AA layer, N+ is injected into the inner NMOS area to form the N type doping injection area of ​​the active area, and P+ is injected into the outer surrounding layer to form the P type doping injection area;

[0019] A Poly gate with a double semi-enclosed structure is formed on the upper N-type doped implanted region in the active area AA layer;

[0020] Forming a through hole CT between the active area AA layer and the metal in the source area and the drain area;

[0021] Metal is deposited in the source and drain regions to form a back-illuminated pixel anti-total dose reinforcement structure.

[0022] Compared with the prior art, the present invention has the following beneficial technical effects:

[0023] The present invention provides a back-illuminated pixel anti-total dose reinforcement structure, the layout area of ​​which is approximately half that of the traditional H-gate structure, effectively expanding the leakage channel distance between the source and the drain, and significantly reducing source-drain leakage. A P+ injection protection ring surrounding structure is adopted to further block the leakage channel. Thus, anti-radiation reinforcement is achieved under the conditions of small-sized pixels. The P+ double-half-surrounding gate anti-radiation reinforcement device of the present invention meets the anti-radiation reinforcement requirements of ultra-large-scale back-illuminated image sensors for small-sized pixels, and is conducive to improving the resolution and anti-radiation reinforcement characteristics of ultra-large-scale image sensors. The anti-radiation reinforcement structure proposed by the present invention is 48% smaller in area than the traditional H-gate anti-radiation reinforcement structure; and 73% smaller in area than the traditional ring-type gate structure, providing technical innovation support for the realization of ultra-high-resolution small-sized pixel anti-radiation reinforcement back-illuminated image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 It is an ultra-large-scale back-illuminated image sensor architecture;

[0025] Figure 2This is a pixel-level circuit schematic diagram suitable for small pixel sizes;

[0026] Figure 3 Schematic diagram of the P+ double half-surround gate anti-radiation reinforcement structure;

[0027] Figure 4 Schematic diagram of the leakage channel of the strip-gate structure;

[0028] Figure 5 Schematic diagram of leakage channel of double half-surround gate radiation hardened device;

[0029] Figure 6 Schematic diagram of the leakage channel of the P+ double half-surround gate radiation-hardened device;

[0030] Figure 7 A schematic diagram for AA formation;

[0031] Figure 8 Schematic diagram of N+ and P+ injection;

[0032] Figure 9 A schematic diagram of double half-encircling gate formation;

[0033] Figure 10 Schematic diagram for through-hole CT formation;

[0034] Figure 11 Schematic diagram of metal formation. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below with reference to specific embodiments, which are intended to explain the present invention rather than to limit it.

[0036] The present invention proposes a double semi-encircling gate anti-radiation reinforcement structure to solve the anti-radiation reinforcement problem under the condition of smaller pixel-level circuit area constraints.

[0037] Ultra-large-scale back-illuminated image sensor architecture Figure 1 As shown, the back-illuminated pixel layer and its readout circuit are 11, the interconnection structure between the back-illuminated pixel layer and its readout circuit and the carrier is 12, and the carrier is 13. Figure 2As shown, it is a pixel-level circuit applicable to small pixel sizes. 40 is an NMOS transistor controlled by Gpol and SH, characterized by the source and drain being connected, and other ports being independent; 41 is a source follower composed of two NMOS transistors, also characterized by the source and drain being connected, and other ports being independent. Using the traditional H-gate structure, if the connection method of the two NMOS transistors is the small-size connection of the H-gate of a common-source-drain device, it can meet the requirement of the source-drain connection of the two NMOS transistors, but the independent gates are connected to each other, causing errors. If the connection method of the two NMOS transistors is the large-size connection of the H-gate of a common-source-drain device, it can not only meet the requirement of the source-drain connection of the two NMOS transistors, but also meet the requirement of the independent gates, and the connection relationship is correct, but the area increases significantly, and it cannot meet the radiation hardening requirement of small pixel sizes.

[0038] The present invention proposes a P+ double semi-surrounding gate radiation hardening structure, as Figure 3 shown. Taking two NMOS transistors as an example, the positions of the source region and the drain region of the NMOS transistor can be interchanged. In this embodiment, the source region 50 of the NMOS1 transistor is the N-type doped injection region of the active region; the gate region 51 of the NMOS1 transistor; the drain regions 52 of the NMOS1 transistor and the NMOS2 transistor are the N-type doped injection regions of the active region; the gate region 53 of the NMOS2 transistor; the source region 54 of the NMOS2 transistor is the N-type doped injection region of the active region; the P-type doped injection region 55 of the active region.

[0039] The gate region 51 of the NMOS1 transistor and the gate region 53 of the NMOS second transistor have a C-shaped structure. The gate region 51 of the NMOS1 transistor and the gate region 53 of the NMOS2 transistor have an opening on only one side, and the other three sides are closed. The gate region 51 of the NMOS1 transistor and the gate region 53 of the NMOS2 transistor are symmetrically arranged. The opening directions of the gate region 51 of the NMOS1 transistor and the gate region 53 of the NMOS2 transistor deviate from the common active region, that is, the opening directions of the gate region 51 of the NMOS1 transistor and the gate region 53 of the NMOS2 transistor both point to the outer surrounding layer.

[0040] The double semi-surrounding gate radiation hardening technology proposed by the present invention reduces the layout area by half compared with the traditional H-gate structure, effectively expands the leakage channel distance between the source and the drain, and greatly reduces the source-drain leakage. The P+ injection protection ring surrounding structure is adopted to further block the leakage channel. Thus, radiation hardening under the condition of small-size pixels is achieved.

[0041] As Figure 4 shown, in the traditional strip gate structure, the radiation parasitic leakage channel at the edge of the field region is narrow, and there is significant radiation parasitic leakage at the edge of the field region after irradiation, which causes problems such as threshold voltage drift and bird's mouth edge leakage, resulting in increased power consumption and even functional errors.

[0042] As Figure 5As shown, the double half-surrounding gate anti-irradiation reinforcement device proposed in the patent of this invention, after irradiation, the parasitic leakage channel 63 of the irradiated NMOS1 tube and the parasitic leakage channel 64 of the NMOS2 tube at the edge of the field area are significantly increased, so the leakage situation is significantly suppressed.

[0043] like Figure 6 The figure shows the P+ double-half-surround gate radiation-hardened device proposed in this patent. After irradiation, the parasitic leakage channels 65 and 66 of the NMOS1 and NMOS2 transistors at the edge of the field region are completely blocked. Electrons generated by the irradiation at the field edge recombine with the P+ surround layer, which is primarily composed of holes, and no electrons can migrate to the other end. This effectively suppresses threshold voltage drift and bird's-beak edge leakage caused by radiation.

[0044] The present invention proposes a P+ double half-surrounded gate anti-radiation reinforcement structure, which is suitable for the circuit structure design of radiation-resistant small-size pixels in ultra-large-scale back-illuminated image sensors. For the source-drain connected dual NMOS structure, a double half-surrounded gate anti-radiation reinforcement technology is proposed. The dual NMOS is directly connected through the active area, the gate shape is C-shaped, and the opening direction is away from the shared active area. The overlapping part of the gate area and the active area is a thin oxygen area, which effectively suppresses the radiation leakage caused by the bird's beak edge effect and greatly reduces the area overhead compared to the traditional H-gate structure. For the source-drain connected dual NMOS structure, a P+ surrounded double half-surrounded gate structure is proposed. The P+ surrounding layer is used to isolate the source and drain areas of the NMOS tube in combination with the double half-surrounded gate structure to isolate all active areas from each other. Since the NMOS tube is electronically conductive, the radiation-induced electrons are combined by the holes in the P+ surrounding layer, completely blocking the leakage of the source and drain areas, greatly improving the recovery performance.

[0045] This invention innovatively proposes a P+ double semi-encircled gate radiation-hardened structure, specifically designed for small-size back-illuminated pixel circuits, to meet the radiation-hardening requirements of ultra-large-scale back-illuminated image sensors for space applications. Compared to traditional H-gate radiation-hardened structures, this proposed radiation-hardened structure is 48% smaller and 73% smaller than traditional ring-type gate structures, providing innovative technical support for the realization of ultra-high-resolution, small-size pixel radiation-hardened back-illuminated image sensors.

[0046] The present invention optimizes the traditional H-type gate structure and combines the characteristics of the double-device source-drain connection in the back-illuminated pixel schematic structure to innovatively propose a double semi-enclosed gate structure. At the same time, it adopts a P+ enclosed structure to completely block the leakage channel caused by radiation, thereby greatly improving the device's radiation resistance.

[0047] The present invention provides a method for preparing a back-illuminated pixel total dose resistance reinforcement structure, comprising the following steps:

[0048] like Figure 7 As shown, an active area AA layer is formed on a silicon wafer.

[0049] like Figure 8 As shown, N+ type doping and P+ type doping are respectively implanted on AA, N+ is implanted in the inner NMOS region, and P+ is implanted in the outer surrounding layer.

[0050] like Figure 9 As shown, a Poly type gate with a double semi-enclosed structure is formed on AA.

[0051] like Figure 10 As shown, a through hole CT is formed between the active area AA and the metal at the source and drain parts.

[0052] like Figure 11 As shown, metal is deposited in the source and drain regions.

[0053] The P+ double half-surround gate radiation-hardened device formed through the above process meets the radiation-hardening requirements of ultra-large-scale back-illuminated image sensors for small pixel sizes, thereby improving the resolution and radiation-hardening characteristics of ultra-large-scale back-illuminated image sensors. The double half-surround gate radiation-hardening technology significantly extends the conductive path length, significantly suppressing source-drain leakage. Combined with the P+ surround structure, it completely blocks the leakage path, significantly improving the device's radiation-hardening performance while minimizing area overhead.

Claims

1. A back-illuminated pixel total dose reinforcement structure, characterized in that: It includes the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor; The gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor are in a U-shaped structure, and the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor are symmetrically arranged. The opening directions of the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor are away from the common active region.

2. The back-illuminated pixel total dose reinforcement structure according to claim 1, characterized in that: There are drain regions of NMOS1 transistor and NMOS2 transistor between the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor. There is a source region of NMOS1 transistor at the opening of the gate region (51) of NMOS1 transistor, and there is a source region of NMOS1 transistor at the opening of the gate region (53) of NMOS2 transistor.

3. The back-illuminated pixel total dose reinforcement structure according to claim 1, characterized in that: There are source regions of NMOS1 transistor and NMOS2 transistor between the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor. There is a drain region of NMOS1 transistor at the opening of the gate region (51) of NMOS1 transistor, and there is a drain region of NMOS2 transistor at the opening of the gate region (53) of NMOS2 transistor.

4. The back-illuminated pixel total dose reinforcement structure according to claim 1, characterized in that: There is a P-type doping injection region (55) of the active region outside the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor.

5. The back-illuminated pixel total dose reinforcement structure according to claim 1, characterized in that: The overlapping part of the gate region (51) of NMOS1 transistor and the gate region (53) of NMOS2 transistor with the active region is a thin oxide region.

6. The back-illuminated pixel total dose reinforcement structure according to claim 1, characterized in that: The source and drain regions of NMOS1 transistor and NMOS2 transistor are N-type doping injection regions of the active region.

7. A method for preparing the back-illuminated pixel total dose reinforcement structure as claimed in claim 1, characterized in that: It includes the following processes, Form an active region AA layer on the silicon wafer; Inject N+ type doping and P+ type doping respectively on the active region AA layer. Inject N+ in the inner NMOS region to form the N-type doping injection region of the active region, and inject P+ in the outer surrounding layer to form the P-type doping injection region (55); Form a Poly gate with a double semi-surrounding structure on the upper N-type doping injection region in the active region AA layer; Form a through hole CT between the active region AA layer and the metal at the source and drain regions; Deposit metal at the source and drain regions to form a back-illuminated pixel anti-total-dose hardened structure.

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