Display panel and display device

Abstract

Disclosed are a display panel and a display device, wherein the display panel comprises: a substrate, comprising a display area, a peripheral area and a pad area; at least one barrier, arranged on the substrate, the barrier being located in the peripheral area and surrounding the display area, the barrier comprising a single-sided barrier structure located between the display area and the pad area; an organic insulating structure, comprising a plurality of stacked sub-insulating structures, each of which has a first boundary located between the display area and the single-sided barrier structure, and for any two adjacent sub-insulating structures, the first boundary of the sub-insulating structure on the side away from the substrate is closer to the display area than the first boundary of the sub-insulating structure on the side close to the substrate; a touch electrode pattern, arranged on a side of the organic insulating structure away from the substrate; and a touch signal line, arranged on a side of the organic insulating structure away from the substrate, the orthographic projection of a portion of the touch signal line in the peripheral area on the substrate intersecting with the first boundary of each sub-insulating structure.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] With the development of organic light emitting diode (OLED) display technology, OLED display devices are widely used. In order to meet users' requirements for product thickness and touch experience, in one production process, a touch function layer is made on the encapsulation layer of the OLED display panel. Summary of the invention

[0003] Embodiments of the present disclosure provide a display panel and a display device.

[0004] According to a first aspect of the present disclosure, there is provided a display panel, comprising:

[0005] A substrate, comprising a display area, a peripheral area and a pad area, wherein the peripheral area surrounds the display area, and the pad area is located at a side of the peripheral area away from the display area;

[0006] at least one barrier disposed on the substrate, the barrier being located in the peripheral area and surrounding the display area, the barrier comprising a single-sided barrier structure located between the display area and the pad area;

[0007] an organic insulating structure, arranged on the substrate, the organic insulating structure comprising a plurality of sub-insulating structures arranged in a stacked manner, a portion of each of the plurality of sub-insulating structures being located in the display area, and each of the plurality of sub-insulating structures having a first boundary located between the display area and the single-sided blocking structure, wherein, for any two adjacent sub-insulating structures, the first boundary of the sub-insulating structure away from the substrate side is closer to the display area than the first boundary of the sub-insulating structure close to the substrate side; and a spacing between the first boundaries of any two adjacent sub-insulating structures is greater than or equal to 20 μm;

[0008] A touch electrode pattern is arranged on a side of the organic insulating structure away from the substrate;

[0009] A touch signal line is arranged on a side of the organic insulating structure away from the substrate, one end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area, and the orthographic projection of the part of the touch signal line in the peripheral area on the substrate intersects with the first boundary of each of the sub-insulating structures.

[0010] In some embodiments, a distance between the first boundaries of any two adjacent sub-insulation structures is between 25 μm and 60 μm.

[0011] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure include:

[0012] A first planarization layer is disposed on the substrate;

[0013] A second planarization layer, located on a side of the first planarization layer away from the substrate;

[0014] The pixel defining layer is located on a side of the second planarization layer away from the substrate.

[0015] In some embodiments, a first boundary of the sub-insulation structure is spaced from the single-sided blocking structure.

[0016] In some embodiments, the display panel further comprises: an encapsulation layer disposed on a side of the organic insulating structure away from the substrate; wherein the touch electrode pattern and the touch signal line are both located on a side of the encapsulation layer away from the substrate.

[0017] In some embodiments, the encapsulation layer comprises:

[0018] a first inorganic encapsulation layer;

[0019] a second inorganic encapsulation layer, located on a side of the first inorganic encapsulation layer away from the substrate;

[0020] The organic encapsulation layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0021] In some embodiments, a groove is formed between the organic insulating structure and the single-sided blocking structure, the orthographic projection of the encapsulation layer on the substrate simultaneously covers the orthographic projection of the organic insulating structure on the substrate, the orthographic projection of the groove on the substrate, and the orthographic projection of the single-sided blocking structure on the substrate, and the single-sided blocking structure is located between the substrate and the encapsulation layer.

[0022] In some embodiments, the display panel further includes: a touch insulating layer, disposed on a side of the encapsulation layer away from the substrate;

[0023] The touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes are cross-arranged with the touch sensing electrodes, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is correspondingly connected to one of the touch signal lines.

[0024] In some embodiments, the touch driving electrode comprises: a plurality of driving electrode units arranged along a first direction, and a connecting portion connected between every two adjacent driving electrode units;

[0025] The touch sensing electrode comprises: a plurality of sensing electrode units arranged along the second direction, and a bridge portion connected between every two adjacent sensing electrode units;

[0026] The first direction intersects with the second direction, the driving electrode unit, the connecting portion and the sensing electrode unit are all located on a side of the touch insulating layer away from the substrate and on the same layer, and the bridging portion is located between the touch insulating layer and the packaging layer.

[0027] In some embodiments, the touch signal line includes a first transmission part and a second transmission part, the first transmission part is located between the touch insulation layer and the packaging layer, the second transmission part is located on a side of the touch insulation layer away from the packaging layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulation layer.

[0028] In some embodiments, the display area includes a plurality of pixel units, each pixel unit is provided with a light-emitting element, and the display panel also includes a power line, which is electrically connected to the light-emitting element, wherein the power line is located between the organic insulating structure and the substrate, and the orthographic projection of the power line on the substrate overlaps with the orthographic projection of the first boundary on the substrate.

[0029] In some embodiments, the barrier comprises:

[0030] A first barrier is located in the peripheral area and surrounds the display area;

[0031] A second barrier located in the peripheral area and surrounding the first barrier;

[0032] Wherein, a portion of the first barrier located between the display area and the pad area and a portion of the second barrier located between the display area and the pad area constitute the single-sided barrier structure.

[0033] In some embodiments, the substrate is a flexible substrate, which further includes a bending region between the peripheral region and the pad region.

[0034] In some embodiments, the display panel further comprises:

[0035] A first buffer layer is disposed on the substrate;

[0036] A semiconductor layer, disposed between the first buffer layer and the first planarization layer;

[0037] a first gate insulating layer, disposed between the semiconductor layer and the first planarization layer;

[0038] a first gate electrode layer, disposed between the first gate insulating layer and the first planarization layer;

[0039] a second gate insulating layer, disposed between the first gate electrode layer and the first planarization layer;

[0040] a second gate electrode layer, disposed between the second gate insulating layer and the first planarization layer;

[0041] an interlayer insulating layer, disposed between the second gate electrode layer and the first planarization layer;

[0042] A first source-drain conductive layer, disposed between the interlayer insulating layer and the first planarization layer;

[0043] A passivation layer, disposed between the first source-drain conductive layer and the first planarization layer;

[0044] A second source-drain conductive layer, disposed between the first planarization layer and the second planarization layer;

[0045] A first electrode layer is disposed between the second planarization layer and the pixel definition layer, the first electrode layer includes a plurality of first electrodes, and the pixel definition layer includes pixel openings corresponding to the first electrodes one by one;

[0046] A light emitting layer is disposed in the pixel opening;

[0047] A second electrode layer is arranged on a side of the light-emitting layer away from the substrate;

[0048] An encapsulation layer, disposed on a side of the light-emitting layer away from the substrate;

[0049] The second buffer layer is arranged on a side of the packaging layer away from the substrate.

[0050] According to a second aspect of the present disclosure, there is provided a display panel, comprising:

[0051] A substrate, comprising: a display area, a peripheral area and a pad area, wherein the peripheral area surrounds the display area, and the pad area is located at a side of the peripheral area away from the display area;

[0052] at least one barrier disposed on the substrate, the barrier being located in the peripheral area and surrounding the display area, the barrier comprising a single-sided barrier structure located between the display area and the pad area;

[0053] an organic insulating structure, disposed on the substrate, wherein a portion of the organic insulating structure is located in the display area, and another portion of the organic insulating structure is located in the peripheral area, the organic insulating structure having a bottom surface facing the substrate, a top surface opposite to the bottom surface, and a first side surface connected between the bottom surface and the top surface and facing the single-sided blocking structure, wherein the first side surface is a slope surface, and a slope angle of the slope surface is between 0° and 40°;

[0054] A touch electrode pattern is arranged on a side of the organic insulating structure away from the substrate;

[0055] A touch signal line is arranged on a side of the organic insulating structure away from the substrate, one end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area, and the orthographic projection of the part of the touch signal line in the peripheral area on the substrate passes through the orthographic projection of the slope surface on the substrate.

[0056] In some embodiments, the slope angle of the slope surface is between 25° and 35°.

[0057] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure include:

[0058] A first planarization layer is disposed on the substrate;

[0059] A second planarization layer, located on a side of the first planarization layer away from the substrate;

[0060] The pixel defining layer is located on a side of the second planarization layer away from the substrate.

[0061] In some embodiments, a gap exists between the first side surface and the single-sided blocking structure.

[0062] In some embodiments, the display panel further comprises: an encapsulation layer, disposed on a side of the organic insulating structure away from the substrate;

[0063] Wherein, the touch electrode pattern and the touch signal line are both located on a side of the packaging layer away from the substrate.

[0064] In some embodiments, the encapsulation layer comprises:

[0065] a first inorganic encapsulation layer;

[0066] a second inorganic encapsulation layer, located on a side of the first inorganic encapsulation layer away from the substrate;

[0067] The organic encapsulation layer is located between the first inorganic encapsulation layer and the second inorganic encapsulation layer.

[0068] In some embodiments, a groove is formed between the organic insulating structure and the single-sided blocking structure, the orthographic projection of the encapsulation layer on the substrate simultaneously covers the orthographic projection of the organic insulating structure on the substrate, the orthographic projection of the groove on the substrate, and the orthographic projection of the single-sided blocking structure on the substrate, and the single-sided blocking structure is located between the substrate and the encapsulation layer.

[0069] In some embodiments, the display panel further includes: a touch insulating layer, disposed on a side of the encapsulation layer away from the substrate;

[0070] The touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes are cross-arranged with the touch sensing electrodes, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is correspondingly connected to one of the touch signal lines.

[0071] In some embodiments, the touch driving electrode comprises: a plurality of driving electrode units arranged along a first direction, and a connecting portion connected between every two adjacent driving electrode units;

[0072] The touch sensing electrode comprises: a plurality of sensing electrode units arranged along the second direction, and a bridge portion connected between every two adjacent sensing electrode units;

[0073] The first direction intersects with the second direction, the driving electrode unit, the connecting portion and the sensing electrode unit are all located on a side of the touch insulating layer away from the substrate and on the same layer, and the bridging portion is located between the touch insulating layer and the packaging layer.

[0074] In some embodiments, the touch signal line includes a first transmission part and a second transmission part, the first transmission part is located between the touch insulation layer and the packaging layer, the second transmission part is located on a side of the touch insulation layer away from the packaging layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulation layer.

[0075] In some embodiments, the display area includes a plurality of pixel units, each pixel unit is provided with a light-emitting element, and the display panel also includes a power line, which is electrically connected to the light-emitting element, wherein the power line is located between the organic insulating structure and the substrate, and the orthographic projection of the power line on the substrate overlaps with the orthographic projection of the first side surface on the substrate.

[0076] In some embodiments, the barrier comprises:

[0077] A first barrier is located in the peripheral area and surrounds the display area;

[0078] A second barrier located in the peripheral area and surrounding the first barrier;

[0079] Wherein, a portion of the first barrier located between the display area and the pad area and a portion of the second barrier located between the display area and the pad area constitute the single-sided barrier structure.

[0080] In some embodiments, the substrate is a flexible substrate, which further includes a bending region between the peripheral region and the pad region.

[0081] In some embodiments, the display panel further comprises:

[0082] A first buffer layer is disposed on the substrate;

[0083] A semiconductor layer, disposed between the first buffer layer and the first planarization layer;

[0084] a first gate insulating layer, disposed between the semiconductor layer and the first planarization layer;

[0085] a first gate electrode layer, disposed between the first gate insulating layer and the first planarization layer;

[0086] a second gate insulating layer, disposed between the first gate electrode layer and the first planarization layer;

[0087] a second gate electrode layer, disposed between the second gate insulating layer and the first planarization layer;

[0088] an interlayer insulating layer, disposed between the second gate electrode layer and the first planarization layer;

[0089] A first source-drain conductive layer, disposed between the interlayer insulating layer and the first planarization layer;

[0090] A passivation layer, disposed between the first source-drain conductive layer and the first planarization layer;

[0091] A second source-drain conductive layer, disposed between the first planarization layer and the second planarization layer;

[0092] A first electrode layer is disposed between the second planarization layer and the pixel definition layer, the first electrode layer includes a plurality of first electrodes, and the pixel definition layer includes pixel openings corresponding to the first electrodes one by one;

[0093] A light emitting layer is disposed in the pixel opening;

[0094] A second electrode layer is arranged on a side of the light-emitting layer away from the substrate;

[0095] An encapsulation layer, disposed on a side of the light-emitting layer away from the substrate;

[0096] The second buffer layer is arranged on a side of the packaging layer away from the substrate.

[0097] According to a third aspect of the present disclosure, there is provided a display panel, comprising:

[0098] A substrate, comprising: a display area, a peripheral area and a pad area, wherein the peripheral area surrounds the display area, and the pad area is located at a side of the peripheral area away from the display area;

[0099] at least one barrier disposed on the substrate, the barrier being located in the peripheral area and surrounding the display area, the barrier comprising a single-sided barrier structure located between the display area and the pad area;

[0100] An organic insulating structure, arranged on the substrate, the organic insulating structure comprising a plurality of sub-insulating structures arranged in a stacked manner, a portion of each of the plurality of sub-insulating structures being located in the display area, each of the sub-insulating structures having a first boundary located between the display area and the single-sided blocking structure, and each of the sub-insulating structures except the sub-insulating structure farthest from the substrate comprises a protruding portion; wherein, for any two adjacent sub-insulating structures, the protruding portion of the sub-insulating structure close to the substrate is located between the first boundary of the sub-insulating structure farthest from the substrate and the single-sided blocking structure;

[0101] A touch electrode pattern is arranged on a side of the organic insulating structure away from the substrate;

[0102] A touch signal line is arranged on a side of the organic insulating structure away from the substrate, one end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area, and an orthographic projection of a portion of the touch signal line in the peripheral area on the substrate overlaps with an orthographic projection of an extended portion of each of the sub-insulating structures on the substrate;

[0103] The sub-insulating structure having the protruding portion is formed by patterning an organic material layer using a two-tone mask, wherein during the patterning process, the region where the protruding portion is to be formed corresponds to a semi-transparent region of the two-tone mask.

[0104] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure include:

[0105] A first planarization layer is disposed on the substrate;

[0106] A second planarization layer, located on a side of the first planarization layer away from the substrate;

[0107] The pixel defining layer is located on a side of the second planarization layer away from the substrate.

[0108] According to a fourth aspect of the present disclosure, a display device is provided, comprising the above-mentioned display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0109] The accompanying drawings are used to provide a further understanding of the present disclosure and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present disclosure but do not constitute a limitation of the present disclosure. In the accompanying drawings:

[0110] Figure 1 A schematic diagram of area division of a substrate of a display panel provided for some embodiments of the present disclosure.

[0111] Figure 2 A schematic plan view of a display panel provided for some embodiments of the present disclosure.

[0112] Figure 3 for Figure 2 Enlarged view of the Q1 region.

[0113] Figure 4 For along Figure 3 Sectional view along line A-A'.

[0114] Figure 5 Schematic diagram of a groove between an organic insulating structure and a single-sided blocking structure in some embodiments of the present disclosure.

[0115] Figure 6 Schematic diagram of an equivalent pixel circuit in some embodiments of the present disclosure.

[0116] Figure 7 For along Figure 2 Cross-sectional view along line BB'.

[0117] Figure 8 For along Figure 2 Sectional view along line D-D'.

[0118] Fig. 9 In some other embodiments of the present disclosure, Figure 3 Sectional view along line A-A'.

[0119] Fig.10 for Fig. 9 One of the structural schematic diagrams of the organic insulating structure.

[0120] Fig.11 for Fig. 9The second structural diagram of the organic insulating structure.

[0121] Figure 12 to Figure 14 A schematic diagram of a manufacturing process of a sub-insulating structure having a protruding portion provided in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0122] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0123] The terms used to describe the embodiments of the present disclosure herein are not intended to limit and / or define the scope of the present disclosure. For example, unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by a person with ordinary skills in the field to which the present invention belongs. It should be understood that the "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Unless the context clearly indicates otherwise, the singular form "one", "one" or "the" and other similar words do not indicate a quantity limit, but indicate that there is at least one. "Including" or "including" and other similar words mean that the elements or objects appearing in front of "including" or "including" cover the elements or objects listed after "including" or "including" and their equivalents, and do not exclude other elements or objects. "Connect" or "connected" and other similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0124] In the following description, when an element or layer is referred to as being "on" or "connected to" another element or layer, the element or layer may be directly on or directly connected to the other element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers. The term "and / or" includes any and all combinations of one or more of the associated listed items.

[0125] The present disclosure provides a display panel, which includes a substrate, Figure 1A schematic diagram of area division of a substrate of a display panel provided in some embodiments of the present disclosure, such as Figure 1 As shown, the substrate SUB includes: a display area DA, a peripheral area PA and a pad area WA, the peripheral area PA surrounds the display area DA, and the pad area WA is located on the side of the peripheral area PA away from the display area DA. Among them, components for displaying images can be set in the display area DA, such as pixel circuits, scan lines GL, data lines DL, light-emitting elements, etc. In addition, the display area DA can also be provided with a touch electrode pattern to realize the touch function. The pad area WA is located on one side of the peripheral area PA away from the display area DA, and the pad area WA includes a plurality of contact pads PAD (or pads), each of which is configured to electrically connect a signal line extending from the display area DA or the peripheral area PA. For example, the data line DL can be connected to the contact pad via a data connection line. The contact pad PAD can be exposed on the surface of the pad area WA, that is, not covered by any layer, so that it is convenient to electrically connect to the flexible printed circuit board FPCB (Flexible Print Circuit Board). The flexible printed circuit board FPCB is electrically connected to the external controller and is configured to transmit signals from the external controller. The contact pad PAD is electrically connected to each signal line, so as to realize mutual communication between the signal line and the flexible printed circuit board FPCB. Figure 1 The number and arrangement of the contact pads PAD are only for illustrative purposes and do not constitute a limitation on the contact pads PAD.

[0126] Figure 2 A schematic plan view of a display panel provided for some embodiments of the present disclosure, Figure 3 for Figure 2 A magnified view of the Q1 region. Figure 4 For along Figure 3 Please refer to the cross-sectional view of the A-A' line in the figure. Figures 1 to 4 The display panel 100 further includes at least one barrier 10, an organic insulating structure 20, a touch electrode pattern and a touch signal line TL.

[0127] The barrier 10 is disposed on the substrate SUB, and the barrier 10 is located in the peripheral area PA and surrounds the display area DA. The barrier 10 is used to block external water vapor or oxygen from entering the display area DA, thereby preventing the display effect from being affected. The barrier 10 includes a single-sided barrier structure located between the display area DA and the peripheral area PA. As a specific example, Figure 2As shown, the blocking portion 10 includes a first barrier 11 and a second barrier 12 surrounding the first barrier 11, the first barrier 11 includes a first blocking portion 111 located between the display area DA and the peripheral area PA, and the second barrier 12 includes a fourth blocking portion 121 located between the display area DA and the peripheral area PA. At this time, the first blocking portion 111 and the third blocking portion 121 constitute the single-sided blocking structure.

[0128] The organic insulating structure 20 is disposed on the substrate SUB. The organic insulating structure 20 includes a plurality of sub-insulating structures 21 stacked and arranged. A portion of each sub-insulating structure 21 is located in the display area DA, and another portion is located in the peripheral area PA. For example, the orthographic projection of the sub-insulating structure 21 on the substrate SUB extends from the display area DA to between the display area DA and the barrier 10. Each sub-insulating structure 21 has a first boundary E1, and for any two adjacent sub-insulating structures 21, the first boundary E1 of the sub-insulating structure 21 on the side away from the substrate SUB is closer to the display area DA than the first boundary E1 of the sub-insulating structure 21 on the side close to the substrate SUB, thereby forming a step shape (see Figure 4 As shown in ). The distance d between the first boundaries E1 of two adjacent sub-insulation structures 21 is greater than or equal to 20 μm. It should be noted that, in order to clearly illustrate the positional relationship between the first boundaries E1 of each sub-insulation structure 21, Figure 3 Only for Figure 2 The Q1 region in FIG. 1 is enlarged, but it should be understood that each first boundary E1 is not only located at Figure 2 The Q1 region in Figure 2 The entire lower edge of the display area DA, that is, the first boundary E1 is from Figure 2 The left end of the middle Q region extends to the right end. Accordingly, the organic insulating structure 20 is not only formed in the Q1 region Figure 4 The step-like morphology in the PDMS layer is also formed in the entire Q region.

[0129] The touch electrode pattern is disposed on a side of the organic insulating structure 20 away from the substrate SUB. The touch electrode pattern is configured to detect the occurrence of a touch in the display area DA. For example, the touch electrode pattern includes Figure 2 The touch driving electrodes TX and the touch sensing electrodes TX shown in FIG.

[0130] The touch signal line TL is arranged on a side of the organic insulating structure 20 away from the substrate SUB, one end of the touch signal line TL is electrically connected to the touch electrode pattern, and the other end is connected to the pad area WA, thereby being electrically connected to the contact pad PAD in the pad area WA. The orthographic projection of the portion of the touch signal line TL in the peripheral area PA on the substrate SUB intersects with the first boundary E1 of each sub-insulating structure 21.

[0131] When the distance d between the first boundaries E1 of two adjacent sub-insulating structures 21 is small (for example, d is less than or equal to 5 μm), the touch signal line TL is located on a steeper slope. In this case, when the touch signal line TL is formed by an etching process, conductive residues are easily generated between the touch signal lines TL, thereby causing a short circuit between the touch signal lines TL. In the embodiment of the present disclosure, in each sub-insulating structure 21 of the organic insulating structure 20, the distance d between the first boundaries E1 of two adjacent sub-insulating structures 21 is large, so that the touch signal line TL is located on a gentler slope, which is conducive to reducing the conductive residues, thereby reducing or preventing the short circuit between the touch signal lines TL.

[0132] In some embodiments, the distance d between the first edges E1 of two adjacent sub-insulating structures 21 is between 25 μm and 60 μm, thereby reducing the conductive residue as much as possible and reducing the border of the display panel 100. For example, d is 30 μm, or 35 μm, or 40 μm, or 45 μm, or 50 μm.

[0133] Combine the following Figures 1 to 8 The display panel provided in the embodiments of the present disclosure is introduced in detail.

[0134] like Figure 2 As shown, the barrier 10 includes: a first barrier 11 and a second barrier 12. The first barrier 11 is located in the peripheral area PA and surrounds the display area DA. The second barrier 12 is located in the peripheral area PA and surrounds the first barrier 11, thereby further preventing external water vapor or oxygen from entering the display area DA, providing double protection for the display area DA. In some embodiments, the vertical distance from the end of the first barrier 11 away from the substrate SUB to the substrate SUB is smaller than the vertical distance from the end of the second barrier 12 away from the substrate SUB to the substrate SUB, thereby extending the path for external water vapor and oxygen to enter the display area DA, thereby improving the blocking ability of the barrier 10. The first barrier 11 includes a first barrier portion 111 and a second barrier portion 112, wherein the first barrier portion 111 is located on the side of the display area DA close to the bending area (i.e., Figure 2 The second barrier 112 is the remaining portion of the first barrier 11 except the first barrier 111. The second barrier 12 includes a third barrier 121 and a fourth barrier 122. The third barrier 121 is located on one side of the display area DA close to the bending area (i.e., Figure 2 The fourth barrier 122 is the rest of the second barrier 12 except the third barrier 121. The first barrier 111 and the third barrier 113 constitute the above-mentioned single-sided barrier structure.

[0135] In some embodiments, the substrate SUB is a flexible substrate, which can be made of a flexible organic material. For example, the organic material is a resin material such as polyimide, polycarbonate, polyacrylate, polyetherimide, polyethersulfone, polyethylene terephthalate and polyethylene naphthalate. The substrate SUB also includes a bending area BA located between the peripheral area PA and the pad area WA. The bending area BA is configured to bend along the bending axis BX. By bending the bending area BA, the pad area WA can be placed on the back side of the display panel 100 (wherein the display side of the display panel 100 is the front side, and the side opposite to the display side is the back side or back side), thereby improving space utilization and reducing the border width of the display product.

[0136] In some embodiments, the display area DA includes a plurality of pixel units P, and the pixel units P are defined by the intersection of the scan lines GL and the data lines DL. The scan lines GL are connected to the gate drive circuit in the peripheral area PA, and the data lines DL can be connected to the contact pads PAD of the pad area WA through the data connection lines. A light-emitting element 50 and a pixel circuit are provided in each pixel unit P. The light-emitting element 50 can be an organic light-emitting diode OLED (Organic Light-Emitting Diode), and the organic light-emitting diode OLED can emit, for example, red light, green light, blue light or white light. Figure 6 is an equivalent schematic diagram of a pixel circuit in some embodiments of the present disclosure, such as Figure 6 As shown, the pixel circuit includes: a driving transistor Td, a switching transistor Ts and a storage capacitor Cs, the gate of the switching transistor Ts is connected to the scanning line GL, the first electrode is connected to the data line DL, and the second electrode is connected to the gate of the driving transistor Td. The two ends of the storage capacitor Cs are respectively connected to the first power line VDD and the gate of the driving transistor Td. The first electrode of the driving transistor Td is connected to the first power line VDD, the second electrode is connected to the first electrode of the light-emitting element 50, and the second electrode of the light-emitting element 50 is connected to the second power line VSS. Among them, each transistor can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, there is no difference between its source and drain. In order to distinguish the source and drain of the transistor, one of the electrodes is called the first electrode and the other electrode is called the second electrode.

[0137] The first power line VDD is connected from the pad area WA to the display area DA, thereby transmitting a voltage signal to each pixel unit. The second power line VSS includes a first portion and a second portion, wherein the first portion is located in the peripheral area PA and surrounds the display area DA in an open loop. The second portion of the second power line VSS is connected between the first portion and the contact pad PAD of the pad area WA. Figure 2 and Figure 4As shown, the orthographic projection of the first boundary E1 of each sub-insulating structure 21 on the substrate SUB overlaps with the orthographic projection of the second power line VSS on the substrate SUB.

[0138] In some embodiments, the touch electrode pattern may adopt a mutual capacitance structure or a self-capacitance structure. The embodiments of the present disclosure are described by taking the mutual capacitance structure as an example. Figure 2 As shown, the touch electrode pattern includes a plurality of touch driving electrodes TX and a plurality of touch sensing electrodes RX. The touch driving electrodes TX and the touch sensing electrodes RX are arranged to cross each other. The crossings of the touch driving electrodes TX and the touch sensing electrodes RX are insulated and spaced apart by a touch insulating layer TLD. Figure 7 For along Figure 2 The cross-sectional view of the B-B' line, combined with Figure 2 and Figure 7 As shown, the touch driving electrode TX includes: a plurality of driving electrode units TX1 arranged along a first direction and a connecting portion TX2 connected between the driving electrode units TX1, and the touch sensing electrode RX includes a plurality of sensing electrode units RX1 and a bridging portion RX2 connected between the sensing electrode units, wherein the first direction intersects the second direction, for example, the first direction is Figure 2 The up and down directions in the second direction are Figure 2 The driving electrode unit TX1, the connecting portion TX2 and the sensing electrode unit RX1 are all located on the side of the touch insulating layer TLD away from the substrate SUB, and the driving electrode unit TX1, the connecting portion TX2 and the sensing electrode unit RX1 can be arranged on the same layer, and the bridge portion RX2 is located on the side of the touch insulating layer TLD close to the substrate SUB. The bridge portion RX2 is arranged crosswise with the connecting portion TX2 and is separated by the touch insulating layer TLD. The sensing electrode unit RX1 is connected to the bridge portion RX2 through a via on the touch insulating layer TLD. It should be noted that Figure 2 and Figure 7 The touch driving electrodes TX and touch sensing electrodes RX shown in the figure are only exemplary and do not constitute a limitation to the present disclosure. For example, the bridge portion RX2 may be located on the side of the touch insulating layer TLD away from the substrate SUB, and the connecting portion may be located on the side of the touch insulating layer TLD close to the substrate SUB. For another example, adjacent driving electrode units TX1 are connected by bridge portions provided on different layers, and adjacent sensing electrode units RX1 are connected by connecting portions on the same layer.

[0139] Among them, each touch drive electrode TX and touch sensing electrode RX can be connected to a corresponding touch drive line TL. When the touch signal line TL passes through the peripheral area PA, the orthographic projection of the part of the touch signal line TL in the peripheral area PA on the substrate SUB intersects with the first boundary E1 of each sub-insulating structure 21. In one example, the touch insulation layer TLD at least also covers the peripheral area PA between the display area DA and the pad area WA, and the touch signal line TL in the peripheral area PA between the display area DA and the pad area WA is located on the touch insulation layer TLD. In one example, the thickness of the touch insulation layer TLD is between 0.2μm and 0.5μm, for example, 0.3μm or 0.33μm or 0.35μm.

[0140] In some embodiments, Figure 4 As shown, the touch signal line TL is a double-layer structure, which includes a first transmission part TL1 and a second transmission part TL2. The first transmission part TL1 is located on the side of the touch insulation layer TLD close to the substrate SUB, and the second transmission part TL2 is located on the side of the touch insulation layer TLD away from the substrate SUB. The second transmission part TL2 is electrically connected to the first transmission part TL1 through a via hole penetrating the touch insulation layer TLD. It should be noted that in order to schematically show the connection method of the second transmission part TL2 and the first transmission part TL1, Figure 4 Only one via hole is shown, but in fact, multiple via holes can be set at other positions, so that the second transmission part TL2 is connected in parallel with the first transmission part TL1 through multiple via holes. The first transmission part TL1 can be set on the same layer as the bridge part RX2, and the second transmission part TL2 can be set on the same layer as the driving electrode unit TX1, the connecting part TX2 and the sensing electrode unit RX1.

[0141] like Figure 7 As shown, the first buffer layer BFL1 is disposed on the substrate SUB to prevent or reduce the diffusion of metal atoms and / or impurities from the substrate SUB into the active layer of the transistor. In the embodiment of the present disclosure, the first buffer layer BFL1 may expose the upper surface of a portion of the substrate SUB located in the bending area BA to facilitate bending of the substrate SUB. For example, the first buffer layer BFL1 may include an inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx) and / or silicon oxynitride (SiON), and may be formed as a multilayer or a single layer.

[0142] The semiconductor layer is arranged on the first buffer layer BFL1. The material of the semiconductor layer may include, for example, inorganic semiconductor materials (e.g., polycrystalline silicon, amorphous silicon, etc.), organic semiconductor materials, and oxide semiconductor materials. The semiconductor layer includes an active layer 31 of each transistor 30, and the active layer 31 includes a channel portion and a source connection portion and a drain connection portion located on both sides of the channel portion, the source connection portion is connected to the source 33 of the transistor 30, and the drain connection portion is connected to the drain 34 of the transistor 30. Both the source connection portion and the drain connection portion may be doped with impurities (e.g., N-type impurities or P-type impurities) with a higher impurity concentration than the channel portion. The channel portion is directly opposite to the gate 32 of the transistor 30. When the voltage signal loaded on the gate 32 reaches a certain value, a carrier path is formed in the channel portion, forming a source 33 and a drain 34 of the transistor 30 to be turned on.

[0143] The first gate insulating layer GI1 is disposed on the semiconductor layer, wherein the first gate insulating layer GI1 may expose a portion of the upper surface of the substrate SUB located in the bending area BA to facilitate bending of the substrate SUB. The material of the first gate insulating layer GI1 may include silicon compounds and metal oxides. For example, the material of the first gate insulating layer GI1 includes silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. In addition, the first gate insulating layer GI1 may be a single layer or a multilayer.

[0144] The first gate electrode layer G1 is disposed on the first gate insulating layer GI1. The first gate electrode layer G1 includes the gates 32 of each transistor 30 and the first electrode plate 41 of the capacitor 40. The material of the first gate electrode layer G1 may include, for example, metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. For example, the first gate electrode layer G1 may include gold (Au), gold alloy, silver (Ag), silver alloy, aluminum (Al), aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The first gate electrode layer G1 may have a single layer or multiple layers.

[0145] like Figure 7As shown, the second gate insulating layer GI2 is disposed on the first gate electrode layer G1, and the second gate insulating layer GI2 may expose the upper surface of a portion of the substrate SUB located in the bending area BA. The material of the second gate insulating layer GI2 may include, for example, silicon compounds, metal oxides. For example, the material of the second gate insulating layer GI2 may include silicon oxynitride (SiON), silicon oxide (SiOx), silicon nitride (SiNx), silicon oxycarbide (SiOxCy), silicon carbide nitride (SiCxNy), aluminum oxide (AlOx), aluminum nitride (AlNx), tantalum oxide (TaOx), hafnium oxide (HfOx), zirconium oxide (ZrOx), titanium oxide (TiOx), etc. The second gate insulating layer GI2 may be formed as a single layer or a multilayer.

[0146] like Figure 7 As shown, the second gate electrode layer G2 is disposed on the second gate insulating layer GI2. The second gate electrode layer G2 may include a second electrode plate 42 of the capacitor 40. The material of the second gate electrode layer G2 may include, for example, a metal, a metal alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the gate electrode layer may include gold (Au), a gold alloy, silver (Ag), a silver alloy, aluminum (Al), an aluminum alloy, aluminum nitride (AlNx), tungsten (W), tungsten nitride (WNx), copper (Cu), a copper alloy, nickel (Ni), chromium (Cr), chromium nitride (CrNx), molybdenum (Mo), a molybdenum alloy, titanium (Ti), titanium nitride (TiNx), platinum (Pt), tantalum (Ta), tantalum nitride (TaNx), neodymium (Nd), scandium (Sc), strontium ruthenium oxide (SRO), zinc oxide (ZnOx), tin oxide (SnOx), indium oxide (InOx), gallium oxide (GaOx), indium tin oxide (ITO), indium zinc oxide (IZO), etc. The second gate electrode layer G2 may have a single layer or a multi-layer.

[0147] like Figure 7 As shown, the interlayer insulating layer ILD is disposed on the second gate electrode layer G2, and the interlayer insulating layer ILD can expose the upper surface of a portion of the substrate SUB located in the bending area BA. The material of the interlayer insulating layer ILD may include, for example, silicon compounds, metal oxides, etc. Specifically, the silicon compounds and metal oxides listed above may be selected, and will not be repeated here.

[0148] The first source-drain conductive layer SD1 is disposed on the interlayer insulating layer ILD. The first source-drain conductive layer SD1 may include a source 33 and a drain 34 of each transistor in the display area DA, the source 33 is electrically connected to the source connection portion, and the drain 34 is electrically connected to the drain connection portion. The first source-drain conductive layer SD1 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. For example, the first source-drain conductive layer SD1 may be a single layer or multiple layers composed of a metal, such as Mo / Al / Mo or Ti / Al / Ti. Figure 7 The transistor 30 shown includes a gate 32, a source 33, a drain 34 and an active layer 31. Figure 7 The transistor 30 shown may be Figure 6 The driving transistor Td of the pixel circuit shown in the figure, but it should be noted that when the pixel circuit adopts other circuit structures, the driving transistor Td is not necessarily directly connected to the light emitting element 50. In this case, Figure 7 The transistor shown in FIG. 1 does not necessarily correspond to the driving transistor Td. In addition, the first source-drain conductive layer SD1 may further include a first power line VDD and a second power line VSS.

[0149] The passivation layer PVX is disposed on the first source-drain conductive layer SD1 and may expose a surface of a portion of the substrate SUB located at the bent portion BA. The material of the passivation layer PVX may include a silicon compound, for example, silicon oxide, silicon nitride, or silicon oxynitride.

[0150] In some embodiments, Figure 4 As shown, the multiple sub-insulating structures 21 of the organic insulating structure 20 include: a first planarization layer PLN1, a second planarization layer PLN2 and a pixel defining layer PDL. The first planarization layer PLN1, the second planarization layer PLN2 and the pixel defining layer PDL each include a portion located in the display area DA and a portion located between the display area DA and the barrier 10. Among them, the second planarization layer PLN2 is located on the side of the first planarization layer PLN1 away from the substrate SUB. The pixel defining layer PDL is located on the side of the second planarization layer PLN2 away from the substrate SUB. The above-mentioned first buffer layer BFL1, semiconductor layer, first gate insulating layer GI1, first gate electrode layer G1, second gate insulating layer GI2, second gate electrode layer G2, interlayer insulating layer ILD, first source and drain conductive layer SD1, and passivation layer PVX are all located between the first planarization layer PLN1 and the substrate SUB. The surface of the first planarization layer PLN1 away from the substrate SUB is substantially flat. The first planarization layer PLN1 is made of an organic insulating material, for example, the organic insulating material includes resin materials such as polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane, etc. For another example, the organic insulating material includes an elastic material, for example, urethane, thermoplastic polyurethane (TPU), etc.

[0151] In one example, the thickness of the first planarization layer PLN1 and the second planarization layer PLN2 is between 1 μm and 2 μm, for example, the thickness of the first planarization layer PLN1 and the second planarization layer PLN2 is 1.6 μm. The thickness of the pixel definition layer PDL is between 1.5 μm and 3 μm, for example, 2 μm.

[0152] like Figure 7As shown, the second source-drain conductive layer SD2 is arranged on the first planarization layer PLN1. The second source-drain conductive layer SD2 may include a switching electrode 60 located in the display area DA. Among them, the switching electrode 60 is electrically connected to the drain 34 through a via hole penetrating the first planarization layer PLN1 and the passivation layer PVX. At the same time, the switching electrode 60 is also electrically connected to the first electrode 51 of the light-emitting element 50 through a via hole penetrating the second planarization layer PLN2. The switching electrode 60 can avoid directly forming a via with a relatively large aperture in the first planarization layer PLN1 and the second planarization layer PLN2, thereby improving the quality of the electrical connection of the via hole. The material of the second source-drain conductive layer SD2 may include metal, alloy, metal nitride, conductive metal oxide or transparent conductive material, for example, the second source-drain conductive layer SD2 may be a single layer or multiple layers composed of metal, for example, Mo / Al / Mo or Ti / Al / Ti. The material of the second source-drain conductive layer SD2 may be the same as or different from the material of the first source-drain conductive layer SD1.

[0153] like Figure 7 As shown, the second planarization layer PLN2 is arranged on the second source-drain conductive layer SD2, the second planarization layer PLN2 covers the switching electrode, and the upper surface of the second planarization layer PLN2 is basically flat. It can have a basically flat upper surface. The second planarization layer PLN2 is made of organic insulating material, for example, the organic insulating material includes polyimide, epoxy resin, acrylic, polyester, photoresist, polyacrylate, polyamide, siloxane and other resin materials. For another example, the organic insulating material includes elastic materials, such as ethyl formate, thermoplastic polyurethane (TPU), etc. The material of the second planarization layer PLN2 can be the same as or different from the material of the first planarization layer PLN1.

[0154] The first electrode layer is disposed on the second planarization layer PLN2, wherein the first electrode layer includes a plurality of first electrodes, and the first electrode may be an anode of the light emitting element 50. Figure 7 As shown, the light emitting element 50 includes a first electrode 51, a light emitting layer 53 and a second electrode 52, and the first electrode 51 is arranged on the second planarization layer PLN2. The first electrode 51 is electrically connected to the transfer electrode 60 through a via hole penetrating the second planarization layer PLN2, and then electrically connected to the drain 34 of the transistor 30. The first electrode 51 can be made of materials such as metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. The first electrode 51 can be a single layer or a multilayer structure.

[0155] The pixel defining layer PDL is arranged on the second planarization layer PLN2. The pixel defining layer PDL includes pixel openings corresponding to the pixel units one by one, and the pixel openings expose a portion of the corresponding first electrode 51. The light-emitting layer 54 is arranged in the pixel openings one by one, and the light-emitting layer 54 may include a small molecule organic material or a polymer molecule organic material, which may be a fluorescent luminescent material or a phosphorescent luminescent material, and may emit red light, green light, blue light, or white light. The material of the pixel defining layer PDL may include organic insulating materials such as polyimide, polyphthalimide, polyphthalamide, acrylic resin, benzocyclobutene or phenolic resin. In addition, a spacer ( Figure 7 (not shown in the figure), the material of the spacer may be the same as that of the pixel definition layer PDL.

[0156] The second electrode 52 is located on the side of the light-emitting layer 53 away from the substrate SUB, and the second electrode 52 can be made of metal, metal alloy, metal nitride, conductive metal oxide, transparent conductive material, etc. In the embodiment of the present disclosure, the light-emitting element 50 can adopt a top emission structure or a bottom emission structure. When the top emission structure is adopted, the first electrode 51 includes a conductive material with light reflection performance or includes a light reflection film, and the second electrode 52 includes a transparent or translucent conductive material. When the bottom emission structure is adopted, the second electrode 52 includes a conductive material with light reflection performance or includes a light reflection film, and the first electrode 51 includes a transparent or translucent conductive material. The second electrodes 52 of the light-emitting elements 50 of each pixel unit can be connected as a whole to form a second electrode layer.

[0157] It should be noted that the light-emitting element 50 may also include other film layers, for example, it may also include: a hole injection layer and a hole transport layer located between the first electrode 51 and the light-emitting layer 53 , and an electron transport layer and an electron injection layer located between the light-emitting layer 53 and the second electrode 52 .

[0158] like Figure 4 and Figure 7As shown, the display panel 100 further includes an encapsulation layer EPL, which is disposed on the pixel definition layer PDL. The encapsulation layer EPL covers the pixel definition layer PDL and the light emitting element 50, and is used to encapsulate the light emitting element 50 to prevent water vapor and / or oxygen in the external environment from corroding the light emitting element 50. In some embodiments, the encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP, the second inorganic encapsulation layer CVD2 is located on a side of the first inorganic encapsulation layer CVD1 away from the substrate SUB, and the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2. Optionally, the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 extend to the peripheral area PA and cover the barrier 10; the organic encapsulation layer IJP extends to the peripheral area PA and is located within the range surrounded by the barrier 10. The first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 can be made of inorganic materials with high density such as silicon oxynitride (SiON), silicon oxide (SiOx), and silicon nitride (SiNx). The organic encapsulation layer IJP can be made of a polymer material containing a desiccant, or a polymer material that can block water vapor. For example, a polymer resin is used to relieve the stress of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2, and a water-absorbing material such as a desiccant can also be included to absorb water, oxygen, and other substances that invade the interior.

[0159] In one example, the thickness of the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 are both between 0.5 μm and 1.5 μm. For example, the thickness of the first inorganic encapsulation layer CVD1 is 1.0 μm, and the thickness of the second inorganic encapsulation layer CVD2 is 0.6 μm. The thickness of the organic encapsulation layer IJP in the display area DA is between 5 μm and 10 μm, for example, 8 μm, or 7 μm, or 9 μm.

[0160] The second buffer layer BFL2 is disposed on the encapsulation layer EPL, and the second buffer layer BFL2 is located in the display area DA and extends to the peripheral area PA to cover the encapsulation layer EPL. The second buffer layer BFL2 can be made of the same material as the aforementioned first buffer layer BFL1, which will not be repeated here. The touch electrode pattern is located on the side of the encapsulation layer EPL away from the substrate SUB, and the bridge portion RX2 of the touch electrode pattern is disposed on the encapsulation layer EPL. The touch insulating layer TLD is located on the side of the encapsulation layer EPL away from the substrate SUB and covers the bridge portion RX2. The sensing electrode unit RX1 of the touch drive electrode TX and the touch sensing electrode RX is located on the touch insulating layer TLD. In order not to affect the display, the drive electrode unit TX1 and the sensing electrode unit RX1 both adopt a structure with good light transmittance. For example, it is made of a transparent conductive material (such as indium tin oxide), or a metal grid structure is adopted.

[0161] The touch electrode pattern and the touch insulating layer TLD are both located on the side of the encapsulation layer EPL away from the substrate SUB, and the bridge portion RX2 in the touch electrode pattern is located between the touch insulating layer TLD and the encapsulation layer EPL. The bridge portion RX2 and the first transmission portion TL1 are both located between the touch insulating layer TLD and the second buffer layer BFL2.

[0162] like Figure 4 As shown, there is a gap between the first boundary of each sub-insulating structure 21 and the single-sided blocking structure, that is, each sub-insulating structure 21 does not contact the single-sided blocking structure. At this time, a groove is formed between the organic insulating structure 20 and the single-sided blocking structure. Figure 5 is a schematic diagram of a groove between an organic insulating structure and a single-sided blocking structure in some embodiments of the present disclosure, Figure 5 That is, after the organic insulating structure 20 and the barrier 10 are formed and before the encapsulation layer EPL is formed, Figure 3 Sectional view of line AA'. Figure 4 and Figure 5 As shown, the orthographic projection of the encapsulation layer EPL on the substrate SUB simultaneously covers the orthographic projection of the organic insulating structure 20 on the substrate SUB, the orthographic projection of the groove V1 on the substrate SUB, and the orthographic projection of the single-sided blocking structure on the substrate SUB.

[0163] The overcoat layer OC is disposed on the side of the touch electrode pattern away from the substrate SUB. The overcoat layer OC extends from the display area DA to the peripheral area PA, and the overcoat layer OC can protect the touch signal line TL in the peripheral area PA. The material of the overcoat layer OC may include an inorganic insulating material or an organic insulating material.

[0164] The flexible substrate SUB of the embodiment of the present disclosure is provided with a first gate insulating layer GI1, a second gate insulating layer GI2, a first buffer layer BFL1, and a second buffer layer BFL2. However, it can be understood that in some examples, these layers can be deleted or added according to actual needs, and the present disclosure does not specifically limit this.

[0165] Figure 8 For along Figure 2 A cross-sectional view taken along line D-D' is shown in FIG. 1 , wherein the structure of the barrier 10 is illustrated concisely and clearly. Figure 8 Only the cross-sectional structure of the barrier 10 and the first inorganic encapsulation layer and the second inorganic encapsulation layer on the barrier 10 are shown. Figure 2 , Figure 4 and Figure 8As shown, the first barrier 111, the second barrier 112, the third barrier 113 and the fourth barrier 114 all include a first barrier layer 11a and a second barrier 11b located on the first barrier 11a, wherein the first barrier 11a is disposed in the same layer as the second planarization layer PLN2 and is made of the same material, and the second barrier 11b is disposed in the same layer as the pixel definition layer PDL and is made of the same material. Figure 4 As shown, the third barrier portion 121 further includes a third barrier layer 11c, which is disposed in the same layer as the first planarization layer PLN1 and made of the same material. Figure 8 As shown, the second barrier 112 includes a first barrier layer 11a, a second barrier layer 11b, and a fourth barrier layer 11d, which is disposed on the same layer and made of the same material as the spacer on the pixel definition layer PDL. The fourth barrier 122 includes a first barrier layer 11a, a second barrier layer 11b, a third barrier layer 11c, and a fourth barrier layer 11d.

[0166] It should be noted that the "same-layer arrangement" in the embodiments of the present disclosure means that the two structures are formed by the same material layer through a patterning process, so the two structures are in the same layer in terms of stacking relationship; however, this does not mean that the distances between the two structures and the substrate SUB must be the same. Figure 5 and Figure 8 As shown in FIG. 1 , the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2 in the encapsulation layer EPL both extend onto the first barrier 11 and the second barrier 12 .

[0167] In some embodiments, the peripheral area PA of the substrate SUB includes a first fan-out area FA1, which is located between the display area DA and the bending area BA. After the data connection line is connected to the data line DL, it extends to the pad area WA through the first fan-out area FA1 and the bending area BA. The substrate SUB also includes a second fan-out area FA2, which is located between the bending area BA and the pad area WA and adjacent to the bending area BA, that is, the second fan-out area FA2 is adjacent to the bending area BA and is directly connected to each other, and there is no other area between the two areas. A test area DTA, a control circuit area CCA, a third fan-out area FA3, and an integrated circuit area IC are also provided between the second fan-out area and the pad area WA of the substrate SUB. In at least one example, the test area DTA is configured to connect an external test device to detect the screen, the disconnection of the bending area BA, etc. In at least one example, the control circuit area CCA includes a selector MUX for switching between the input circuit and the output circuit.

[0168] Some other embodiments of the present disclosure further provide a display panel, comprising: a substrate, a barrier, an organic insulating structure, a touch electrode pattern and a touch signal line. The substrate comprises: a display area, a peripheral area and a pad area, wherein the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area. A barrier is disposed on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier comprises a single-sided barrier structure located between the display area and the pad area. An organic insulating structure is disposed on the substrate, and a portion of the organic insulating structure is located in the display area, and another portion is located in the peripheral area.

[0169] Fig. 9 In some other embodiments of the present disclosure, Figure 3 The cross-sectional view of the A-A' line, Fig.10 for Fig. 9 One of the structural diagrams of the organic insulating structure in the figure. Fig.11 for Fig. 9 The second schematic diagram of the organic insulating structure in the invention. Figure 2 , Figures 9 to 11 As shown, the organic insulating structure 20 has a bottom surface BS facing the substrate SUB, a top surface TS opposite to the bottom surface BS, and a first side surface LS connected between the bottom surface BS and the top surface TS and facing the single-sided blocking structure. The first side surface LS is a slope surface, and the slope angle of the slope surface is between 0 and 40°.

[0170] It should be noted that the "slope surface" here refers to a surface that gradually approaches the display area DA in a direction away from the substrate SUB. The slope surface can be an inclined plane (such as Fig.10 As shown), it can also be an inclined arc surface (as shown Fig.11 When the slope surface is a plane, its slope angle refers to the angle θ1 between the slope surface and the bottom surface BS of the organic insulating structure 20; when the slope surface is a curved surface, its slope angle refers to the maximum value θ2 of the angle between the tangent of the curved surface and the bottom surface BS of the organic insulating structure 20. It should also be noted that the slope surface is not only located in the Q1 region, but extends from the left end to the right end of the Q region.

[0171] Combination Figure 2 and Fig. 9 As shown, the touch electrode pattern (ie Figure 2 The organic insulating structure 20 (including the pattern of touch driving electrodes TX and touch sensing electrodes RX) is arranged on the side of the organic insulating structure 20 away from the substrate SUB. The touch signal line TL is arranged on the side of the organic insulating structure 20 away from the substrate SUB, one end of the touch signal line TL is electrically connected to the touch electrode pattern, and the other end is connected to the pad area WA. The orthographic projection of the portion of the touch signal line TL in the peripheral area PA on the substrate SUB passes through the orthographic projection of the slope surface on the substrate SUB.

[0172] In some embodiments, the slope angle of the slope surface is between 25° and 35°, thereby reducing the conductive residue and preventing the frame of the display product from being too wide. For example, the slope angle is 28°, 29°, 30°, 31°, or 32°.

[0173] like Fig. 9 As shown, the organic insulating structure 20 includes a plurality of sub-insulating structures 21 stacked, and the plurality of sub-insulating structures 21 include: a first planarization layer PLN1, a second planarization layer PLN2, and a pixel defining layer PDL. The first planarization layer PLN1 is disposed on a substrate SUB. The second planarization layer PLN2 is located on a side of the first planarization layer PLN1 away from the substrate SUB. The pixel defining layer PDL is located on a side of the second planarization layer PLN2 away from the substrate SUB.

[0174] An encapsulation layer EPL, a second buffer layer BFL2, and a touch insulating layer TLD are also provided on the organic insulating structure 20. The encapsulation layer EPL includes a first inorganic encapsulation layer CVD1, a second inorganic encapsulation layer CVD2, and an organic encapsulation layer IJP. The second inorganic encapsulation layer CVD2 is located on the side of the first inorganic encapsulation layer CVD1 away from the substrate SUB; the organic encapsulation layer IJP is located between the first inorganic encapsulation layer CVD1 and the second inorganic encapsulation layer CVD2.

[0175] In this embodiment, the configuration of the touch insulating layer TLD and the touch signal line TL refers to the description in the above embodiment. Figure 2 and Figure 7 As shown in , the touch electrode pattern includes touch drive electrodes TX and touch sensing electrodes RX, and the touch drive electrodes TX and the touch sensing electrodes RX are arranged crosswise, and the intersection of the touch drive electrodes TX and the touch sensing electrodes RX is separated by the touch insulation layer TLD. The touch drive electrode TX and the touch sensing electrode RX are both electrically connected to a touch signal line TL. The touch signal line TL includes a first transmission part TL1 and a second transmission part TL2, the first transmission part TL1 is located between the touch insulation layer TLD and the encapsulation layer EPL, the second transmission part TL2 is located on the side of the touch insulation layer TLD away from the substrate SUB, and the second transmission part TL2 is electrically connected to the first transmission part TL1 through a via penetrating the touch insulation layer TLD. The touch electrode pattern and the touch signal line TL are both located on the side of the encapsulation layer EPL away from the substrate SUB.

[0176] There is a gap between the first side surface LS and the single-sided blocking structure, for example, there is a gap between the end of the first side surface LS close to the substrate SUB and the end of the first side surface LS far from the substrate SUB and the single-sided blocking structure. A groove is formed between the organic insulating structure 20 and the single-sided blocking structure, and the orthographic projection of the encapsulation layer EPL on the substrate SUB simultaneously covers the orthographic projection of the organic insulating structure 20 on the substrate SUB, the orthographic projection of the groove on the substrate SUB, and the orthographic projection of the single-sided blocking structure on the substrate SUB, and the single-sided blocking structure is located between the substrate SUB and the encapsulation layer EPL.

[0177] The display area DA includes a plurality of pixel units, each of which is provided with a light-emitting element 50. The display panel 100 also includes a second power line VSS, which is electrically connected to the light-emitting element 50. The second power line VSS is located between the organic insulating structure 20 and the substrate SUB, and the orthographic projection of the first side surface LS on the substrate SUB overlaps with the orthographic projection of the second power line VSS on the substrate SUB.

[0178] The barrier 10 includes a first barrier 11 and a second barrier 12. The first barrier 11 is located in the peripheral area PA and surrounds the display area DA. The second barrier 12 is located in the peripheral area PA and surrounds the first barrier 11. The specific structures of the first barrier 11 and the second barrier 12 refer to the description in the above embodiment, which will not be repeated here. The substrate SUB is also provided with a first buffer layer BFL1, a semiconductor layer, a first gate insulating layer GI1, a first gate electrode layer G1, a second gate insulating layer GI2, an interlayer insulating layer ILD, a first source-drain conductive layer SD1, a passivation layer PVX, a second source-drain conductive layer SD2 and other structures. The structure and position of each film layer refer to the description in the above embodiment, which will not be repeated here. The substrate SUB in this embodiment is a flexible substrate, which also includes a bending area BA between the peripheral area PA and the pad area WA. In addition, it also includes other areas such as a test area DTA and a control circuit area CCA. The positional relationship between the areas refers to the description in the above embodiment, which will not be repeated here.

[0179] In the display panel of this embodiment, the first side surface of the organic insulating structure 20 is a slope surface with a small slope. Therefore, when the touch signal lines are subsequently made through an etching process, the conductive residue can be reduced, thereby reducing or preventing short circuits between the touch signal lines TL.

[0180] The embodiment of the present disclosure also provides a display panel, comprising a substrate, a barrier, an organic insulating structure, a touch electrode pattern and a touch signal line. The substrate comprises: a display area, a peripheral area and a pad area, wherein the peripheral area surrounds the display area, and the pad area is located on a side of the peripheral area away from the display area. The barrier is arranged on the substrate, the barrier is located in the peripheral area and surrounds the display area, and the barrier comprises a single-sided blocking structure located between the display area and the pad area. The organic insulating structure is arranged on the substrate, and the organic insulating structure comprises a plurality of stacked sub-insulating structures, a portion of each of the sub-insulating structures is located in the display area, and another portion is located in the peripheral area. Each of the sub-insulating structures has a first boundary located between the display area and the single-sided blocking structure, and except for the sub-insulating structure farthest from the substrate SUB, each of the remaining sub-insulating structures comprises a protruding portion, wherein for any two adjacent sub-insulating structures, the protruding portion of the sub-insulating structure close to the substrate SUB is located between the first boundary of the sub-insulating structure far from the substrate SUB and the single-sided blocking structure. The touch electrode pattern is arranged on a side of the organic insulating structure away from the substrate and is located in the display area. The touch signal line is arranged on a side of the organic insulating structure away from the substrate, one end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area, and the orthographic projection of the part of the touch signal line in the peripheral area on the substrate overlaps with the orthographic projection of the protruding part of each sub-insulating structure on the substrate.

[0181] The sub-insulating structure having the protruding portion is formed by patterning the organic material layer using a two-tone mask, wherein during the patterning process, the region where the protruding portion is to be formed corresponds to a semi-transparent region of the two-tone mask.

[0182] In some embodiments, the plurality of sub-insulating structures of the organic insulating structure include: a first planarization layer, a second planarization layer and a pixel defining layer. The first planarization layer is disposed on the substrate; the second planarization layer is located on a side of the first planarization layer away from the substrate; and the pixel defining layer is located on a side of the second planarization layer away from the substrate.

[0183] Figure 12 to Figure 14 A schematic diagram of a manufacturing process of a sub-insulating structure with an extension portion provided in some embodiments of the present disclosure is provided. The manufacturing process is introduced below by taking a sub-insulating structure with an extension portion as an example. The sub-insulating structure may be a first planarization layer or a second planarization layer.

[0184] like Fig.12As shown, an organic insulating material layer 210 is formed, wherein the organic insulating material layer 210 is a light-sensitive organic material layer, such as a positive photoresist.

[0185] like Fig.13 As shown, a two-tone mask M is used to expose the photoresist layer. The two-tone mask M is a gray tone mask or a half-tone mask. The two-tone mask M includes a fully transparent area M1, an opaque area M3 and a semi-transparent area M2, and the transmittance of the semi-transparent area M2 is less than the transmittance of the fully transparent area M1. Taking the organic insulating material layer 210 as a positive photoresist as an example, when exposing, the semi-transparent area M2 of the two-tone mask M corresponds to the area where the extension is to be formed, the fully transparent area M1 of the two-tone mask M corresponds to the area where the organic insulating material layer 210 needs to be completely removed, and the opaque area M3 of the two-tone mask M corresponds to other areas. After exposure, the portion of the organic insulating material layer 210 corresponding to the opaque area is not exposed, the portion of the organic insulating material layer 210 corresponding to the fully transparent area is fully exposed, and the portion of the organic insulating material layer 210 corresponding to the semi-transparent area is partially exposed.

[0186] Afterwards, the organic insulating material layer 210 is developed so that the portion of the organic insulating material layer 210 corresponding to the fully transparent area M1 is completely removed, the portion corresponding to the partially transparent area M2 is partially removed, and the portion corresponding to the opaque area M3 is completely retained. The formed pattern is the sub-insulating structure 21. Fig.14 The portion of the sub-insulating structure 21 corresponding to the partial light-transmitting area M2 is the protruding portion 21a, and the surface of the protruding portion 21a is a gentle slope surface.

[0187] It should be understood that in the above-mentioned patterning process, a negative photoresist may also be used. In this case, the pattern of the mask used is complementary to the pattern of the two-tone mask M mentioned above.

[0188] In the disclosed embodiment, the sub-insulating structure 21 having the protruding portion 21a is manufactured by patterning the organic material layer 210 using a two-tone mask. During exposure, the region where the protruding portion 21a is to be formed corresponds to the semi-transparent region M2 of the two-tone mask M, so that the formed protruding portion 21a can have a sloped surface. Therefore, the overall side surface of the organic insulating structure 20 is relatively flat. When the touch signal line is subsequently manufactured through an etching process, the residue of the conductive material can be reduced, thereby reducing or preventing short circuits between the touch signal lines.

[0189] In this embodiment, the structure of the barrier 20, the structure and material of the pixel defining layer PDL, the structure and material of the first planarization layer PLN1, and the structure and material of the second planarization layer PLN2 can all refer to the description in the above embodiments and will not be repeated here.

[0190] In addition, in this embodiment, an encapsulation layer and a touch insulating layer are further provided on the organic insulating structure. A light-emitting element may also be provided in the display area of ​​the substrate, and the light-emitting element is connected to the second power line. The specific structure and material of the encapsulation layer, the setting method and material of the touch insulating layer, the structure and material of the light-emitting element, and the setting method of the second power line and the touch signal line can all refer to the description in the above embodiment, and will not be repeated here.

[0191] The present disclosure also provides a display device, which includes the display panel of any of the above embodiments. The display device can be any product or component with a display function, such as an OLED panel, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0192] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and substance of the present disclosure, and these modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. A display panel, comprising: A substrate, comprising a display area, a peripheral area and a pad area, wherein the peripheral area surrounds the display area, and the pad area is located at a side of the peripheral area away from the display area; at least one barrier disposed on the substrate, the barrier being located in the peripheral area and surrounding the display area, the barrier comprising a single-sided barrier structure located between the display area and the pad area; an organic insulating structure disposed on the substrate, the organic insulating structure comprising a plurality of sub-insulating structures stacked, a portion of each of the plurality of sub-insulating structures being located in the display area, each of the plurality of sub-insulating structures having a first boundary located between the display area and the single-sided blocking structure, wherein for any two adjacent sub-insulating structures, the first boundary of the sub-insulating structure away from the substrate side is closer to the display area than the first boundary of the sub-insulating structure close to the substrate side; A touch electrode pattern is arranged on a side of the organic insulating structure away from the substrate; A touch signal line is arranged on a side of the organic insulating structure away from the substrate, one end of the touch signal line is electrically connected to the touch electrode pattern, and the other end is connected to the pad area, and the orthographic projection of the part of the touch signal line in the peripheral area on the substrate intersects with the first boundary of each of the sub-insulating structures; The distance between the first boundaries of any two adjacent sub-insulating structures is greater than or equal to 20 μm; The organic insulating structure has a bottom surface facing the substrate, a top surface opposite to the bottom surface, and a first side surface connected between the bottom surface and the top surface and facing the single-sided blocking structure, wherein the first side surface is a slope surface, and the slope angle of the slope surface is between 0° and 40°; The orthographic projection of the portion of the touch signal line in the peripheral area on the substrate passes through the orthographic projection of the slope surface on the substrate.

2. The display panel according to claim 1, wherein: The distance between the first boundaries of any two adjacent sub-insulation structures is between 25 μm and 60 μm, and the slope angle of the slope surface is between 25° and 35°.

3. The display panel according to any one of claims 1 to 2, wherein: The plurality of sub-insulating structures of the organic insulating structure include: A first planarization layer is disposed on the substrate; A second planarization layer, located on a side of the first planarization layer away from the substrate; The pixel defining layer is located on a side of the second planarization layer away from the substrate.

4. The display panel according to any one of claims 1 to 2, wherein: A gap is formed between the first boundary of the sub-insulation structure and the single-sided blocking structure.

5. The display panel according to any one of claims 1 to 2, wherein: The display panel further comprises: an encapsulation layer, which is arranged on a side of the organic insulating structure away from the substrate; Wherein, the touch electrode pattern and the touch signal line are both located on a side of the packaging layer away from the substrate.

6. The display panel according to claim 5, wherein: A groove is formed between the organic insulating structure and the single-sided blocking structure, the orthographic projection of the encapsulation layer on the substrate simultaneously covers the orthographic projection of the organic insulating structure on the substrate, the orthographic projection of the groove on the substrate and the orthographic projection of the single-sided blocking structure on the substrate, and the single-sided blocking structure is located between the substrate and the encapsulation layer.

7. The display panel according to claim 5, wherein: The display panel further includes: a touch insulating layer, which is arranged on a side of the encapsulation layer away from the substrate; The touch electrode pattern includes a plurality of touch driving electrodes and a plurality of touch sensing electrodes, the touch driving electrodes are cross-arranged with the touch sensing electrodes, the intersections of the touch driving electrodes and the touch sensing electrodes are insulated and separated by the touch insulating layer, and each of the touch driving electrodes and each of the touch sensing electrodes is correspondingly connected to one of the touch signal lines.

8. The display panel according to claim 7, wherein: The touch driving electrode comprises: a plurality of driving electrode units arranged along a first direction, and a connecting portion connected between every two adjacent driving electrode units; The touch sensing electrode comprises: a plurality of sensing electrode units arranged along the second direction, and a bridge portion connected between every two adjacent sensing electrode units; The first direction intersects with the second direction, the driving electrode unit, the connecting portion and the sensing electrode unit are all located on a side of the touch insulating layer away from the substrate and on the same layer, and the bridging portion is located between the touch insulating layer and the packaging layer.

9. The display panel according to claim 7, wherein: The touch signal line includes a first transmission part and a second transmission part, the first transmission part is located between the touch insulation layer and the packaging layer, the second transmission part is located on a side of the touch insulation layer away from the packaging layer, and the second transmission part is electrically connected to the first transmission part through a via hole penetrating the touch insulation layer.

10. The display panel according to any one of claims 1 to 2, wherein: The display area includes a plurality of pixel units, each of which is provided with a light-emitting element. The display panel also includes a power line, which is electrically connected to the light-emitting element. The power line is located between the organic insulating structure and the substrate, and an orthographic projection of the power line on the substrate overlaps with an orthographic projection of the first boundary on the substrate.

11. The display panel according to any one of claims 1 to 2, wherein: The obstacles include: A first barrier is located in the peripheral area and surrounds the display area; A second barrier located in the peripheral area and surrounding the first barrier; Wherein, a portion of the first barrier located between the display area and the pad area and a portion of the second barrier located between the display area and the pad area constitute the single-sided barrier structure.

12. The display panel according to claim 3, wherein: The display panel further includes: A first buffer layer is disposed on the substrate; A semiconductor layer, disposed between the first buffer layer and the first planarization layer; a first gate insulating layer, disposed between the semiconductor layer and the first planarization layer; a first gate electrode layer, disposed between the first gate insulating layer and the first planarization layer; a second gate insulating layer, disposed between the first gate electrode layer and the first planarization layer; a second gate electrode layer, disposed between the second gate insulating layer and the first planarization layer; an interlayer insulating layer, disposed between the second gate electrode layer and the first planarization layer; A first source-drain conductive layer, disposed between the interlayer insulating layer and the first planarization layer; A passivation layer, disposed between the first source-drain conductive layer and the first planarization layer; A second source-drain conductive layer, disposed between the first planarization layer and the second planarization layer; A first electrode layer is disposed between the second planarization layer and the pixel definition layer, the first electrode layer includes a plurality of first electrodes, and the pixel definition layer includes pixel openings corresponding to the first electrodes one by one; A light emitting layer is disposed in the pixel opening; A second electrode layer is arranged on a side of the light-emitting layer away from the substrate; An encapsulation layer is arranged on a side of the light-emitting layer away from the substrate; The second buffer layer is arranged on a side of the packaging layer away from the substrate.

13. A display device comprising the display panel according to any one of claims 1 to 12.

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