A trench gate structure device and its manufacturing method

Abstract

This invention provides a trench structure device and its fabrication method. The device includes: a substrate having a first conductivity and having a first main surface and a second main surface disposed opposite to each other; a drift region formed on the first main surface of the substrate, the drift region having the first conductivity and the carrier concentration of the drift region being lower than that of the substrate; a well region formed on the drift region, the well region having a second conductivity opposite to the first conductivity; a trench gate extending through the well region to the drift region, the trench gate having outwardly widened notch shapes at both bottom corners, the inner angle of the notch shape being less than 90°; a heavily doped region formed in the well region and located at the side edge of the trench gate, the heavily doped region having the first conductivity; an electrode disposed on the heavily doped region, the electrode contacting the heavily doped region and extending at least partially within the well region. This invention has a simple process and can provide better VDMOS and IGBT breakdown voltages while also considering on-state resistance and oxide reliability.

Description

Technical Field

[0001] This invention relates to a semiconductor device and a method for fabricating the same, and more particularly to a trench gate structure device and a method for fabricating the same. Background Technology

[0002] Trench gate structure is a common functional structure in MOSFETs and IGBTs. VDMOS based on trench gate structure, such as... Figure 1 As shown, the MOSFET includes a drift region 200 located on an n+ substrate 100, wherein the drift region 200 is an n-epitaxial layer. A p-well 300 is disposed on the drift region 200, and a heavily doped n+ region 500 is disposed within the p-well 300. The power MOSFET also includes a gate material 401 located on the drift region 200, and a gate dielectric layer 402 is disposed between the gate 401 and the p-well 300. A source electrode 600 is disposed on the p-well 300, and a back gold electrode 700 is disposed on the other side of the substrate as a drain electrode.

[0003] The development of trench gate structures has evolved from right-angled bottom structures to bottom-rounded structures and bottom-thick oxide structures. In traditional trench formation processes, the oxide on the (110) crystal plane of the trench sidewall is thicker than that on the bottom (100) crystal plane. For smaller trench bottom widths, the growth of thermal oxides is limited due to stress and the restriction of oxygen diffusion into the corner interface between the insulator and the sidewall substrate, resulting in weaknesses at the corners of the trench bottom. For larger trench bottom widths, the oxide layer is thinner than that on the sidewall because the oxidation rate of the (100) crystal plane at the bottom of the trench is slower, while the oxide thickness at the bottom corner is the same as that on the sidewall.

[0004] Studies have shown that improving the oxidation rate by ion etching at the bottom of the trench—specifically, by implanting Ar, As, P, and O ions at a certain angle at the bottom of the trench—can increase the oxidation rate of Si at the trench bottom. Double sacrificial oxide layers can smooth the right angles at the trench bottom, resulting in a more uniform oxidation rate. While double sacrificial oxide layers inhibit the thinning of the bottom oxide layer, this is still insufficient at corners for gates with a width <0.5µm. Therefore, combining these two methods—using double sacrificial oxide layers during the trench etching process to round the trench bottom—can simultaneously achieve a rounded, thick oxide layer at the bottom of the gate.

[0005] For conventional power MOSFETs and IGBTs, the on-state resistance Ron (saturation voltage Vsat) of the gate structure is positively correlated with the breakdown voltage (BV). However, the split-gate trench structure, developed from the trench gate structure, can better balance Ron (Vsat) and BV. Furthermore, superjunction technology can further increase BV and simultaneously reduce Ron through a more complex process of transforming the p-drift region into an n-drift region for charge compensation. These structures are complex, and their process routes are excessively lengthy. Therefore, for trench gate structures in power MOSFETs and IGBTs, achieving a simpler structure and process while effectively balancing parameters such as bottom oxide thickness, Ron (Vsat), and BV remains a major technical challenge for engineers. Summary of the Invention

[0006] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a trench gate structure device and its fabrication method, which solves the problem that it is difficult to simultaneously achieve the desired breakdown voltage, on-state resistance and oxide reliability of power devices in the prior art.

[0007] To achieve the above and other related objectives, the present invention provides a trench gate structure device, the trench structure device comprising at least:

[0008] A substrate having a first conductivity, the substrate having a first main surface and a second main surface disposed opposite to each other;

[0009] A drift region is formed on a first main surface of the substrate, the drift region has a first conductivity, and the carrier concentration of the drift region is lower than that of the substrate;

[0010] A well region is formed on the drift region, and the well region has a second conductivity that is opposite to the first conductivity.

[0011] A trench gate that extends through the well region to reach the drift region, wherein the bottom corners of the trench gate have outwardly widened notch shapes and the interior angles of the notch shapes are less than 90°;

[0012] A heavily doped region is formed in the well region and located at the side edge of the trench gate, the heavily doped region having a first conductivity;

[0013] An electrode is disposed on the heavily doped region, the electrode being in contact with the heavily doped region and extending at least partially into the well region.

[0014] Preferably, the substrate comprises one of silicon, silicon carbide, germanium, and gallium nitride.

[0015] Preferably, the electrode is made of metal.

[0016] The trench gate includes a trench, a gate dielectric layer located on the trench wall, and a gate material filled in the trench. The gate material includes at least one of polysilicon, metal, or metal silicide. The gate dielectric layer includes an insulating layer such as silicon dioxide or silicon nitride.

[0017] Preferably, a drain is also formed on the second main surface of the substrate to form a VDMOS device.

[0018] Preferably, the second main surface of the substrate is further formed with a collector region of second conductivity, and a collector electrode is further formed on the surface of the collector region to form an IGBT device.

[0019] Preferably, the interior angle of the notch shape is between 20 and 70°.

[0020] The present invention also provides a method for fabricating a trench gate structure device, comprising the following steps:

[0021] A substrate is provided, the substrate having a first conductivity, and the substrate having a first main surface and a second main surface disposed opposite to each other;

[0022] A drift region is formed on a first main surface of the substrate, the drift region having a first conductivity, and the carrier concentration of the drift region being lower than that of the substrate;

[0023] A well region is formed on the drift region, and the well region has a second conductivity that is opposite to the first conductivity.

[0024] A trench gate is formed that extends through the well region to the drift region, wherein the bottom corners of the trench gate have outwardly widened notch shapes and the inner angles of the notch shapes are less than 90°;

[0025] A heavily doped region is formed in the well region, located at the side edge of the trench gate, and the heavily doped region has a first conductivity.

[0026] An electrode is disposed on the heavily doped region, the electrode being in contact with the heavily doped region and extending at least partially within the well region.

[0027] Preferably, the method for fabricating the trench gate includes: firstly, performing anisotropic trench etching in the vertical direction until approaching the desired depth, and then performing isotropic etching at the bottom of the trench, wherein the isotropic etching simultaneously extends laterally to form an outwardly widened notch shape.

[0028] Preferably, the inner angle of the notch shape is adjusted by the isotropic etching rate, etching time, and etching temperature.

[0029] As described above, the trench gate structure device and its fabrication method of the present invention have the following beneficial effects: The novel trench gate structure with bottom corners for VDMOS and IGBTs of the present invention can achieve a better balance between Ron(Vsat), BV, and oxide thickness, providing better breakdown voltage for VDMOS and IGBTs while taking into account on-state resistance and oxide reliability. The trench gate structure for VDMOS and IGBTs does not require special trench bottom rounding, additional source (ground) connection, or complex epitaxial processes to form a superjunction structure, and the fabrication method is simple and easy to implement. This process and structure are applicable to all Si, SiC, and GaN-based power devices with trench gate structures. Attached Figure Description

[0030] Figure 1 The diagram shows a traditional trench gate structure.

[0031] Figure 2 The diagram shown is a schematic of a trench gate structure VDMOS device according to the present invention.

[0032] Figure 3 The diagram shows a TCAD electrical performance simulation of VDMOS with a right-angle trench gate structure, a rounded trench gate structure, and the gate structure of the present invention.

[0033] Figure 4 The diagram shown is a schematic of an IGBT device with a trench gate structure according to the present invention.

[0034] Component designation explanation

[0035] 100 substrate

[0036] 200 Drift Zone

[0037] 300 well area

[0038] 400 trench gate

[0039] 401 gate material

[0040] 402 Gate Dielectric Layer

[0041] 500 heavily doped region

[0042] 600 Source

[0043] 700 Drain

[0044] 800 collector area

[0045] 900 collector Detailed Implementation

[0046] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0047] In the detailed description of embodiments of the present invention, for ease of explanation, the cross-sectional views illustrating the device structure may be partially enlarged and not to scale. Furthermore, the schematic diagrams are merely examples and should not limit the scope of protection of the present invention. In actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0048] For ease of description, spatial relation terms such as “below,” “under,” “lower than,” “below,” “above,” and “upper” may be used herein to describe the relationship between one element or feature shown in the accompanying drawings and other elements or features. It will be understood that these spatial relation terms are intended to include directions other than those depicted in the drawings for devices in use or operation. Furthermore, when a layer is referred to as being “between” two layers, it may be the only layer between the two layers, or there may be one or more layers in between.

[0049] In the context of this application, the structure described above the first feature may include embodiments in which the first and second features are formed in direct contact, or embodiments in which additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0050] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape, formation method and size of the components in the actual implementation. In the actual implementation, the form, formation method, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0051] like Figure 2 As shown, this embodiment provides a VDMOS device based on a trench gate structure, comprising at least:

[0052] The substrate 100 has a first conductivity and has a first main surface and a second main surface disposed opposite to each other; the substrate 100 may be one of silicon, silicon carbide, germanium and gallium nitride.

[0053] A drift region 200 is formed on the first main surface of the substrate 100. The drift region 200 has a first conductivity and the carrier concentration of the drift region 200 is lower than that of the substrate.

[0054] A well region 300 is formed on the drift region 200, and the well region 300 has a second conductivity that is opposite to the first conductivity.

[0055] A trench gate 400 extends through the well region 300 to reach the drift region 200. The trench gate 400 has outwardly widening notches at its two bottom corners, with the inner angle of the notch shape being less than 90°, preferably between 20° and 70°. The trench gate 400 includes a trench, a gate dielectric layer 402 located on the trench wall, and a gate material 401 filling the trench. The gate material 401 can be at least one of polysilicon, metal, or metal silicide, and the gate dielectric layer 402 can be an insulating layer such as silicon dioxide or silicon nitride.

[0056] A heavily doped region 500 is formed in the well region 300 and located on the side edge of the trench gate 400. The heavily doped region 500 has a first conductivity. An electrode 600 is disposed on the heavily doped region. The electrode 600 is made of metal. The electrode 600 is in contact with the heavily doped region 500 and extends at least partially in the well region 300.

[0057] A drain electrode 700 is formed on the second main surface of the substrate 100.

[0058] like Figure 2 As shown, this embodiment also provides a method for fabricating a VDMOS device based on a trench gate structure, including the following steps:

[0059] A substrate 100 is provided, having a first conductivity, and the substrate has a first main surface and a second main surface disposed opposite to each other.

[0060] A drift region 200 is formed on the first main surface of the substrate 100. The drift region 200 has a first conductivity and the carrier concentration of the drift region 200 is lower than that of the substrate.

[0061] A well region 300 is formed on the drift region 200, and the well region 300 has a second conductivity that is opposite to the first conductivity.

[0062] A trench gate 400 is formed, extending through the well region 300 to the drift region 200. The trench gate 400 has outwardly widening notch shapes at its bottom corners, with the inner angle of the notch shape being less than 90°. Specifically, anisotropic trench etching can be performed first in the vertical direction until the desired depth is reached, followed by isotropic etching at the bottom of the trench, which simultaneously extends laterally to form the outwardly widening notch shape. The inner angle of the notch shape is adjusted by the isotropic etching rate, etching time, and etching temperature.

[0063] A heavily doped region 500 is formed in the well region 300, located on the side edge of the trench gate 400, and the heavily doped region 500 has a first conductivity.

[0064] An electrode 600 is disposed on the heavily doped region 500, the electrode 600 is in contact with the heavily doped region 500 and extends at least partially in the well region 300.

[0065] A drain 700 is formed on the second main surface of the substrate 100 to obtain a VDMOS device.

[0066] like Figure 3 As shown, TCAD electrical performance simulations were performed on VDMOS with right-angle trench gate structure, rounded trench gate structure, and gate structure of the present invention. Meanwhile, the table below provides comparative data on BV, Vsat, and maximum electric field strength for the trench gate bottom notch shape of the VDMOS with right-angle trench gate structure, rounded trench gate structure, and gate structure of the present invention at different internal angles.

[0067]

[0068] Depend on Figure 3 As can be seen from the data in the table above, the maximum electric field strength of the right-angle trench gate structure is at the sharp corner. The gate oxide layer of the circular trench is relatively thin, while the right-angle trench has a thicker BV, but the increase in Vsat is not significant. Data analysis shows that, compared with the previous two structures, the trench structure of this invention has a better BV and a smaller Vsat. Furthermore, as the inner angle (α) decreases, that is, as the width of the gate bottom increases, the BV gradually increases, while Vsat increases slightly.

[0069] Compared to factors such as plasma damage, implant type, and crystal surface orientation, rounded corners are not traditionally considered a major way to increase oxide thickness, and they do not significantly improve BV and Ron. Conversely, TCAD results show that the trench shape at the bottom corner can significantly improve BV. The thicker oxide at the inner corner improves oxide reliability; the enhanced electric field at the trench gate tip at the bottom corner reduces Ron.

[0070] On the surface, reducing the oxide thickness may lead to oxide reliability issues in the conductive state, but in reality, the oxide thickness can be controlled by the inner angle (α). That is, a smaller inner angle in the bottom corner structure may result in an oxide thickness greater than that of a rounded structure with a larger inner angle (>90°). Therefore, the notch at the bottom corner has a gain effect on the oxide thickness.

[0071] In the on-state, although the notch corner occupies part of the N-drift region, Ron may decrease slightly. However, the high electric field at the sharper polysilicon gate will induce more accumulated carriers in the drift region near the notch corner, and the final effect on Ron is minimal. In the off-state, firstly, the electric field in the depletion region is redistributed more uniformly, thereby increasing the breakdown voltage; secondly, the Si oxide in the bottom corner may be thicker than Si and more resistant to breakdown; in addition, since the electric field is only related to the ion dopants in the depletion layer, the sharper corner at the concave corner will not generate a larger electric field in the off-state. Therefore, the trench gate of the present invention increases the breakdown voltage in the off-state.

[0072] In summary, this invention effectively achieves a balance and optimization of device oxide thickness, Ron, and BV performance through a simple process structure design.

[0073] like Figure 4 As shown, this embodiment also provides an IGBT device based on a trench gate structure, comprising at least:

[0074] The substrate 100 has a first conductivity and has a first main surface and a second main surface disposed opposite to each other; the substrate 100 may be one of silicon, silicon carbide, germanium and gallium nitride.

[0075] A drift region 200 is formed on the first main surface of the substrate 100. The drift region 200 has a first conductivity and the carrier concentration of the drift region 200 is lower than that of the substrate.

[0076] A well region 300 is formed on the drift region 200, and the well region 300 has a second conductivity that is opposite to the first conductivity.

[0077] A trench gate 400 extends through the well region 300 to reach the drift region 200. The trench gate 400 has outwardly widening notches at its two bottom corners, with the inner angle of the notch shape being less than 90°, preferably between 20° and 70°. The trench gate 400 includes a trench, a gate dielectric layer 402 located on the trench wall, and a gate material 401 filling the trench. The gate material 401 can be at least one of polysilicon, metal, or metal silicide, and the gate dielectric layer 402 can be an insulating layer such as silicon dioxide or silicon nitride.

[0078] A heavily doped region 500 is formed in the well region 300 and located on the side edge of the trench gate 400. The heavily doped region 500 has a first conductivity. An electrode 600 is disposed on the heavily doped region. The electrode 600 is made of metal. The electrode 600 is in contact with the heavily doped region 500 and extends at least partially in the well region 300.

[0079] The second main surface of the substrate 100 also has a collector region 800 with second conductivity, and a collector electrode 900 is formed on the surface of the collector region 800.

[0080] like Figure 4 As shown, this embodiment also provides a method for fabricating an IGBT device based on a trench gate structure, including the following steps:

[0081] A substrate 100 is provided, having a first conductivity, and the substrate has a first main surface and a second main surface disposed opposite to each other.

[0082] A drift region 200 is formed on the first main surface of the substrate 100. The drift region 200 has a first conductivity and the carrier concentration of the drift region 200 is lower than that of the substrate.

[0083] A well region 300 is formed on the drift region 200, and the well region 300 has a second conductivity that is opposite to the first conductivity.

[0084] A trench gate 400 is formed, extending through the well region 300 to the drift region 200. The trench gate 400 has outwardly widening notch shapes at its bottom corners, with the inner angle of the notch shape being less than 90°. First, anisotropic trench etching is performed vertically until the desired depth is reached. Then, isotropic etching is performed at the bottom of the trench, simultaneously advancing laterally to form the outwardly widening notch shape. The inner angle of the notch shape is adjusted by the isotropic etching rate, etching time, and etching temperature.

[0085] A heavily doped region 500 is formed in the well region 300, located on the side edge of the trench gate 400, and the heavily doped region 500 has a first conductivity.

[0086] An electrode 600 is disposed on the heavily doped region 500, the electrode 600 is in contact with the heavily doped region 500 and extends at least partially in the well region 300.

[0087] A collector region 800 is formed on the second main surface of the substrate 100. The collector region 800 has a second conductivity opposite to the first conductivity. A collector electrode 900 is formed on the surface of the collector region 800 to obtain an IGBT device.

[0088] In summary, this invention provides a trench gate structure device and its fabrication method, applicable to VDMOS and IGBTs. The trench gate structure of this invention achieves a better balance between Ron(Vsat), BV, and oxide thickness, providing better breakdown voltage for VDMOS and IGBTs while also considering on-state resistance and oxide reliability. The trench gate structure for VDMOS and IGBTs does not require special trench bottom rounding, additional source (ground) connection, or complex epitaxial processes to form a superjunction structure; the fabrication method is simple and easy to implement. This process and structure are applicable to all trench gate structures in Si, SiC, and GaN-based power devices. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial applicability.

[0089] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A trench gate structure device, characterized in that, The trench gate structure device includes at least: A substrate having a first conductivity, the substrate having a first main surface and a second main surface disposed opposite to each other; A drift region is formed on a first main surface of the substrate, the drift region has a first conductivity, and the carrier concentration of the drift region is lower than that of the substrate; A well region is formed on the drift region, and the well region has a second conductivity that is opposite to the first conductivity. A trench gate extends through the well region to reach the drift region. The bottom corners of the trench gate have outwardly widened notch shapes. The connection between the notch shapes and the sidewalls of the trench gate has a corner. The interior angle of the notch shapes is between 20° and 70°. A heavily doped region is formed in the well region and located at the side edge of the trench gate, the heavily doped region having a first conductivity; An electrode is disposed on the heavily doped region, the electrode being in contact with the heavily doped region and extending at least partially into the well region.

2. The trench gate structure device according to claim 1, characterized in that: The substrate includes one of silicon, silicon carbide, germanium, and gallium nitride.

3. The trench gate structure device according to claim 1, characterized in that: The electrode is made of metal.

4. A trench gate structure device according to claim 1, characterized in that: The trench gate includes a trench, a gate dielectric layer located on the trench wall, and a gate material filled in the trench. The gate material includes at least one of polysilicon, metal, or metal silicide. The gate dielectric layer includes one of silicon dioxide and silicon nitride.

5. A trench gate structure device according to claim 1, characterized in that: The second main surface of the substrate also has a drain electrode formed to form a VDMOS device.

6. A trench gate structure device according to claim 1, characterized in that: The second main surface of the substrate also forms a collector region with second conductivity, and a collector electrode is formed on the surface of the collector region to form an IGBT device.

7. A method for fabricating a trench gate structure device, characterized in that, Including the following steps: A substrate is provided, the substrate having a first conductivity, and the substrate having a first main surface and a second main surface disposed opposite to each other; A drift region is formed on a first main surface of the substrate, the drift region having a first conductivity, and the carrier concentration of the drift region being lower than that of the substrate; A well region is formed on the drift region, and the well region has a second conductivity that is opposite to the first conductivity. A trench gate is formed that passes through the well region to reach the drift region. The bottom corners of the trench gate have outwardly widened notch shapes. The connection between the notch shape and the sidewall of the trench gate has a corner. The inner angle of the notch shape is between 20° and 70°. A heavily doped region is formed in the well region, the heavily doped region being located at the side edge of the trench gate, and the heavily doped region having a first conductivity; An electrode is disposed on the heavily doped region, the electrode being in contact with the heavily doped region and extending at least partially within the well region.

8. The method for fabricating a trench gate structure device according to claim 7, characterized in that: First, anisotropic trench etching is performed vertically until the desired depth is reached. Then, isotropic etching is performed at the bottom of the trench, which simultaneously extends laterally to form an outwardly widening notch shape.

9. The method for fabricating a trench gate structure device according to claim 8, characterized in that: The inner angle of the notch shape is adjusted by the isotropic etching rate, etching time, and etching temperature.

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