A maximum power point fast tracking control circuit suitable for boost converter circuit

Abstract

The present invention relates to the technical field of conversion circuits, and discloses a maximum power point fast tracking control circuit suitable for a boost conversion circuit, comprising: a timing generation module, a dynamic comparator module, a main logic module, an end register module and a power reference module, wherein the timing generation module comprises an S1 signal, an S2 signal, an S3 signal and a RESET signal, the dynamic comparator module comprises a comparator switch tube enable terminal, the dynamic comparator module comprises a dynamic comparator, the main logic module comprises a shift addition enable terminal, the main logic module comprises a shift adder, the power reference module signal is connected with an NMOS tube, the dynamic comparator comprises a VP terminal, a VN terminal, a P terminal and an N terminal, the P terminal generates a POUT signal, the N terminal generates an NOUT signal, and the POUT signal is connected to the main logic module. The present invention searches for the maximum power point by a binary method, thereby improving the search efficiency.

Description

Technical Field

[0001] The present invention relates to the technical field of conversion circuits, and in particular to a maximum power point fast tracking control circuit suitable for a boost conversion circuit. Background Art

[0002] Voltage conversion circuits are often used as bridges to connect low-voltage circuits and high-voltage circuits, especially in low-voltage core logic circuits and high-voltage I / O interface circuits to obtain higher drive currents. Boost converters are commonly used in various electronic products to increase the input voltage to the operating voltage required by the electronic products, so that the electronic products can operate normally.

[0003] Traditional maximum power point tracking circuits have disadvantages such as low tracking speed and accuracy, narrow tracking range, and high tracking power consumption. Researchers hope to improve the module's tracking speed, improve the module's efficiency, and reduce the module's power consumption while ensuring the circuit tracking accuracy. Summary of the invention

[0004] The purpose of the present invention is to provide a maximum power point fast tracking control circuit suitable for a boost converter circuit, which searches for the maximum power point by binary search and improves the search efficiency, so as to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A maximum power point fast tracking control circuit suitable for a boost conversion circuit comprises: a timing generation module, a dynamic comparator module, a shift addition module, an end register module and a power reference module, wherein the timing generation module comprises an S1 signal, an S2 signal, an S3 signal and a RESET signal, the dynamic comparator module comprises a comparator switch tube enable terminal, the dynamic comparator module comprises a dynamic comparator, the main logic module comprises a shift addition enable terminal, the main logic module comprises a shift adder, the power reference module signal is connected to an NMOS tube, the power reference module signal is connected to a capacitor, and the end register module comprises an end register.

[0007] Preferably, the number of the NMOS tubes is three, and the number of the capacitors is two.

[0008] Preferably, the dynamic comparator includes a P terminal and an N terminal, the P terminal generates a POUT signal, the N terminal generates a NOUT signal, the POUT signal is connected to the main logic module, and the NOUT signal is connected to the main logic module.

[0009] Preferably, the S1 signal is connected to a power reference module, the S2 signal is connected to a power reference module, and the S3 signal is connected to a power reference module.

[0010] Preferably, the RESET signal is connected to a power reference module, the RESET signal is connected to a comparator switch tube enable terminal, and the RESET signal is connected to a shift addition enable terminal.

[0011] Preferably, the four-bit binary output terminal of the shift-add module is connected to the input terminal of the terminal register.

[0012] Compared with the prior art, the maximum power point fast tracking control circuit applicable to the boost conversion circuit provided by the present invention has the following beneficial effects:

[0013] 1. The maximum power point fast tracking control circuit suitable for the boost conversion circuit searches for the maximum power point by binary division, thereby improving the search efficiency.

[0014] 2. The maximum power point fast tracking control circuit suitable for the boost conversion circuit effectively reduces the power consumption of the circuit under non-continuous call by dynamically enabling the circuit.

[0015] 3. The maximum power point fast tracking control circuit suitable for the boost conversion circuit adopts digital methods for the main logic modules. By expanding the timing generation module, the shift addition module and the register module, the search range and search accuracy can be expanded. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor:

[0017] Figure 1 Schematic diagram of the circuit principle of the control circuit of an embodiment of the present invention;

[0018] Figure 2 This is a schematic diagram of the maximum power point fast tracking control according to an embodiment of the present invention;

[0019] Figure 3 The schematic diagram of the timing generation module circuit of the embodiment of the present invention;

[0020] Figure 4 This is a circuit schematic diagram of a shift addition module according to an embodiment of the present invention;

[0021] Figure 5 This is a schematic diagram of the terminal register circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0022] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0024] Example:

[0025] See also Figure 1-5 The maximum power point fast tracking control circuit for a boost conversion circuit provided by the present invention comprises: a timing generation module, a dynamic comparator module, a shift addition module, an end register module and a power reference module, the timing generation module comprises an S1 signal, an S2 signal, an S3 signal and a RESET signal, the dynamic comparator module comprises a comparator switch tube enable terminal, the dynamic comparator module comprises a dynamic comparator, the main logic module comprises a shift addition enable terminal, the main logic module comprises a shift adder, the power reference module signal is connected with an NMOS tube, the power reference module signal is connected with a capacitor, the end register module comprises an end register, There are three NMOS tubes and two capacitors. The dynamic comparator includes a P terminal and an N terminal. The P terminal generates a POUT signal and the N terminal generates a NOUT signal. The POUT signal is connected to the main logic module and the NOUT signal is connected to the main logic module. The S1 signal is connected to the power reference module and the S2 signal is connected to the power reference module and the S3 signal is connected to the power reference module and the RESET signal is connected to the power reference module. The RESET signal is connected to the comparator switch enable terminal and the RESET signal is connected to the shift addition enable terminal. The four-bit binary output terminal of the shift addition module is connected to the input terminal of the terminal register.

[0026] In actual operation, when this device is used, the maximum power point tracking circuit compares the internal resistance of the input power supply with the circuit input impedance. This process is equivalent to comparing half of the power supply short-circuit voltage with the input voltage. The specific comparison process is as follows:

[0027] Before starting the comparison, the timing generation module generates a reset signal to reset the high-order register REGH and the low-order register REGL in the logic module, and output the binary values ​​of "all 1" and "all 0" respectively. Taking a four-bit register as an example, at this time, the calculation process of the logic module is:

[0028] REGOUT=(((1111)2+(0000)2)>>1)+C in

[0029] =((1111)2>>1)+1=((0111)2+1)=(1000)2=(8) 10

[0030] The shift-add module outputs the calculation result to the terminal register module. Since the register is not enabled during the calculation process, the data selector directly outputs the shift-add module.

[0031] The timing module generates S1, S2, and S3 control signals respectively, which control the on and off of the NMOS switch tubes N1, N2, and N3 in the power reference module respectively. When the S1 signal is at a high level, N1 is turned on, and N2 and N3 are turned off. At this time, VDDI charges the capacitor C1; when the S2 signal is at a high level, N2 is turned on, and N1 and N3 are turned off. At this time, the capacitor C1 is discharged and the capacitor C2 is charged; when the S3 signal is at a high level, N3 is turned on, and N1 and N2 are turned off. At this time, C2 is discharged, and the voltage at the VN terminal is half the power supply voltage.

[0032] The clock signal CMPCLK generated by the timing module triggers the comparator to compare half the power supply voltage with the input voltage and output the comparison results POUT and NOUT.

[0033] The comparison results of POUT and NOUT will activate the high register REGH and the low register REGL respectively to store the output result of the shift adder. If the input voltage is greater than half of the power supply short-circuit voltage, the comparator outputs the NOUT signal. The calculation process of the logic module is:

[0034] REGH=REGOUT

[0035]

[0036] Since the shift operation in the digital module will discard the lowest bit, the division rule in the above formula is to round down, resulting in the search range being limited to 0 to 2 n -1, in order to make the search interval contain the binary value of "all 1", the carry bit C of the adder needs to be in Set to 1.

[0037] Repeat the above operation and adjust the binary signal of the control output according to the comparison result. Figure 1 As shown, the comparison range will be gradually reduced, because the circuit impedance of the boost converter circuit can be derived from the following relationship:

[0038] R=8Lf

[0039] When the comparison process is over, the two voltages at the comparator input terminals are close to each other, and the output signal of the logic module will control the oscillator output frequency, so that the input impedance of the circuit is close to the internal resistance of the power supply. At this time, the maximum input power is achieved. At the same time, the timing generation module will output the register enable signal LATCH_EN, so that the register module stores the calculation results and dynamically turns off the comparator module and the shift addition module. Taking the N-bit logic module as an example, the clock cycle required for the entire comparison process is N-1.

[0040] The above embodiments of the present invention focus on finding the maximum power point by binary division, thereby improving the search efficiency.

[0041] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0042] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A maximum power point fast tracking control circuit suitable for a boost converter circuit, comprising: A timing generation module, a dynamic comparator module, a shift addition module, an end register module and a power reference module, characterized in that: the timing generation module includes an S1 signal, an S2 signal, an S3 signal, a RESET signal and a LATCH_EN enable signal, the dynamic comparator module includes a comparator switch tube enable terminal, the dynamic comparator module includes a dynamic comparator, the main logic module includes a shift addition enable terminal, the main logic module includes a shift adder, the power reference module signal is connected to an NMOS tube, the power reference module signal is connected to a capacitor, and the end register module includes an end register; The timing generation module is respectively connected to the power reference module, the dynamic comparator module and the terminal register module, and its S1 signal, S2 signal and S3 signal are input to the power reference module, and its RESET signal is connected to the input end of the shift addition module. The input end of the dynamic comparator module is respectively connected to the power reference module and the timing generation module, and its output end is connected to the input end of the shift addition module, and the output end of the shift addition module is connected to the input end of the terminal register module. At the same time, the power reference module includes three NMOS tubes, the source of the P1 NMOS tube is connected to the VDDI signal, the drain of the P1 NMOS tube is connected to the source of the P2NMOS tube, the drain of the P2 NMOS tube is connected to the source of the P3 NMOS tube, and the drain of the P3 NMOS tube is grounded. One end of the capacitor C1 is connected to the drain of the P1 NMOS tube and the source of the P2 NMOS tube, and the other end is grounded; one end of the capacitor C2 is connected to the drain of the P2 NMOS tube and the source of the P3 NMOS tube, and the other end is grounded.

2. The maximum power point fast tracking control circuit suitable for a boost converter circuit according to claim 1, characterized in that: The number of the NMOS tubes is three, and the number of the capacitors is two.

3. The maximum power point fast tracking control circuit suitable for a boost converter circuit according to claim 1, characterized in that: The dynamic comparator includes a P terminal and an N terminal, the P terminal generates a POUT signal, the N terminal generates a NOUT signal, the POUT signal is connected to the main logic module, and the NOUT signal is connected to the main logic module.

4. The maximum power point fast tracking control circuit suitable for a boost converter circuit according to claim 1, characterized in that: The LATCH_EN enable signal is connected to a shift addition enable terminal.

5. The maximum power point fast tracking control circuit suitable for a boost converter circuit according to claim 1, characterized in that: The four-bit binary output end of the shift-add module is connected to the input end of the terminal register.

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