Verification method, verification device, equipment and storage medium for processor

Abstract

This disclosure provides a verification method, verification apparatus, device, and storage medium for processors. The method includes: during regression verification of a processor, acquiring a first stimulus to be verified corresponding to a target instruction set of the processor, wherein the first stimulus includes one or more instructions to be verified; based on the one or more instructions to be verified of the first stimulus, acquiring the current functional coverage including the first stimulus by operating a first database, wherein the first database stores a set of comparison data for verifying functional coverage. This disclosure, by using a database, enables the collection of functional coverage corresponding to instructions gathered during regression verification of the processor, thereby achieving a more comprehensive and clear functional coverage analysis oriented towards the instruction set. It is suitable for processor verification corresponding to instruction sets with high complexity, and achieves rapid convergence and more complete verification work with limited cost.

Description

Technical Field

[0001] Embodiments of this disclosure relate to a verification method, verification apparatus, device, and storage medium for a processor. Background Technology

[0002] With the continuous development of science and technology, people's demand for processors is also constantly increasing. Commonly used processors include: Central Processing Unit (CPU), General-Purpose Graphics Processor (GPGPU), Digital Signal Processor (DSP), and Application-Specific Integrated Circuit (ASIC). These processors must undergo verification before being put into use to ensure they function correctly and are free from damage.

[0003] When verifying a designed processor, it is necessary to determine whether the processor functions correctly and whether there are any design or manufacturing defects. For example, when verifying a processor using test programs, the coverage of processor functionality verification may be low, resulting in a lack of completeness in the functional coverage.

[0004] Currently, software demands increasingly higher computational power from processors, and the scale and complexity of processors are constantly increasing. Consequently, processor verification is becoming more difficult and time-consuming. In the processor design process, verification work accounts for more than half of the entire R&D cycle, making verification efficiency and quality crucial factors in processor design. Summary of the Invention

[0005] At least one embodiment of this disclosure provides a verification method for a processor, comprising: during regression verification of the processor, obtaining a first stimulus to be verified corresponding to a target instruction set of the processor, wherein the first stimulus includes one or more instructions to be verified; and based on the one or more instructions to be verified of the first stimulus, obtaining a current functional coverage including the first stimulus by operating a first database, wherein the first database stores a set of comparison data for verifying the functional coverage.

[0006] For example, at least one embodiment of this disclosure provides a verification method that further includes: in response to each of the one or more instructions to be verified in the first stimulus being machine code, receiving the machine code through an assembler and processing it to form disassembly instructions in text format to obtain a disassembly instruction set corresponding to the first stimulus; wherein, based on the one or more instructions to be verified in the first stimulus, obtaining the current functional coverage including the first stimulus by operating a first database includes: based on the disassembly instruction set corresponding to the first stimulus, obtaining the current functional coverage including the first stimulus by operating a first database.

[0007] For example, in a verification method provided in at least one embodiment of this disclosure, based on the disassembly instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating a first database, including: based on the disassembly instruction set corresponding to the first stimulus, obtaining intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus; collecting the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus to obtain a covered data set; operating the first database to compare the covered data set with the comparison data set to obtain the current functional coverage including the first stimulus.

[0008] For example, in a verification method provided in at least one embodiment of this disclosure, intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus is included to obtain a covered data set, including: including intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus in the first database, so that the first database includes the covered data set.

[0009] For example, in a verification method provided in at least one embodiment of this disclosure, operating the first database and comparing the covered data set with the comparison data set to obtain the current functional coverage including the first stimulus includes: using operation instructions of a database operation language for the first database encapsulated by a first programming language to operate the first database to obtain the current functional coverage including the first stimulus; and recording the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus to obtain the covered data set includes: using operation instructions of a database operation language for the first database encapsulated by a first programming language to make the first database include the covered data set.

[0010] For example, in a verification method provided in at least one embodiment of this disclosure, based on the disassembly instruction set corresponding to the first stimulus, intermediate data to be verified is obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, including: preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus to obtain at least one field of each disassembly instruction in the disassembly instruction set, so as to obtain intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus.

[0011] For example, in a verification method provided in at least one embodiment of this disclosure, the at least one field segment includes an opcode; or, the at least one field segment includes an opcode and at least one of a prefix, a modifier, and an operand.

[0012] For example, in a verification method provided in at least one embodiment of this disclosure, intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is recorded in the first database, so that the first database records the covered data set, including: checking the intermediate data to be recorded in the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, so that the intermediate data corresponding to the disassembly instruction conforms to the general format of the first database and that the intermediate data corresponding to the disassembly instruction includes information of each field segment in at least one field segment corresponding to the disassembly instruction.

[0013] For example, in a verification method provided in at least one embodiment of this disclosure, checking the intermediate data to be entered into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus includes: obtaining the original string based on the instruction code format of the disassembly instruction; obtaining the intermediate format of the intermediate data, wherein the intermediate format is consistent with the general format of the first database; restoring the intermediate data from the intermediate format according to the instruction code format to obtain the restored string corresponding to the disassembly instruction; in response to the restored string of the disassembly instruction being consistent with the corresponding original string, determining that the intermediate data of the disassembly instruction corresponds one-to-one with each field segment in at least one field segment of the corresponding disassembly instruction, thereby determining that the check of the first database including the disassembly instruction has passed.

[0014] For example, in a verification method provided in at least one embodiment of this disclosure, intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is recorded in the first database, so that the first database records the covered data set, including: deduplicating the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus recorded in the first database, so that the disassembly instruction corresponding to the intermediate data in the covered data set in the first database is unique.

[0015] For example, in a verification method provided in at least one embodiment of this disclosure, during a regression verification process for the processor, obtaining a first stimulus to be verified corresponding to the target instruction set of the processor includes: determining one or more test phases of the regression verification process based on the regression verification process for the processor; and obtaining a second stimulus corresponding to each current test phase based on each of the one or more test phases, wherein the second stimulus corresponding to each current test phase is the current first stimulus.

[0016] For example, at least one embodiment of this disclosure provides a verification method that further includes: for each current test stage among the plurality of test stages, based on the disassembly instruction set corresponding to the first stimulus, obtaining the current functional coverage including the first stimulus by operating the first database.

[0017] For example, in a verification method provided in at least one embodiment of this disclosure, for each current test stage among the plurality of test stages, based on the disassembly instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database, including: based on the disassembly instruction set corresponding to the first stimulus corresponding to the current test stage, obtaining intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus; deduplicating the intermediate data of the disassembly instruction set corresponding to the first stimulus corresponding to the current test stage to obtain a deduplicated data set; adding the deduplicated data set corresponding to the current test stage to the first database to obtain a corresponding covered data set; operating the first database to compare the covered data set with the comparison data set to obtain the current functional coverage including the first stimulus.

[0018] For example, a verification method provided in at least one embodiment of this disclosure further includes: for each current test stage among the plurality of test stages, in response to obtaining the current functional coverage including the first stimulus by operating the first database, transferring the deduplicated data set corresponding to the current first stimulus to the backup second database.

[0019] For example, in a verification method provided in at least one embodiment of this disclosure, the deduplication data set corresponding to the current first stimulus is transferred to the backup second database, including: for the current intermediate data in the deduplication data set corresponding to the first stimulus, in response to the disassembly instructions corresponding to the current intermediate data being different from the disassembly instructions corresponding to the intermediate data already stored in the second database, the intermediate data is stored in the second database for backup, so that the disassembly instructions corresponding to the intermediate data in the second database are unique.

[0020] For example, at least one embodiment of this disclosure provides a verification method that further includes: controlling the verification method according to a modular specification by using command-line parameters through top-level code; wherein the verification method is implemented by executing multiple independent functional modules: an update function module configured to obtain the updated current first stimulus through update parameters in response to the target instruction set update; a running module configured to obtain the current functional coverage including the first stimulus by operating the first database; a report acquisition module configured to obtain a functional coverage report; and a transfer module configured to store the deduplicated data set corresponding to the current first stimulus into a backed-up second database in response to the current first stimulus, and to clear the deduplicated data set corresponding to the current first stimulus already entered in the first database.

[0021] For example, at least one embodiment of this disclosure provides a verification method that further includes: in response to the current functional coverage including the first stimulus being not less than the target coverage, the regression verification of the processor is passed; in response to the current functional coverage including the first stimulus being less than the target coverage, the first stimulus is updated, and the updated first stimulus is used to update the functional coverage until the obtained functional coverage including the updated first stimulus is not less than the target coverage, and the regression verification of the processor is passed.

[0022] For example, at least one embodiment of this disclosure provides a verification method that further includes: classifying one or more instructions to be verified from the first stimulus to obtain multiple instruction sets; and based on the current functional coverage including the first stimulus, obtaining the relationship between the functional coverage of each instruction set in the multiple instruction sets and time, thereby obtaining a curve between the functional coverage of the multiple instruction sets and time.

[0023] For example, in a verification method provided in at least one embodiment of this disclosure, the disassembly instruction set corresponding to the first stimulus includes a very long instruction word.

[0024] At least one embodiment of this disclosure provides a verification apparatus for a processor, comprising: a stimulus acquisition module configured to acquire, during regression verification of the processor, a first stimulus to be verified corresponding to a target instruction set of the processor, wherein the first stimulus includes one or more instructions to be verified; and a functional coverage acquisition module configured to acquire, based on the one or more instructions to be verified of the first stimulus, a current functional coverage including the first stimulus by operating a first database, wherein the first database stores a set of comparison data for verifying the functional coverage.

[0025] For example, in a verification apparatus provided in at least one embodiment of this disclosure, each of the one or more instructions to be verified in the first stimulus is machine code, and the functional coverage acquisition module includes: an assembler configured to receive the machine code and process it to form disassembly instructions in text format to obtain a set of disassembly instructions corresponding to the first stimulus.

[0026] For example, in a verification apparatus provided in at least one embodiment of this disclosure, the functional coverage acquisition module further includes: a preprocessing module configured to acquire, based on the disassembly instruction set corresponding to the first stimulus, intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus; an inclusion processing module configured to include the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus, to obtain a covered data set; and a coverage acquisition module configured to compare the covered data set and the comparison data set by operating the first database to obtain the current functional coverage including the first stimulus.

[0027] For example, in a verification apparatus provided in at least one embodiment of this disclosure, the disassembly instruction set corresponding to the first stimulus includes a very long instruction word.

[0028] At least one embodiment of this disclosure provides an electronic device, including: a processor and a memory, wherein the memory stores a computer program, which, when executed by the processor, implements the verification method as described in any of the preceding embodiments.

[0029] At least one embodiment of this disclosure provides a computer-readable storage medium, wherein the storage medium stores a computer program that, when executed by a processor, implements the verification method as described in any of the above examples. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of a verification method for a processor proposed in some embodiments of this disclosure;

[0032] Figure 2 This is a flowchart of a verification method for a processor according to other embodiments of this disclosure;

[0033] Figure 3 yes Figure 2 A flowchart of an execution process for step S23 of the verification method used for the processor;

[0034] Figure 4 This diagram illustrates the performance optimization of psql operations provided in some embodiments of this disclosure.

[0035] Figure 5 This is a flowchart of the execution process of checking the intermediate data to be entered into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, provided by some embodiments of this disclosure;

[0036] Figure 6A A schematic diagram of the raw string of disassembled instructions provided for some embodiments of this disclosure;

[0037] Figure 6B Correspondence provided for some embodiments of this disclosure Figure 6A A diagram illustrating the restored string from the disassembled instructions;

[0038] Figure 7 for Figure 2 A flowchart of the execution process of step S21 of the verification method in the diagram;

[0039] Figure 8 A flowchart illustrating a verification method for a processor provided for some embodiments of this disclosure;

[0040] Figure 9 A flowchart of an execution process for step S31 of the verification method for a processor;

[0041] Figure 10 For the corresponding Figure 9 A schematic diagram illustrating the principle of the verification method;

[0042] Figure 11 This is a schematic diagram illustrating the script structure planning provided for some embodiments of this disclosure;

[0043] Figure 12 A schematic diagram illustrating the relationship between a set of instructions and time, provided for some embodiments of this disclosure;

[0044] Figure 13 A block diagram of a verification apparatus for a processor provided for some embodiments of this disclosure;

[0045] Figure 14 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. Detailed Implementation

[0046] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0047] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of this disclosure shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It should also be understood that terms such as those defined in a common dictionary shall be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and shall not be interpreted in an idealized or highly formalized sense, unless expressly defined in the embodiments of this disclosure.

[0048] The terms "first," "second," and similar words used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms "an," "one," or "the" do not indicate a quantity limitation, but rather indicate the presence of at least one. Likewise, the terms "including" or "comprising" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. The terms "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Flowcharts are used in this disclosure to illustrate the steps of the method according to embodiments of this disclosure. It should be understood that the preceding or following steps are not necessarily performed in exact order. Instead, various steps can be processed in reverse order or simultaneously. Furthermore, other operations can be added to these processes, or one or more steps can be removed from these processes.

[0049] The inventors of this disclosure have discovered that, due to the sheer volume of random fields in a single instruction of a General Purpose Graphics Processing Unit (GPGPU) instruction set, as well as the number of intersections between random fields and various combinations between multiple instructions—for example, the combinations of some complex single VLIW (Very Long Instruction Word) basic domains have reached tens of millions—traditional methods of collecting functional coverage (such as collecting functional coverage through EDA simulation tools) are insufficient to meet such a massive amount of data, nor are they suitable for such a massive amount of data. They can only manually split and discard certain combinations based on priority and urgency, resulting in incomplete coverage collection and difficulties in subsequent analysis.

[0050] At least one embodiment of this disclosure provides a verification method for a processor. The verification method includes: during regression verification of the processor, obtaining a first stimulus to be verified corresponding to a target instruction set of the processor, wherein the first stimulus includes one or more instructions to be verified; and based on the one or more instructions to be verified of the first stimulus, obtaining a current functional coverage including the first stimulus by operating a first database, wherein the first database stores a set of comparison data for verifying the functional coverage.

[0051] The embodiments disclosed above utilize a database to collect functional coverage data corresponding to instructions gathered during the processor regression verification process. This enables more comprehensive and clear functional coverage analysis oriented towards instruction sets, making it suitable for verifying processors with highly complex instruction sets. It overcomes the limitations of traditional coverage collection methods in such specific scenarios as instruction sets, and allows for rapid convergence and more complete verification work with limited time, manpower, and resources, facilitating subsequent tape-out.

[0052] Figure 1 This is a flowchart of a verification method for a processor proposed in some embodiments of this disclosure.

[0053] For example, such as Figure 1 As shown, the verification method includes at least steps S11 and S12.

[0054] Step S11: In the regression verification process for the processor, obtain the first stimulus to be verified corresponding to the target instruction set of the processor, wherein the first stimulus includes one or more instructions to be verified.

[0055] Step S12: Based on one or more instructions to be verified for the first stimulus, obtain the current functional coverage including the first stimulus by operating the first database, wherein the first database stores a set of comparison data for verifying the functional coverage.

[0056] At least one embodiment of this disclosure uses a database to collect the functional coverage of instructions collected during the regression verification process of the processor, thereby achieving a more comprehensive and clear functional coverage analysis oriented towards the instruction set. This is applicable to the verification of processors with high-complexity instruction sets, and solves the limitations of traditional coverage collection methods in the special scenario of instruction sets. It can achieve rapid convergence and more complete verification work with limited time, manpower, and resources, which is beneficial to subsequent tape-out.

[0057] For example, in step S11, the target instruction set refers to a collection of instructions. As a specialized unit for computation and logic control, the processor packages commonly used computations or logic controls into single instructions. When developing programs based on a specific processor platform, users can directly use these instructions to achieve specific goals. The combination of these instructions is called an instruction set. The embodiments of this disclosure do not limit the target instruction set; it can be determined according to the actual situation, and will not be elaborated further here.

[0058] For example, in step S11, processor regression verification refers to the verification of the processor by developing test cases and the regression testing used to ensure the convergence of the verification results. For example, the verification method for processor regression verification in the embodiments of this disclosure is a method for verifying the completeness of the processor's regression verification.

[0059] For example, the processor can be a chip with a specific instruction set, such as a GPGPU. The method of the embodiments of this disclosure is applicable to scenarios involving the verification of chips with specific instruction sets, such as GPGPUs. Although the complexity of the instruction set is high in this scenario, resulting in an excessively large number of combinations of random instruction stimuli generated by a given instruction set, the embodiments of this disclosure can still achieve a more comprehensive and clear functional coverage analysis oriented towards the instruction set by using a database for functional coverage analysis. This allows for rapid convergence and more complete verification work with limited human and material resources.

[0060] In some examples, the processors applicable to the embodiments of this disclosure are not limited to the GPGPU described above, but may also be other types of processors, such as a central processing unit (CPU) or a dedicated instruction set processor (ASIP). The embodiments of this disclosure are not limited or described in detail here.

[0061] For example, in step S11, the instructions to be verified included in the first stimulus are derived from test cases in the backtesting verification used to verify the processor, in order to calculate whether the regression verification fully covers all functional points, i.e., to obtain the corresponding functional coverage. For example, the instructions to be verified are collected in real time during the processor's regression verification process to obtain the first stimulus.

[0062] Figure 2 This is a flowchart of a verification method for a processor according to other embodiments of this disclosure. For example, such as Figure 2 As shown, the verification method includes at least steps S21 to S23.

[0063] Step S21: In the regression verification process for the processor, obtain the first stimulus to be verified corresponding to the target instruction set of the processor, wherein the first stimulus includes one or more instructions to be verified.

[0064] Step S22: In response to the first stimulus, each of the one or more instructions to be verified being machine code, the machine code is received by the assembler and processed to form disassembly instructions in text format, thereby obtaining the disassembly instruction set corresponding to the first stimulus.

[0065] Step S23: Based on the disassembly instruction set corresponding to the first stimulus, obtain the current functional coverage including the first stimulus by operating the first database, wherein the first database stores a set of comparison data for verifying the functional coverage.

[0066] The embodiments of this disclosure obtain the disassembled instructions corresponding to the first stimulus through assembly processing, so as to improve the readability of the instructions to be verified, which is conducive to the execution of the verification method of this disclosure and to obtain functional coverage.

[0067] In some examples, the first database is a collection of tables. For example, the first database is an SQL (Structured Query Language) database. An SQL database is a collection of tables defined by one or more SQL schemas. An SQL table consists of a set of rows, where a row is a sequence (set) of columns, and each column corresponds to a data item in the row. For example, the first database could be a PostgreSQL database. This is merely exemplary, and other types of SQL databases are also possible, and the embodiments of this disclosure are not limited thereto. Since SQL databases are not the focus of the embodiments described in this disclosure, they will not be elaborated upon here.

[0068] In some examples, the comparison data set stored in the first database refers to the set of instructions to be verified that the processor regression verification needs to cover. The comparison data set can be pre-stored in the first database. For example, the current functional coverage including the first stimulus is equal to the ratio of the number of disassembled instructions corresponding to all currently verified covered data sets to the number of instructions to be verified corresponding to the ideal comparison data set.

[0069] In some examples, the disassembled instruction set corresponding to the first stimulus includes a Very Long Instruction Word (VLE). Thus, the embodiments of this disclosure are well-suited for verifying processors that include VLEs, enabling not only a more comprehensive and clear functional coverage analysis oriented towards the instruction set, but also saving time, manpower, and resource costs.

[0070] Figure 3 yes Figure 2 A flowchart illustrating the execution process of step S23 in the processor verification method. For example, as... Figure 3 As shown, an example of step S23 includes at least steps S231 to S233.

[0071] Step S231: Based on the disassembly instruction set corresponding to the first stimulus, obtain the intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus.

[0072] Step S232: Collect the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus, and obtain the covered data set.

[0073] Step S233: Operate the first database, compare the covered data set and the comparison data set, and obtain the current functional coverage rate including the first stimulus.

[0074] The embodiments of this disclosure preprocess the disassembly instruction set to ensure its effective inclusion, thereby obtaining a data set to be compared with the comparison data set. This approach is effectively applicable to verification scenarios with large amounts of data and has a wide range of applications.

[0075] For example, in step S231, in some examples, based on the disassembly instruction set corresponding to the first stimulus, the intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus includes the following process or steps: by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, at least one field segment of each disassembly instruction in the disassembly instruction set is obtained to obtain the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus. For example, when preprocessing disassembly instructions in text format, the value of each field segment of the disassembly instruction can be accurately extracted according to a specific instruction set architecture, thereby obtaining the intermediate data corresponding to the disassembly instruction.

[0076] The embodiments of this disclosure obtain information for each field segment by preprocessing the disassembly instructions, and the intermediate data corresponds one-to-one with the disassembly instructions, thereby enabling accurate collection of functional coverage.

[0077] In some examples, at least one field of the disassembled instruction includes an opcode. In other examples, at least one field of the disassembled instruction includes an opcode and at least one of a prefix, modifiers, and operands. For example, the instruction format of the disassembled instruction may include a prefix, opcode, operands, and a large number of modifiers, thereby generating a high order of magnitude of random combinations in regression verification. This is merely exemplary and is not a limitation of this disclosure; the disassembled instructions of this disclosure may also be constructed in other ways, which will not be elaborated here.

[0078] In some examples, certain embodiments of this disclosure implement preprocessing using Python. This provides greater flexibility. Of course, this is merely exemplary and not a limitation of this disclosure.

[0079] For example, in some examples, step S232 involves collecting the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus to obtain an overwritten data set, including the following step S2321: collecting the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus into the first database, so that the first database contains the overwritten data set.

[0080] For example, for step S233, in some examples, operating the first database, comparing the covered data set and the comparison data set, and obtaining the current functional coverage including the first stimulus, includes the following process or steps: using operation instructions of a database operation language for the first database encapsulated by the first programming language to operate the first database to obtain the current functional coverage including the first stimulus.

[0081] For example, for step S232, in some examples, the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus is included to obtain the covered data set, including the following process or steps: using the operation instructions of the database operation language for the first database encapsulated by the first programming language, so that the first database includes the covered data set.

[0082] Therefore, the embodiments of this disclosure utilize a flexible programming language to encapsulate the operation instructions of a database operation language with high query efficiency to realize data entry and function coverage collection of the first database, which can both meet the need for flexibility and improve efficiency.

[0083] In some examples, the first language is a scripting programming language.

[0084] Figure 4 This diagram illustrates performance optimization of psql operations provided in some embodiments of this disclosure.

[0085] For example, such as Figure 4 As shown, the first language is Python, an object-oriented high-level language. The first database is PostgreSQL, and the database operation language is SQL. SQL is a database query language and lacks the flow control features of high-level languages. For example, the operation commands used in the first database are various operations based on psql, which can be implemented through scripts, such as for data entry and coverage collection. psql is a built-in command-line tool in PostgreSQL that can not only perform basic SQL functions but also execute scripts, import / export data, and restore table data. The psql command-line tool includes two operating modes: interactive mode and non-interactive mode.

[0086] Some embodiments of this disclosure utilize the object-oriented features of Python to encapsulate various psql operations into Python instance methods through custom modules. This allows for direct import of the encapsulated module in actual development work, enabling development in a full Python environment. Specifically, it utilizes Python's psycopg2 interface to execute SQL statements in the PostgreSQL database, thereby improving development efficiency and reducing error rates.

[0087] In some examples, before inputting the intermediate data corresponding to the disassembled instructions into the SQL database, the data format of the intermediate data obtained after disassembly instruction preprocessing needs to conform to the general format of SQL tables. Furthermore, before inputting the intermediate data corresponding to the disassembled instructions into the SQL database, it is also necessary to ensure the accuracy of the content of the intermediate data after disassembly instruction conversion. In this way, the insertion of the intermediate data corresponding to the disassembled instructions into the SQL table can be automated.

[0088] For example, in some examples, for step S2321, the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is recorded into the first database, so that the first database contains the covered data set, including the following process or steps: checking the intermediate data to be recorded into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, so that the intermediate data corresponding to the disassembly instruction conforms to the general format of the first database and that the intermediate data corresponding to the disassembly instruction includes the information of each field segment in at least one field segment of the corresponding disassembly instruction.

[0089] For example, if the intermediate data of the disassembly instructions conforms to the general format of the first database and includes information for all fields corresponding to the corresponding disassembly instructions, then the intermediate data of the disassembly instructions is entered into the first database. Conversely, if the intermediate data of the disassembly instructions does not conform to the general format of the first database, or if the intermediate data of the disassembly instructions does not completely include information for all fields corresponding to the corresponding disassembly instructions, then an error needs to be reported, and the process should return to the previous step to modify the preprocessing script to ensure the preprocessing result is correct.

[0090] The embodiments of this disclosure ensure that the intermediate data of all disassembled instructions can be successfully entered into the first database by checking the preprocessed intermediate data, and by checking whether there is any information loss during the preprocessing process, the information provided by the intermediate data can contain all the information of the original data, thereby accurately obtaining the functional coverage.

[0091] Figure 5 This is a flowchart illustrating the execution process of checking the intermediate data to be entered into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, as provided in some embodiments of this disclosure.

[0092] For example, such as Figure 5 As shown, an example of checking the intermediate data to be entered into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus includes at least steps T1 to T4.

[0093] Step T1: Obtain the original string based on the instruction code format of the disassembled instructions.

[0094] Step T2: Obtain the intermediate format of the intermediate data, wherein the intermediate format is consistent with the general format of the first database.

[0095] Step T3: Restore the intermediate data from the intermediate format according to the instruction code format to obtain the restored string corresponding to the disassembled instruction.

[0096] Step T4: In response to the consistency between the restored string of the disassembly instruction and the corresponding original string, it is determined that the intermediate data of the disassembly instruction corresponds one-to-one with each field segment in at least one field segment of the corresponding disassembly instruction, thereby determining that the check of the disassembly instructions included in the first database has passed.

[0097] In some examples, embodiments of this disclosure automatically determine whether the restored string and the corresponding original string are consistent by comparing the values ​​of each field in the restored string and the original string using a script. For example, if all fields in the restored string and the corresponding original string are the same, it indicates that the restored string and the original string are the same, and the instruction to be included has no missing information and no conversion error; conversely, if the restored string and the corresponding original string are different, the instruction to be included has missing information and / or conversion error, and an error is automatically reported, and the conversion tool is debugged (e.g., manually repaired) after the error is reported.

[0098] The embodiments of this disclosure restore the preprocessed intermediate data according to the instruction code format. By comparing the consistency between the original string and the restored string, automatic detection of instruction input errors is achieved, solving the problem of unreliability of manual inspection. This ensures that no information is omitted from the instructions to be included or avoids conversion errors, making the function coverage index more accurate.

[0099] In some examples, embodiments of this disclosure utilize Python to inspect preprocessed intermediate data. This provides greater flexibility. Of course, this is merely exemplary and not a limitation of this disclosure.

[0100] Figure 6A This is a schematic diagram of the original string of disassembled instructions provided for some embodiments of this disclosure. Figure 6B Correspondence provided for some embodiments of this disclosure Figure 6A A diagram illustrating the restoration of the string from the disassembled instructions.

[0101] For example, in Figure 6A and Figure 6B In the example, Figure 6A raw strings and Figure 6A The restored strings are not equal because the prefix of the disassembled instruction code is lost, i.e., they become... Figure 6A The null value shown indicates that a conversion error occurred during the preprocessing of the disassembly instruction into intermediate data.

[0102] Therefore, the embodiments of this disclosure cleverly utilize the directness and simplicity of restoring intermediate data according to the instruction code format, and compare the original string and the restored string to effectively and accurately check whether there are errors in the disassembly instruction preprocessing. The operation is simple and highly efficient.

[0103] Figure 7 yes Figure 2 A flowchart illustrating the execution process of step S21 of the verification method. For example, as... Figure 7 As shown, an example of step S21 includes at least steps S211 to S212.

[0104] Step S211: Based on the regression verification process for the processor, determine one or more test phases of the regression verification process.

[0105] Step S212: Based on each current test stage in one or more test stages, obtain a second stimulus corresponding to the current test stage, wherein the second stimulus corresponding to each current test stage is the current first stimulus.

[0106] For example, in step S211, the regression verification process for the processor can be divided into a test phase, and thus the test phase corresponds to the entire regression verification process, thereby obtaining the functional coverage of the first stimulus corresponding to the test phase.

[0107] For example, in step S211, the regression verification process for the processor can also be divided into multiple testing phases (see below for details). Figure 7 (For example), the entire regression verification process can only be completed after all these multiple test phases are executed, thereby obtaining the functional coverage of the first stimulus corresponding to these multiple test phases.

[0108] In some examples, the execution process of step S11 can also refer to the execution process of step S21, which will not be repeated here.

[0109] In some examples, the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is recorded in the first database, so that the first database contains the covered data set, including the following process or step A1: deduplicating the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus recorded in the first database, so that the disassembly instruction corresponding to the intermediate data in the covered data set in the first database is unique.

[0110] Therefore, the embodiments of this disclosure obtain the covered data set in the first database through deduplication, which can avoid repetitive analysis work, improve the efficiency of functional coverage analysis, and reduce costs.

[0111] For example, step A1 above can be applied to the case where the regression verification process for the processor is divided into a test phase. In this way, the present embodiment performs deduplication in a regression verification process in one phase, avoiding duplication of intermediate data in the covered data set in the first database. That is, the disassembly instructions corresponding to the covered data set are unique, thereby improving the efficiency of functional coverage analysis.

[0112] For example, step A1 above can be applied to the case where the regression verification process for the processor is divided into a test phase. The operation of recording intermediate data of disassembled instructions into the first database is added to the regression verification process. For instance, after each test case is completed, the newly recorded intermediate data of disassembled instructions is deduplicated by comparing it with the already recorded intermediate data of disassembled instructions in the first database. The inventors of this disclosure have found that this causes the number of records in the first database to continuously increase. Given a large number of combinations of random instruction stimuli generated by a given instruction set, each deduplication requires querying a large amount of data, thus slowing down the regression verification process.

[0113] In some examples, where the regression verification process for the processor is divided into multiple test phases, the verification method of the embodiments of this disclosure further includes the following step S31: for each current test phase in the multiple test phases, based on the disassembled instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database.

[0114] In some examples, for step S31, for each stage, the specific implementation of obtaining the current functional coverage including the first stimulus by operating the first database based on the disassembled instruction set corresponding to the first stimulus can be any reasonable embodiment described above, or other specific methods (see below). The embodiments disclosed herein are not limited.

[0115] In some examples, the verification method of embodiments of this disclosure further includes the following step B1: in response to the current functional coverage including the first stimulus being not less than the target coverage, the regression verification of the processor passes; and in response to the current functional coverage including the first stimulus being less than the target coverage, the first stimulus is updated, and the updated first stimulus is used to update the functional coverage until the obtained functional coverage including the updated first stimulus is not less than the target coverage, and the regression verification of the processor passes.

[0116] For example, if the target coverage is 100%, and the obtained functional coverage is 100%, it means that all the instructions to be verified in the verification plan have been randomly generated during the regression verification process, and the processor verification work is complete. Of course, the embodiments of this disclosure do not limit the target coverage, and it can be freely adjusted according to actual needs. The embodiments of this disclosure are not limited in this respect.

[0117] For example, if the current functional coverage is less than 100%, the regression validation is optimized by adding uncovered scenarios (Addhole), which causes the regression validation to generate new instructions to be validated and re-acquire new functional coverage until the functional coverage reaches 100%.

[0118] For example, step B1 above can be applied to the case where the regression verification process for the processor is divided into one test phase. If the current functional coverage is less than 100%, then after the completion of this test phase, the uncovered scenarios are added to update the functional coverage until it reaches 100%, then the regression verification is successful.

[0119] For example, step B1 above can be applied to the case where the regression verification process for the processor is divided into multiple test phases. If the entire regression verification process has been executed and the current functional coverage is less than 100%, then after the last test phase is completed, the uncovered scenarios are added to update the functional coverage until it reaches 100%, and then the regression verification passes.

[0120] Figure 8 This is a flowchart illustrating a verification method for a processor, provided for some embodiments of this disclosure.

[0121] For example, such as Figure 8 As shown, the verification method for the processor includes steps Q1 to Q10.

[0122] Step Q1: Begin the current verification method used for the processor.

[0123] Step Q2: During the regression verification process for the processor, obtain the current first stimulus to be verified, which includes one or more instructions to be verified.

[0124] Step Q3: Obtain the intermediate data to be verified corresponding to the disassembled instructions through preprocessing.

[0125] Step Q4: Check the intermediate data to be entered into the first database corresponding to the disassembly instruction, and determine whether the intermediate data of the disassembly instruction conforms to the general format of the first database and whether the intermediate data of the disassembly instruction includes information of each field segment in at least one field segment corresponding to the corresponding disassembly instruction: if yes (i.e. pass), then continue to step Q5; if no, return to step Q3.

[0126] Step Q5: Add the intermediate data corresponding to each disassembly instruction in the disassembly instruction set to the first database, so that the first database contains the covered data set.

[0127] Step Q6: Remove duplicates from the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus entered into the first database, so that the disassembly instruction corresponding to the intermediate data in the overwritten data set in the first database is unique.

[0128] Step Q7: Operate the first database, compare the covered data set and the comparison data set, and obtain the current functional coverage including the first stimulus.

[0129] Step Q8: Determine whether the current functional coverage has reached the target coverage (e.g., 100%): If not, proceed to step Q9; if yes, proceed to step Q10.

[0130] Step Q9: Add scenarios that are not yet covered to optimize regression validation, and then proceed to step Q2.

[0131] Step Q10, End, the processor regression verification is successful.

[0132] Therefore, the embodiments of this disclosure can be effectively applied to processor verification scenarios with large amounts of data, with a wide range of applications. They can achieve rapid convergence and more complete verification work with limited time, manpower, and resources, which is beneficial for subsequent tape-out.

[0133] Figure 9 This is a flowchart of an execution process for step S31 of the verification method for the processor. Figure 10 For the corresponding Figure 9 A schematic diagram illustrating the principle of the verification method.

[0134] For example, such as Figure 9 and Figure 10As shown, for each current test phase in multiple test phases, in step S31, based on the disassembled instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database, including the following steps S311 to S314.

[0135] Step S311: Based on the disassembly instruction set corresponding to the first stimulus in the current test phase, obtain the intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus.

[0136] Step S312: Remove duplicate data from the disassembled instruction set corresponding to the first stimulus in the current test phase to obtain a deduplicated data set.

[0137] Step S313: Add the deduplicated data set corresponding to the current test phase to the first database to obtain the corresponding covered data set.

[0138] Step S314: Operate the first database, compare the covered data set and the comparison data set, and obtain the current functional coverage rate including the first stimulus.

[0139] The embodiments of this disclosure divide the regression verification process into multiple test phases and perform initial deduplication for each test phase and obtain the functional coverage of the corresponding current test phase in real time, thereby improving the speed of functional coverage analysis in the entire regression verification process.

[0140] In some examples, the verification method of embodiments of this disclosure further includes the following step S32: for each current test phase in a plurality of test phases, in response to obtaining the current functional coverage including the first stimulus by operating the first database, the deduplicated data set corresponding to the current first stimulus is transferred to the backup second database.

[0141] Thus, in the embodiments of this disclosure, after the functional coverage calculation is completed in each test phase, the deduplicated data set after the initial deduplication in each test phase is stored in the backup database. This will not affect the calculation of functional coverage each time, and can also obtain the intermediate data of the disassembled instruction set of the entire regression verification process, effectively avoiding the problem of slowing down the collection of functional coverage.

[0142] In some examples, for step S32, transferring the deduplicated data set corresponding to the current first stimulus to the backup second database means: storing the deduplicated data set corresponding to the current first stimulus into the backup second database, and then clearing the deduplicated data set corresponding to the current first stimulus already entered in the first database, so that the first database is empty at the beginning of the next stage. This does not affect the calculation of functional coverage each time, and the calculation result of each current stage will update the functional coverage (e.g., the functional coverage increases or remains unchanged), and it also facilitates the deduplication operation, reduces duplicate data, and allows the functional coverage to be calculated faster.

[0143] In some examples, in step S32, the deduplicated data set corresponding to the current first stimulus is transferred to the backup second database, which includes the following process or steps: for the current intermediate data in the deduplicated data set corresponding to the first stimulus, in response to the fact that the disassembly instruction corresponding to the current intermediate data is different from the disassembly instruction corresponding to the intermediate data already stored in the second database, the intermediate data is stored in the second database for backup, so that the disassembly instruction corresponding to the intermediate data in the second database is unique.

[0144] Therefore, the embodiments of this disclosure store current data into the backup database according to the storage condition that the stored data cannot be duplicated with the data in the backup instruction. This results in a completely unique and complete backup data set, minimizing the space occupied by the backup database. Furthermore, the backup database can back up all previous data, and it can be recalled for re-analysis when the functional coverage rules change, making operation convenient and improving efficiency.

[0145] In some examples, the backup second database is a separate data table from the first database, capable of storing a large amount of intermediate data for disassembly instructions. For example, the backup second database could be of the same type as the first database. This is merely illustrative and not a limitation of this disclosure; as long as the second database can store intermediate data for the disassembly instruction set, it is acceptable, and further details will not be elaborated here.

[0146] The embodiments of this disclosure can separate the secondary deduplication operation from the regression verification process, avoiding the problem of slow collection function coverage caused by the need for a large amount of data deduplication.

[0147] For example, in one instance, the regression validation process for the processor is carried out on a weekly cycle, with the regression validation process divided into seven test phases, one for each day of the week.

[0148] Specifically, when performing the current regression verification on Monday, based on the disassembled instruction set corresponding to the first stimulus on Monday, the intermediate data to be verified on Monday is obtained. Initial deduplication of Monday's intermediate data is performed to obtain a deduplicated data set corresponding to Monday. This deduplicated data set is then added to the first database, resulting in the covered data set for Monday. Functional coverage is then calculated to obtain the functional coverage for Monday. The deduplicated data set for Monday is then placed into a backup second database according to the storage conditions, and the deduplicated data set for Monday in the first database is cleared to empty the first database. For Monday, the initial deduplication and functional coverage calculation for this single day are relatively fast. Similarly, when performing the current regression verification on Tuesday, the first database is empty before work begins on Tuesday. Therefore, the initial deduplication of Tuesday's intermediate data and the corresponding functional coverage calculation are also performed. The deduplicated data set for Tuesday is then placed into the backup second database according to the storage conditions, and the deduplicated data set for Tuesday is cleared from the first database to empty the first database. Thus, regression verification, initial deduplication, functional coverage calculation, and data backup and wipe are executed sequentially from Wednesday to Sunday. Therefore, after Sunday, the second backup database will contain backup data from that week, with no duplication among the backups. Therefore, the embodiments of this disclosure are applicable to situations where the number of combinations of random instruction stimuli generated by a given instruction set is large, enabling accurate and efficient functional coverage analysis. Of course, this is merely exemplary and not a limitation of this disclosure; the embodiments of this disclosure do not limit the number or time period of test phases.

[0149] Figure 11 This is a schematic diagram illustrating the script structure planning provided for some embodiments of this disclosure.

[0150] For example, such as Figure 11 As shown, the verification method in some embodiments of this disclosure further includes the following process or steps: controlling the verification method according to a modular specification through command-line parameters in the top-level code; wherein the verification method is implemented by executing multiple independent functional modules:

[0151] The update function module is configured to respond to target instruction set updates by obtaining the updated current first stimulus through update parameters.

[0152] The runtime module is configured to obtain the current functional coverage, including the first stimulus, by operating the first database;

[0153] The report acquisition module is configured to acquire a functional coverage report;

[0154] In the transfer module, it is configured to store the deduplicated data set corresponding to the current first stimulus into the backup second database in response to the current first stimulus, and to clear the deduplicated data set corresponding to the current first stimulus that has been entered into the first database.

[0155] Thus, the embodiments of this disclosure standardize the coverage collection process by dividing the functional coverage collection process into independent functional points, which are controlled by the top-level code through command-line parameters. This makes the boundaries between functions clear and easy to maintain.

[0156] In some examples, the verification method of embodiments of this disclosure further includes the following process or steps: classifying one or more instructions to be verified of the first stimulus to obtain multiple instruction sets; and, based on the current functional coverage including the first stimulus, obtaining the relationship between the functional coverage of each instruction set in the multiple instruction sets and time, thereby obtaining a curve between the functional coverage of the multiple instruction sets and time.

[0157] The embodiments of this disclosure can reflect the change in functional coverage as the verification work progresses by obtaining curves between multiple instruction sets and time, thus reflecting the execution progress of the verification plan and facilitating the management of the verification work.

[0158] In some examples, embodiments of this disclosure can classify instructions to be verified according to whether their opcodes are the same. For example, instructions to be verified with the same opcode are grouped into one category, such as addition instructions as one category and subtraction instructions as another. This is merely exemplary and is not a limitation of this disclosure. For example, basic arithmetic operations can also be grouped into one category. Embodiments of this disclosure do not limit this and can be freely adjusted according to specific needs, which will not be elaborated here.

[0159] Figure 12 This is a schematic diagram illustrating the relationship between a set of instructions and time, provided for some embodiments of this disclosure.

[0160] For example, Figure 12 This illustrates the relationship between the functional coverage of the addition instruction set and time. Figure 12 The horizontal axis represents time. Figure 12 The vertical axis represents the functional coverage. From Figure 12 It can be seen that the functional coverage of the addition instruction set changes with the date. The curve shows that as the project converges, it gradually flattens out to reach 100%.

[0161] Figure 13 This is a block diagram of a verification apparatus for a processor provided for some embodiments of this disclosure.

[0162] For example, such as Figure 13As shown, at least one embodiment of this disclosure provides a processor verification apparatus 100 including a stimulus acquisition module 110 and a functional coverage acquisition module 120. The stimulus acquisition module 110 is configured to acquire, during regression verification of the processor, a first stimulus to be verified corresponding to the target instruction set of the processor, the first stimulus including one or more instructions to be verified. The functional coverage acquisition module 120 is configured to acquire, based on the one or more instructions to be verified from the first stimulus, a functional coverage including the first stimulus by operating a first database, the first database storing a set of comparison data for verifying functional coverage.

[0163] In some examples, each of the one or more instructions to be verified in the first stimulus is machine code, and the functional coverage acquisition module 120 includes an assembler 121 configured to receive the machine code and process it into disassembled instructions in text format to obtain the disassembled instruction set corresponding to the first stimulus.

[0164] In some examples, the functional coverage acquisition module 120 further includes a preprocessing module 122, an inclusion processing module 123, and a coverage acquisition module 124. The preprocessing module 122 is configured to acquire, based on the disassembly instruction set corresponding to the first stimulus, intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus. The inclusion processing module 123 is configured to include the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus, obtaining a covered data set. The coverage acquisition module 124 is configured to compare the covered data set and the comparison data set by operating a first database to obtain the current functional coverage including the first stimulus.

[0165] It should be noted that in the embodiments of this disclosure, the processor verification device may include more or fewer modules, and the connection relationship between the modules is not limited and can be determined according to actual needs. The specific configuration of each module is not limited. For specific implementation methods and technical effects of the processor verification device, please refer to the relevant content of the processor verification method provided in the above embodiments of this disclosure, which will not be repeated here.

[0166] The modules in the above embodiments can be configured as software, hardware, firmware, or any combination thereof to perform specific functions. For example, these modules may correspond to dedicated integrated circuits, pure software code, or modules combining software and hardware.

[0167] It should be noted that although the above description of the verification device for the processor divides it into modules for performing corresponding processes, those skilled in the art will understand that the processes performed by each module can also be performed without any specific module division in the verification device or without clear boundaries between the modules.

[0168] Figure 14 This is a schematic diagram of the structure of an electronic device provided in at least one embodiment of the present disclosure. The electronic device 200 includes a processor 210 and a memory 220, wherein the memory 220 stores a computer program, and when the computer program is executed by the processor 210, it implements the verification method of at least some embodiments of the present disclosure.

[0169] The electronic devices in the embodiments of this disclosure may include, but are not limited to, mobile terminals such as laptops and tablets, and fixed terminals such as desktop computers. Figure 14 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0170] For example, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For instance, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts. When the computer program is executed by a processor, the verification method of embodiments of this disclosure is performed.

[0171] It should be noted that the computer-readable medium described above in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In embodiments of this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. In embodiments of this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0172] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0173] It should be noted that, in the embodiments of this disclosure, the specific functions and technical effects of the electronic device 200 can be referred to the description of the verification method above, and will not be repeated here.

[0174] The following points need to be explained:

[0175] (1) The accompanying drawings of the embodiments of this disclosure only involve the structures involved in the embodiments of this disclosure. Other structures can be referred to the general design.

[0176] (2) Where there is no conflict, the embodiments of this disclosure and the features in the embodiments can be combined with each other to obtain new embodiments.

[0177] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. The scope of protection of this disclosure should be determined by the scope of protection of the claims.

Claims

1. A verification method for a processor, comprising: During the regression verification process for the processor, a first stimulus to be verified corresponding to the target instruction set of the processor is obtained, wherein the processor includes a general-purpose graphics processor, and the first stimulus includes one or more instructions to be verified. Based on one or more instructions to be verified by the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database. The first database stores a set of comparison data for verifying the functional coverage. The set of comparison data stored in the first database is a set of data of instructions to be verified that are required to be covered by the regression verification of the processor. The verification method further includes: in response to the first stimulus being acquired, each of the one or more instructions to be verified being machine code, receiving the machine code through an assembler and processing it to form disassembly instructions in text format, thereby obtaining a disassembly instruction set corresponding to the first stimulus; wherein, the current functional coverage including the first stimulus is equal to the ratio of the number of disassembly instructions corresponding to the current covered data set to the number of instructions to be verified corresponding to the comparison data set. The method of obtaining the current functional coverage including the first stimulus by operating the first database based on one or more instructions to be verified based on the first stimulus includes: obtaining the current functional coverage including the first stimulus by operating the first database based on the disassembled instruction set corresponding to the first stimulus. Specifically, based on the disassembly instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database, including: Based on the disassembly instruction set corresponding to the first stimulus, obtain the intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus; The intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus is collected to obtain the covered data set; Operate the first database to compare the covered data set and the comparison data set to obtain the current functional coverage including the first incentive; The method further includes: using a hash index to remove duplicate intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus entered into the first database.

2. The verification method as described in claim 1, wherein, The intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus is collected to obtain the covered data set, including: The intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is included in the first database, so that the first database includes the covered data set.

3. The verification method as described in claim 2, wherein, Operating the first database, comparing the covered data set and the comparison data set to obtain the current functional coverage including the first incentive, includes: Using operation instructions of a database operation language for the first database encapsulated in a first programming language, the first database is manipulated to obtain the current functional coverage including the first stimulus; and The intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus is collected to obtain the covered data set, including: The first database is made to include the covered data set by using operation instructions of a database operation language encapsulated in a first programming language.

4. The verification method as described in claim 2, wherein, Based on the disassembly instruction set corresponding to the first stimulus, obtain the intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, including: By preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, at least one field segment of each disassembly instruction in the disassembly instruction set is obtained, so as to obtain the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus.

5. The verification method as described in claim 4, wherein, The at least one field segment includes an opcode; or, the at least one field segment includes an opcode and at least one of a prefix, a modifier, and an operand.

6. The verification method as described in claim 4, wherein, The intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is included in the first database, so that the first database includes the covered data set, including: Check the intermediate data to be entered into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, so that the intermediate data corresponding to the disassembly instruction conforms to the general format of the first database and that the intermediate data corresponding to the disassembly instruction includes information of each field segment in at least one field segment corresponding to the disassembly instruction.

7. The verification method as described in claim 6, wherein, The intermediate data to be entered into the first database corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is examined, including: Based on the instruction code format of the disassembled instructions, obtain the original string; Obtain the intermediate format of the intermediate data, wherein the intermediate format is consistent with the general format of the first database; The intermediate data is restored from the intermediate format according to the instruction code format to obtain the restored string corresponding to the disassembled instruction; In response to the fact that the restored string of the disassembly instruction matches the corresponding original string, it is determined that the intermediate data of the disassembly instruction corresponds one-to-one with each field segment in at least one field segment of the corresponding disassembly instruction, thereby determining that the check of the disassembly instruction included in the first database has passed.

8. The verification method as described in claim 2, wherein, The intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus is included in the first database, so that the first database includes the covered data set, including: The intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus entered into the first database is deduplicated, so that the disassembly instruction corresponding to the intermediate data in the covered data set in the first database is unique.

9. The verification method as described in claim 1, wherein, During the regression verification process for the processor, obtaining the first stimulus to be verified corresponding to the target instruction set of the processor includes: Based on the regression verification process for the processor, one or more test phases of the regression verification process are determined; For each current test phase in the one or more test phases, a second incentive corresponding to the current test phase is obtained, wherein the second incentive corresponding to each current test phase is the current first incentive.

10. The verification method as described in claim 9, further comprising: For each current test phase among the plurality of test phases, based on the disassembly instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database.

11. The verification method as described in claim 10, wherein, For each current test phase among the plurality of test phases, based on the disassembly instruction set corresponding to the first stimulus, the current functional coverage including the first stimulus is obtained by operating the first database, including: Based on the disassembly instruction set corresponding to the first stimulus in the current test phase, obtain the intermediate data to be verified obtained by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus; The intermediate data of the disassembled instruction set corresponding to the first stimulus in the current test phase is deduplicated to obtain a deduplicated data set. The deduplicated data set corresponding to the current test phase is included in the first database to obtain the corresponding covered data set. Operate the first database to compare the covered data set and the comparison data set to obtain the current functional coverage including the first stimulus.

12. The verification method as described in claim 11, further comprising: For each current test phase among the plurality of test phases, in response to obtaining the current functional coverage including the first stimulus by operating the first database, the deduplicated data set corresponding to the current first stimulus is transferred to the backup second database.

13. The verification method as described in claim 12, wherein, Transfer the deduplicated data set corresponding to the current first incentive to the backup second database, including: For the current intermediate data in the deduplication data set corresponding to the first stimulus, in response to the fact that the disassembly instruction corresponding to the current intermediate data is different from the disassembly instruction corresponding to the intermediate data already stored in the second database, the intermediate data is stored in the second database for backup, so that the disassembly instruction corresponding to the intermediate data in the second database is unique.

14. The verification method as described in claim 12, further comprising: The verification method is controlled by command-line arguments in the top-level code, enabling it to execute according to a modular specification. The verification method is implemented by executing multiple independent functional modules: The update function module is configured to respond to the target instruction set update by obtaining the updated current first stimulus through update parameters; The runtime module is configured to obtain the current functional coverage, including the first stimulus, by operating the first database; The report acquisition module is configured to acquire a functional coverage report; In the transfer module, it is configured to store the deduplicated data set corresponding to the current first stimulus into the backup second database in response to the current first stimulus, and to clear the deduplicated data set corresponding to the current first stimulus that has been entered into the first database.

15. The verification method as described in claim 1, further comprising: If the current functional coverage including the first stimulus is not less than the target coverage, the regression verification of the processor is passed; In response to the current functional coverage including the first stimulus being less than the target coverage, the first stimulus is updated, and the updated first stimulus is used to update the functional coverage until the obtained functional coverage including the updated first stimulus is not less than the target coverage, at which point the regression verification of the processor is passed.

16. The verification method as described in claim 1, further comprising: Classify one or more instructions to be verified from the first stimulus to obtain a set of multiple instruction categories; Based on the current functional coverage including the first stimulus, the relationship between the functional coverage of each instruction set in the multi-instruction set and time is obtained, thereby obtaining the curve between the functional coverage of the multi-instruction set and time.

17. The verification method according to any one of claims 1 to 14, wherein, The set of disassembly instructions corresponding to the first stimulus includes very long instruction words.

18. A verification apparatus for a processor, comprising: The stimulus acquisition module is configured to acquire a first stimulus to be verified corresponding to the target instruction set of the processor during the regression verification process for the processor, wherein the processor includes a general-purpose graphics processor, and the first stimulus includes one or more instructions to be verified. The function coverage acquisition module is configured to acquire the current function coverage including the first stimulus by operating a first database based on one or more instructions to be verified by the first stimulus. The first database stores a set of comparison data for verifying the function coverage. The set of comparison data stored in the first database is a preset set of data of instructions to be verified that need to be covered by the regression verification of the processor. Wherein, each of the one or more instructions to be verified in the first stimulus is machine code, and the functional coverage acquisition module includes: An assembler is configured to receive the machine code and process it into disassembly instructions in text format to obtain a set of disassembly instructions corresponding to the first stimulus; wherein the current functional coverage including the first stimulus is equal to the ratio of the number of disassembly instructions corresponding to the current covered data set to the number of instructions to be verified corresponding to the comparison data set. The process of obtaining the current functional coverage including the first stimulus by operating the first database based on one or more instructions to be verified based on the first stimulus includes: obtaining the current functional coverage including the first stimulus by operating the first database based on the disassembled instruction set corresponding to the first stimulus. The functional coverage acquisition module further includes: The preprocessing module is configured to obtain intermediate data to be verified by preprocessing each disassembly instruction in the disassembly instruction set corresponding to the first stimulus, based on the disassembly instruction set corresponding to the first stimulus. The data collection and processing module is configured to collect the intermediate data to be verified corresponding to the disassembly instruction set corresponding to the first stimulus, and obtain the covered data set. The coverage acquisition module is configured to compare the covered data set and the comparison data set by operating the first database to obtain the current functional coverage including the first stimulus; The verification device is further configured to: use a hash index to deduplicate the intermediate data corresponding to each disassembly instruction in the disassembly instruction set corresponding to the first stimulus entered into the first database.

19. The verification apparatus as claimed in claim 18, wherein, The set of disassembly instructions corresponding to the first stimulus includes very long instruction words.

20. An electronic device, comprising: Processor and memory, The memory stores a computer program, which, when executed by the processor, implements the verification method according to any one of claims 1 to 17.

21. A computer-readable storage medium, wherein, The storage medium stores a computer program, which, when executed by a processor, implements the verification method according to any one of claims 1 to 17.

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