Memory

Abstract

The present invention provides a memory device that, when calibration is initiated, sends a data input signal in a predetermined pattern to a comparator. Different DFE bias currents are applied multiple times to any one of a first DFE unit, a second DFE unit, a third DFE unit, and a fourth DFE unit. The width of the data eye window corresponding to each application is calculated, and the widths of the data eye windows are compared to obtain the data eye window with the largest width. The DFE bias current corresponding to the data eye window with the largest width is set as the optimal DFE bias current. Automatic calibration can be used to set the optimal DFE bias current applied to the DFE unit, thereby minimizing the adverse effects of post-markers on subsequent pulse signals and reducing the possibility of misjudgment.

Description

Technical Field

[0001] The present invention relates to a memory. Background Art

[0002] Memory can be divided into read-only memory (ROM) and random access memory (RAM) based on read-write functionality. The contents stored in ROM are fixed and unchanging; it is a semiconductor memory that can only be read but not written. Random access memory, on the other hand, is a memory that can be both read and written. Furthermore, random access memory can be further divided into SRAM (static) and DRAM (dynamic). SRAM includes SDR SRAM, DDR SRAM, QDR SRAM, and ZBT SRAM; DRAM includes SDRAM, DDR DRAM, and RDRAM.

[0003] DRAM is a clock-synchronous memory that operates based on the processor's clock signal. The command signal defining the action and the address signal specifying the memory cell are sent in parallel and synchronized with the rising edge of the clock. In DDR data transmission, the DQ Strobe (DQS) signal serves as the reference, replacing the clock, and data is transmitted via the DQ bus. The command and address signals are synchronized only to the rising edge of the clock, while the data signal is synchronized to both the rising and falling edges of DQS. The clock, command, and address signals are input unidirectionally from the processor to the DRAM, while DQS and DQ are bidirectional, input to the DRAM during writes and output from the DRAM during reads. Summary of the Invention

[0004] Generally speaking, the controller and memory ( Figure 1 DRAM) need to be connected through interconnection. Figure 1 As shown, the pulse signal sent by the controller is a rectangular pulse. As it passes through the middle interconnection part, the pulse response of the DRAM receiving end becomes Figure 1 The waveform shown below, that is, on the right side of the main mark T0, there will be post marks such as T1, T2, T3, and T4 ( Figure 1 Corresponding to a 4-tap DFE, if the DFE is 1-tap, there is only one post-cursor (T1), which will have an adverse effect on subsequent pulse signals and may cause misjudgment. In the present invention, DFE is the abbreviation of Decision Feedback Equalizer.

[0005] The present invention is designed to address the aforementioned issues. Its purpose is to provide a memory device that, when calibration is initiated, sends a data input signal in a predetermined pattern to a comparator. Different DFE bias currents are applied multiple times to any of the first, second, third, and fourth DFE sections. The width of the data eye window corresponding to each application is calculated, and the widths of the data eye windows are compared to determine the data eye window with the largest width. The DFE bias current corresponding to the data eye window with the largest width is then set as the optimal DFE bias current. This optimal DFE bias current applied to the DFE section can be set through automatic calibration, minimizing the adverse effects of post-markers on subsequent pulse signals and reducing the likelihood of misjudgment.

[0006] The memory according to the first aspect of the present invention includes an input receiving unit, a storage unit, and a calibration unit. The input receiving unit includes a comparator, a first DFE unit, a second DFE unit, a third DFE unit, a fourth DFE unit, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The comparator compares an input data input signal with a reference voltage signal and outputs a data output signal to the first DFE unit, the second DFE unit, the third DFE unit, and the fourth DFE unit. The input receiving unit divides a data clock signal into a first data clock divided signal, a second data clock divided signal, a third data clock divided signal, and a fourth data clock divided signal. The first DFE unit divides the data clock signal into a first data clock divided signal, a second data clock divided signal, a third data clock divided signal, and a fourth data clock divided signal. The first amplifier amplifies the first corrected data output signal according to the first data clock divided signal and outputs the first data output divided signal to the second DFE unit and the storage unit. The second DFE unit corrects the data output signal according to the data output signal and the first data output divided signal output from the first amplifier, and outputs a second corrected data output signal to the second amplifier. The second amplifier amplifies the second corrected data output signal according to the second data clock divided signal and outputs the first data output divided signal to the second amplifier and the storage unit. The second data output signal is output to the third DFE section and the storage unit. The third DFE section corrects the data output signal based on the data output signal and the second data output signal output from the second amplifier, and outputs the third corrected data output signal to the third amplifier. The third amplifier amplifies the third corrected data output signal based on the third data clock signal and outputs the third data output signal to the fourth DFE section and the storage unit. The fourth DFE section corrects the data output signal based on the data output signal and the third data output signal output from the third amplifier, and outputs the fourth corrected data output signal to the fourth amplifier. The fourth amplifier amplifies the fourth corrected data output signal according to the fourth data clock sub-signal and outputs the fourth data output sub-signal to the first DFE unit and the storage unit. When calibration is started, the calibration unit sends a data input signal in a predetermined pattern to the comparator. Different DFE bias currents are applied to any one of the first DFE unit, the second DFE unit, the third DFE unit, and the fourth DFE unit multiple times, and the width of the data eye window corresponding to each application is calculated. The widths of the data eye windows are compared to obtain the data eye window with the largest width, and the DFE bias current corresponding to the data eye window with the largest width is set as the optimal DFE bias current.

[0007] Preferably, in the memory involved in the first aspect of the present invention, the second aspect of the present invention, the first data output sub-signal, the second data output sub-signal, the third data output sub-signal, and the fourth data output sub-signal have phases of 0°, 90°, 180°, and 270°, respectively.

[0008] Preferably, in the memory device according to the first aspect of the present invention, a third aspect of the present invention is configured such that four different DFE bias currents are applied to the first DFE unit.

[0009] Preferably, in the memory according to the third aspect of the present invention, the magnitude of the applied DFE bias current is automatically increased stepwise by operation of a counter.

[0010] Preferably, in the fifth aspect of the present invention, in the memory involved in the first aspect of the present invention,

[0011] When calibration is started, a data input signal of a predetermined pattern is repeatedly sent to the comparator, and the delay of the data clock signal is increased each time. The optimal DFE bias current of each repetition is obtained based on the delayed data clock signal of each repetition.

[0012] Preferably, in the memory according to the first aspect of the present invention, the first DFE unit, the second DFE unit, the third DFE unit, and the fourth DFE unit are all 1-tap DFEs.

[0013] Effects of the Invention

[0014] According to the memory device of the present invention, when calibration is initiated, a data input signal of a predetermined pattern is sent to the comparator. Different DFE bias currents are applied multiple times to any of the first, second, third, and fourth DFE sections. The width of the data eye window corresponding to each application is calculated. The widths of the data eye windows are then compared to determine the data eye window with the largest width. The DFE bias current corresponding to the data eye window with the largest width is then set as the optimal DFE bias current. Automatic calibration is then used to set the optimal DFE bias current applied to the DFE section, minimizing the adverse effects of post-markers on subsequent pulse signals and reducing the likelihood of misjudgment. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 1 is a schematic diagram showing a situation where a pulse response at a DRAM receiving end is post-signaled due to the presence of an interconnection between the controller and the DRAM.

[0016] Figure 2A is a circuit diagram showing an input receiving unit in a memory according to an embodiment of the present invention; Figure 2B 1 is a circuit diagram showing an example of a specific configuration of the comparator 101 and the DFE unit 201 in the input receiving unit of the memory according to the embodiment of the present invention.

[0017] Figure 3 This is a schematic diagram illustrating an example of increasing the data eye width by applying a bias current to the DFE unit in the memory according to the embodiment of the present invention.

[0018] Figure 4 The present invention is a circuit diagram and signal timing diagram illustrating an example of determining the data eye width in a memory according to an embodiment of the present invention. Four consecutive occurrences of the signal 1, i.e., 1111, indicate that the data eye window check for the specified offset is complete, the data is shifted to the register, and the counter is reset for the next offset.

[0019] Figure 5 An example of a timing chart of each signal pulse when calibration is performed in the memory according to the embodiment of the present invention is shown.

[0020] Figure 6 This is a schematic diagram illustrating how a counter is reset when an abnormal waveform appears in a pulse waveform in a memory according to an embodiment of the present invention.

[0021] Figure 7 It is a signal timing diagram and circuit schematic diagram showing a memory according to an embodiment of the present invention for resetting a counter when an abnormal waveform appears in a pulse waveform.

[0022] Figure 8 This is a schematic diagram showing how BIAS0_CAL / BIAS1_CAL / BIAS2_CAL / BIAS3_CAL are generated by a counter and a decoder during calibration in a memory according to an embodiment of the present invention.

[0023] Figure 9 The memory involved in the embodiment of the present invention is calibrated according to the BIAS0_CNT <n:0> / BIAS1_CNT <n:0> / BIAS2_CNT <n:0> / BIAS3_CNT <n:0>The comparison results of the data eye window are used to generate the BIAS0_WR / BIAS1_WR / BIAS2_WR / BIAS3_WR diagram.

[0024] Figure 10 This is a schematic diagram showing a basic structure of a memory with a calibration function according to an embodiment of the present invention.

[0025] Label Description

[0026] 101 Comparator

[0027] 201 First DFE Department

[0028] 202 Second DFE Department

[0029] 203 Third DFE Department

[0030] 204 Fourth DFE Department

[0031] 301 First Amplifier

[0032] 302 Second Amplifier

[0033] 303 Third Amplifier

[0034] 304 Fourth Amplifier

[0035] 1011 First Transistor

[0036] 1012 Second transistor

[0037] 2011 The Third Transistor

[0038] 2012 The Fourth Transistor

[0039] 10 Input receiving unit

[0040] 11 Calibration Unit

[0041] 12 storage units DETAILED DESCRIPTION

[0042] The present invention is described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be implemented in various ways and should not be limited to the embodiments set forth herein. The sizes and relative sizes of layers and regions may be exaggerated in the drawings for clarity.

[0043] For ease of description, spatially relative terms, such as "below," "beneath," "down," "above," and "upper," may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature.

[0044] Unless otherwise defined, the terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. Terms should be understood to have meanings consistent with their meanings in the context of the relevant technology and should not be understood in an idealized or overly formal sense unless explicitly defined herein.

[0045] Figure 10 This is a schematic diagram showing a basic structure of a memory with a calibration function according to an embodiment of the present invention.

[0046] The memory of the present invention includes an input receiving unit 10, a storage unit 12, and a calibration unit 11. Below, the memory of the present invention is described as an example of a DRAM, but its type is not particularly limited as long as it has the calibration function described in this application.

[0047] Figure 2A is a circuit diagram showing an input receiving unit in a memory according to an embodiment of the present invention; Figure 2B 1 is a circuit diagram showing an example of a specific configuration of the comparator 101 and the DFE unit 201 in the input receiving unit of the memory according to the embodiment of the present invention.

[0048] The input receiving unit includes a comparator 101, a first DFE section 201, a second DFE section 202, a third DFE section 203, a fourth DFE section 204, a first amplifier 301, a second amplifier 302, a third amplifier 303, and a fourth amplifier 304. The comparator 101 compares the input data input signal DQ_IN with the reference voltage signal VREFDQ and outputs a data output signal to the first DFE section 201, the second DFE section 202, the third DFE section 203, and the fourth DFE section 204. The input receiving unit also divides the data clock signal DQS into a first data clock divided signal DQS_0, a second data clock divided signal DQS_90, a third data clock divided signal DQS_180, and a fourth data clock divided signal DQS_270.

[0049] The first DFE unit 201 corrects the data output signal according to the data output signal and the fourth data output sub-signal DQ_270 output from the fourth amplifier 304, and outputs the first corrected data output signal to the first amplifier 301. The first amplifier 301 amplifies the first corrected data output signal according to the first data clock sub-signal DQS_0 and outputs the first data output sub-signal DQ_0 to the second DFE unit 202 and the storage unit.

[0050] The second DFE unit 202 corrects the data output signal according to the data output signal and the first data output sub-signal DQ_0 output from the first amplifier 301, and outputs the second corrected data output signal to the second amplifier 302. The second amplifier 302 amplifies the second corrected data output signal according to the second data clock sub-signal DQS_90 and outputs the second data output sub-signal DQ_90 to the third DFE unit 203 and the storage unit.

[0051] The third DFE unit 203 corrects the data output signal based on the data output signal and the second data output sub-signal DQ_90 output from the second amplifier 302, and outputs the third corrected data output signal to the third amplifier 303. The third amplifier 303 amplifies the third corrected data output signal based on the third data clock sub-signal DQS_180 and outputs the third data output sub-signal DQ_180 to the fourth DFE unit 204 and the storage unit.

[0052] The fourth DFE unit 204 corrects the data output signal based on the data output signal and the third data output sub-signal DQ_180 output from the third amplifier 303, and outputs the fourth corrected data output signal to the fourth amplifier 304. The fourth amplifier 304 amplifies the fourth corrected data output signal based on the fourth data clock sub-signal DQS_270 and outputs the fourth data output sub-signal DQ_270 to the first DFE unit 201 and the storage unit.

[0053] Figure 2A In the example, the phases of the first data output sub-signal DQ_0, the second data output sub-signal DQ_90, the third data output sub-signal DQ_180, and the fourth data output sub-signal DQ_270 are 0°, 90°, 180°, and 270°, respectively.

[0054] As an example of a comparator, the specific structure of the comparator 101 is as follows: Figure 2B As shown, it includes a first transistor 1011, a second transistor 1012, a first resistor 1013, and a second resistor 1014.

[0055] As an example of a DFE unit, the specific structure of the first DFE unit 201 is as follows: Figure 2B As shown, the DFE circuit includes a third transistor 2011, a fourth transistor 2012, and a bias current application terminal. The output signal DQON from the comparator 101 is input to the source of the third transistor 2011, the output signal DQOP from the comparator 101 is input to the source of the fourth transistor 2012, the DQ_N portion of the fourth data output component signal DQ_270 from the fourth amplifier 304 is input to the gate of the third transistor 2011, and the DQ_P portion of the fourth data output component signal DQ_270 from the fourth amplifier 304 is input to the gate of the fourth transistor 2012. The drains of the third transistor 2011 and the fourth transistor 2012 are connected to the bias current application terminal. Furthermore, the specific structures of the second, third, and fourth DFE sections 202, 203, and 204 are similar to those of the first DFE section 201.

[0056] When the calibration is started, the calibration unit sends a data input signal DQ_IN of a predetermined pattern to the comparator 101. For any one of the first DFE section 201, the second DFE section 202, the third DFE section 203, and the fourth DFE section 204 ( Figure 2B , the first DFE unit 201 is shown in FIG. 1 . Different DFE bias currents (BIAS<3:0>) are applied multiple times, and the width of the data eye window corresponding to each application is calculated. The widths of the data eye windows are compared to obtain the data eye window with the largest width. The DFE bias current corresponding to the data eye window with the largest width is set as the optimal DFE bias current.

[0057] Table 1 below shows an example of a DFE offset calibration code automatically generated by a counter during calibration and the bias current corresponding to the DFE offset calibration code.

[0058]

[0059]

[0060] In the example in Table 1, when the counter value CNT<1:0> is 00, the DFE bias calibration code BIAS0_CAL = 1, BIAS1_CAL = 0, BIAS2_CAL = 0, and BIAS3_CAL = 0. At this time, the bias setting BIAS<3:0> is 0001, and the applied bias current is 1 times the bias current, that is, bias current × 1. When the counter value CNT<1:0> is 01, the DFE bias calibration code BIAS0_CAL = 0, BIAS1_CAL = 1, BIAS2_CAL = 0, and BIAS3_CAL = 0. At this time, the bias setting BIAS<3:0> is 0011, and the applied bias current is 2 times the bias current, that is, bias current × 2. When the counter value CNT<1:0> is 10, the DFE bias calibration code BIAS0_CAL = 0, BIAS1_CAL = 0, BIAS2_CAL = 1, and BIAS3_CAL = 0. At this time, the bias setting BIAS<3:0> is 0111, and the applied bias current is 3 times the bias current, that is, bias current × 3. When the counter value CNT<1:0> is 11, the DFE bias calibration code BIAS0_CAL = 0, BIAS1_CAL = 0, BIAS2_CAL = 0, and BIAS3_CAL = 1. At this time, the bias setting BIAS<3:0> is 1111, and the applied bias current is 4 times the bias current, that is, bias current × 4.

[0061] Table 2 below shows an example of a DFE bias code corresponding to an optimal bias current obtained through calibration and applied to the bias current application terminal of the DFE unit during a write operation.

[0062]

[0063]

[0064] In the example of Table 1, when the optimal bias current obtained through calibration is 1 times the bias current, that is, bias current × 1, the corresponding DFE bias codes BIAS0_WR = 1, BIAS1_WR = 0, BIAS2_WR = 0, and BIAS3_WR = 0. In this case, the bias setting BIAS<3:0> is 0001. When the optimal bias current obtained through calibration is 2 times the bias current, that is, bias current × 2, the corresponding DFE bias codes BIAS0_WR = 0, BIAS1_WR = 1, BIAS2_WR = 0, and BIAS3_WR = 0. In this case, the bias setting BIAS<3:0> is 0011. When the optimal bias current obtained through calibration is 3 times the bias current, that is, bias current × 3, the corresponding DFE bias codes BIAS0_WR = 0, BIAS1_WR = 0, BIAS2_WR = 1, and BIAS3_WR = 0. In this case, the bias setting BIAS<3:0> is 0111. When the optimal bias current obtained through calibration is 4 times the bias current, that is, bias current × 4, the corresponding DFE bias codes BIAS0_WR = 0, BIAS1_WR = 0, BIAS2_WR = 0, and BIAS3_WR = 1. At this time, the bias setting BIAS<3:0> is 1111.

[0065] also, Figure 2B Tables 1 and 2 illustrate an example in which four different DFE bias currents, namely bias current ×1, bias current ×2, bias current ×3, and bias current ×4, are applied to the first DFE unit 201. However, the present invention is not limited to this embodiment. For example, DFE bias currents may be applied to other DFE units, and the number of DFE bias current applications is not limited to four.

[0066] Figure 3 This is a schematic diagram illustrating an example of increasing the data eye width by applying a bias current to the DFE unit in the memory according to the embodiment of the present invention.

[0067] like Figure 3 As shown in the figure, the dashed line represents an idealized pulse waveform assuming the absence of noise in the aforementioned impulse response. The second solid line to the right of the dashed line represents the noise waveform of the impulse response generated on the memory receiving end due to the interconnection between the controller and the memory. By applying a bias current to the DFE unit, this second solid line can be shifted leftward to become the first solid line to the right of the dashed line, thereby increasing the data eye width. If the bias current is too low, the waveform will not be able to approach the dashed line as closely as possible, while if the bias current is too high, it may exceed the dashed line. Therefore, it is necessary to find the optimal bias current to ensure that the noise waveform of the aforementioned impulse response closely matches the dashed line.

[0068] Figure 4 A circuit diagram and a signal timing diagram illustrating an example of obtaining a data eye width in a memory according to an embodiment of the present invention. Figure 5 An example of a timing chart of each signal pulse when calibration is performed in the memory according to the embodiment of the present invention is shown.

[0069] First, the controller sends a series of DQ data "1111" to the memory to initialize calibration. Then, the controller sends DQ data "0101" to the memory. Through the operation of the counter, four different DFE bias currents (bias current ×1, bias current ×2, bias current ×3, and bias current ×4) are applied to the first DFE unit 201. The width of the data eye window corresponding to each application is calculated as BIAS0_CNT. <n:0>、BIAS1_CNT <n:0>、BIAS2_CNT <n:0>、BIAS3_CNT <n:0>.

[0070] Then, in Figure 5 In the example, the controller sends DQ data "0101" to the memory again, and repeats the above action after increasing the DQS delay by 1T (10T is the length of a DQ signal). The number of times the controller repeats the DQ data "0101" to the memory depends on the calibration resolution. For example, Figure 5 In the example of , the number of repetitions is 10. In addition, the number of repetitions of the present invention is not limited to this.

[0071] also, Figure 4 In the example, the continuous signal 1 appears 4 times, that is, 1111, indicating that the data eye window check of the specified offset is completed, the data is shifted to the register, and the counter is reset for the next offset.

[0072] Figure 6 This is a schematic diagram illustrating how a counter is reset when an abnormal waveform appears in a pulse waveform in a memory according to an embodiment of the present invention.

[0073] The noise waveform of the impulse response generated on the memory receiving side due to the interconnection between the controller and the memory may be as follows: Figure 6 As shown by the solid line, it will be at a high level (i.e. higher than Figure 6 The horizontal line in the middle (reference voltage VREFDQ) generates a short high level and a short low level period, that is, the signal that should be "1" will be mistakenly judged as "101", thereby counting one more "1" signal. Since the data eye window is defined by continuous data above VREFDQ, Figure 6 The short high level and short low level in the memory are undesirable data. Therefore, the noise waveform of the impulse response generated on the memory receiving end side appears Figure 6 When the low level is short as shown, the counter is reset. The counter can be reset by Figure 7 It can be realized by the signal timing diagram and circuit schematic shown in the figure.

[0074] Figure 7 It is a signal timing diagram and circuit schematic diagram showing a memory according to an embodiment of the present invention for resetting a counter when an abnormal waveform appears in a pulse waveform.

[0075] Figure 7 In the example, when a short low level is detected in the signal of DQ_270 on the memory receiving end side, DET_L becomes a falling edge. At this time, the counter reset signal CNT_R becomes a high level, and the counter is reset to stop measuring the width of the data eye window.

[0076] Figure 8 This is a schematic diagram showing how BIAS0_CAL / BIAS1_CAL / BIAS2_CAL / BIAS3_CAL are generated by a counter and a decoder during calibration in a memory according to an embodiment of the present invention.

[0077] like Figure 8 As shown, during calibration, the counter generates CNT<1:0>, i.e., "00", "01", "10", and "11". The decoder then generates BIAS0_CAL / BIAS1_CAL / BIAS2_CAL / BIAS3_CAL corresponding to CNT<1:0>, as shown in Table 1. This results in the DFE bias setting BIAS<3:0> shown in Table 1 used during calibration.

[0078] Figure 9 The memory involved in the embodiment of the present invention is calibrated according to the BIAS0_CNT <n:0> / BIAS1_CNT <n:0> / BIAS2_CNT <n:0> / BIAS3_CNT <n:0>The comparison results of the data eye window are used to generate the BIAS0_WR / BIAS1_WR / BIAS2_WR / BIAS3_WR diagram.

[0079] Figure 9 BIAS0_CNT <n:0>、BIAS1_CNT <n:0>、BIAS2_CNT <n:0>、BIAS3_CNT <n:0>They respectively represent the widths of the data eye windows corresponding to the application of various DFE bias currents. By comparing the widths of the aforementioned data eye windows, the data eye window with the largest width can be obtained. The DFE bias current corresponding to the data eye window with the largest width is set as the optimal DFE bias current. This allows the DFE bias codes BIAS0_WR, BIAS1_WR, BIAS2_WR, and BIAS3_WR corresponding to the optimal DFE bias current applied to the bias current application terminal of the DFE unit during a write operation to be obtained.

[0080] According to the memory device according to the embodiments of the present invention, when calibration is initiated, a data input signal of a predetermined pattern is sent to the comparator. Different DFE bias currents are applied multiple times to any of the first, second, third, and fourth DFE sections. The width of the data eye window corresponding to each application is calculated. The widths of the data eye windows are then compared to determine the data eye window with the largest width. The DFE bias current corresponding to the data eye window with the largest width is then set as the optimal DFE bias current. Automatic calibration is then used to set the optimal DFE bias current applied to the DFE section, minimizing the adverse effects of post-markers on subsequent pulse signals and reducing the possibility of misjudgment.

[0081] The present invention has been described in detail, but the above embodiments are merely examples of all embodiments and the present invention is not limited thereto. The present invention can freely combine the various embodiments within the scope of the invention, or modify or omit any constituent elements of the various embodiments.

[0082] Industrial applicability

[0083] The memory with calibration function of the present invention can be applied to various types of memories such as SRAM including SDR SRAM, DDR SRAM, QDR SRAM, and ZBT SRAM; DRAM including SDRAM, DDR DRAM, and RDRAM; and ROM.

Claims

1. A memory comprising an input receiving unit, a storage unit, and a calibration unit. The input receiving unit includes a comparator, a first DFE section, a second DFE section, a third DFE section, a fourth DFE section, a first amplifier, a second amplifier, a third amplifier, and a fourth amplifier. The comparator compares an input data input signal with a reference voltage signal and outputs a data output signal to the first DFE section, the second DFE section, the third DFE section, and the fourth DFE section. The input receiving unit also divides a data clock signal into a first data clock divided signal, a second data clock divided signal, a third data clock divided signal, and a fourth data clock divided signal. The first DFE section corrects the data output signal based on the data output signal and a fourth data output component signal output from the fourth amplifier, and outputs a first corrected data output signal to the first amplifier. The first amplifier amplifies the first corrected data output signal based on a first data clock component signal and outputs the first data output component signal to the second DFE section and the storage unit. The second DFE section corrects the data output signal based on the data output signal and the first data output sub-signal output from the first amplifier, and outputs a second corrected data output signal to the second amplifier. The second amplifier amplifies the second corrected data output signal based on a second data clock sub-signal and outputs the second data output sub-signal to the third DFE section and the storage unit. The third DFE section corrects the data output signal based on the data output signal and the second data output sub-signal output from the second amplifier, and outputs a third corrected data output signal to the third amplifier. The third amplifier amplifies the third corrected data output signal based on a third data clock sub-signal and outputs the third data output sub-signal to the fourth DFE section and the storage unit. The fourth DFE section corrects the data output signal based on the data output signal and the third data output sub-signal outputted from the third amplifier, and outputs a fourth corrected data output signal to the fourth amplifier. The fourth amplifier amplifies the fourth corrected data output signal based on a fourth data clock sub-signal and outputs the fourth data output sub-signal to the first DFE section and the storage unit. When calibration is initiated, the calibration unit sends a data input signal of a predetermined pattern to the comparator, applies different DFE bias currents to any one of the first, second, third, and fourth DFE sections multiple times, calculates the width of a data eye window corresponding to each application, compares the widths of the data eye windows to obtain a data eye window with the largest width, and sets the DFE bias current corresponding to the data eye window with the largest width as an optimal DFE bias current.

2. The memory according to claim 1, wherein The phases of the first data output signal, the second data output signal, the third data output signal, and the fourth data output signal are 0°, 90°, 180°, and 270°, respectively.

3. The memory according to claim 1, wherein Four different DFE bias currents are applied to the first DFE section.

4. The memory according to claim 3, wherein The magnitude of the applied DFE bias current is automatically increased step by step through the action of the counter.

5. The memory according to claim 1, wherein When calibration is started, a data input signal of a predetermined pattern is repeatedly sent to the comparator, and the delay of the data clock signal is increased each time. The optimal DFE bias current of each repetition is obtained based on the delayed data clock signal of each repetition.

6. The memory according to claim 1, wherein: The first DFE section, the second DFE section, the third DFE section, and the fourth DFE section are all 1-tap DFEs.

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