Method for Generating Shallow Trench Isolation in 2D Memory

Abstract

The present invention provides a method for generating shallow trench isolation of a 2D memory, which includes forming a tunneling oxide layer on a silicon substrate, and then forming a memory cell region and a peripheral circuit region on the tunneling oxide layer; generating an organic dielectric layer to cover the memory cell region, the peripheral circuit region and the tunneling oxide layer; etching the organic dielectric layer until the tunneling oxide layer of the peripheral circuit region is exposed, and then etching the tunneling oxide layer and the silicon substrate; removing the organic dielectric layer of the memory cell region, and etching the tunneling oxide layer and the silicon substrate again to form a second shallow trench isolation of the memory cell region and a first shallow trench isolation of the peripheral circuit region. During the first etching, the organic dielectric layer can protect the memory cell region and lay a foundation for forming the first shallow trench isolation. The second etching forms the first shallow trench isolation and the second shallow trench isolation. There is no need to increase the etching amount to form the first shallow trench isolation, which protects the memory cell region, and only one photolithography is required, reducing the cost.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor processes, and in particular, to a method for forming shallow trench isolation in a 2D memory. Background Art

[0002] For a 2D memory, in order to reduce the etching difficulty in the storage cell area, the depth of the shallow trench isolation should not be too large. However, the peripheral circuit area has strict requirements for the shallow trench isolation, that is, a larger depth is required.

[0003] In the prior art, the shallow trench isolation in the storage cell area and the peripheral circuit area can be formed respectively through two photomasks, but the additional photomask increases the process cost.

[0004] In the prior art, the shallow trench isolation in the storage cell area and the peripheral circuit area can also be formed simultaneously by using the etching load effect. Although the cost is reduced, the etching amount is large. Since the material of the floating gate layer in the storage cell area is close to that of the silicon substrate, excessive etching will cause the ions that cannot enter the bottom to continuously damage the floating gate layer, thereby damaging the storage cell area and affecting the product reliability.

[0005] Therefore, it is necessary to provide a new method for forming shallow trench isolation in a 2D memory to solve the above problems existing in the prior art. Summary of the Invention

[0006] The purpose of the present invention is to provide a method for forming shallow trench isolation in a 2D memory, which reduces the etching amount in the storage cell area to protect the storage cell area and reduces the cost.

[0007] To achieve the above purpose, the method for forming shallow trench isolation in the 2D memory of the present invention includes:

[0008] Form a tunneling oxide layer on a silicon substrate, and then form a storage cell area and a peripheral circuit area on the tunneling oxide layer;

[0009] Generate an organic dielectric layer to cover the storage cell area, the peripheral circuit area, and the tunneling oxide layer;

[0010] Etch the organic dielectric layer until the tunneling oxide layer in the peripheral circuit area is exposed, and then etch the tunneling oxide layer and the silicon substrate;

[0011] Remove the organic dielectric layer in the storage cell area, and etch the tunneling oxide layer and the silicon substrate again to form a second shallow trench isolation in the storage cell area and a first shallow trench isolation in the peripheral circuit area.

[0012] The beneficial effects of the method for generating shallow trench isolation in the 2D memory are as follows: An organic dielectric layer is generated to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer. The organic dielectric layer is etched until the tunneling oxide layer in the peripheral circuit region is exposed. Then, the tunneling oxide layer and the silicon substrate are etched to remove the organic dielectric layer in the memory cell region. The tunneling oxide layer and the silicon substrate are etched again to form the second shallow trench isolation in the memory cell region and the first shallow trench isolation in the peripheral circuit region. During the first etching, the organic dielectric layer in the memory cell region can protect the memory cell region and lay the foundation for forming the first shallow trench isolation. The second etching forms the first shallow trench isolation and the second shallow trench isolation, without the need to increase excessive etching amount to form the first shallow trench isolation, protecting the memory cell region and only requiring one photolithography, thus reducing the cost.

[0013] Optionally, forming the memory cell region and the peripheral circuit region on the tunneling oxide layer includes:

[0014] Forming a material layer on the tunneling oxide layer;

[0015] Coating a photoresist on the material layer and exposing the photoresist to form a photoresist pattern;

[0016] Etching the material layer using the photoresist pattern as a mask to form the memory cell region and the peripheral circuit region, and then removing the photoresist pattern.

[0017] Optionally, forming the material layer on the tunneling oxide layer includes:

[0018] Sequentially depositing a floating gate layer, a silicon nitride layer, and a silicon oxide layer on the tunneling oxide layer.

[0019] Optionally, forming the memory cell region and the peripheral circuit region on the tunneling oxide layer includes:

[0020] Forming at least two memory cells and at least one peripheral circuit on the tunneling oxide layer. There is a first gap between the memory cells, and there are second gaps both between the peripheral circuits and between the memory cell region and the peripheral circuit region, and the width of the second gap is greater than the width of the first gap. All the memory cells constitute the memory cell region, and all the peripheral circuits constitute the peripheral circuit region.

[0021] Optionally, generating the organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer includes:

[0022] Generating an organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer and filling the first gap and the second gap.

[0023] Optionally, etching the organic dielectric layer until the tunneling oxide layer in the peripheral circuit region is exposed, and then etching the tunneling oxide layer and the silicon substrate, includes:

[0024] Etching the organic dielectric layer until the surface of the tunneling oxide layer located in the second void is exposed;

[0025] Using the memory cell and the peripheral circuit as a mask, etching the tunneling oxide layer exposed in the second void, and then etching the silicon substrate exposed in the second void to form an initial shallow trench isolation on the silicon substrate.

[0026] Optionally, removing the organic dielectric layer, and etching the tunneling oxide layer and the silicon substrate again to form a second shallow trench isolation in the memory cell region and a first shallow trench isolation in the peripheral circuit region, includes:

[0027] Removing the organic dielectric layer in the memory cell region, using the memory cell and the peripheral circuit as a mask, etching the silicon substrate to further form the first shallow trench isolation in the peripheral circuit region from the initial shallow trench isolation, while etching the tunneling oxide layer exposed in the first void, and then etching the silicon substrate exposed in the first void to form the second shallow trench isolation in the memory cell region.

[0028] Optionally, the material of the organic dielectric layer is an organic insulating material. Description of the Drawings

[0029] Figure 1 is a flowchart of a method for generating a shallow trench isolation of a 2D memory according to the present invention;

[0030] Figure 2 is a schematic structural diagram of a first intermediate structure in some embodiments of the present invention;

[0031] Figure 3 is a schematic structural diagram of a second intermediate structure in some embodiments of the present invention;

[0032] Figure 4 is a schematic structural diagram of a third intermediate structure in some embodiments of the present invention;

[0033] Figure 5 is a schematic structural diagram of a fourth intermediate structure in some embodiments of the present invention;

[0034] Figure 6 is a schematic structural diagram of a fifth intermediate structure in some embodiments of the present invention;

[0035] Figure 7 is a schematic structural diagram of a sixth intermediate structure in some embodiments of the present invention. Detailed implementation manners

[0036] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without making creative efforts shall fall within the protection scope of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein shall have the ordinary meanings as understood by those of ordinary skill in the art to which the present invention pertains. The words such as "including" used herein mean that the elements or items appearing before this word cover the elements or items listed after this word and their equivalents, without excluding other elements or items.

[0037] In view of the problems existing in the prior art, an embodiment of the present invention provides a method for generating a shallow trench isolation of a 2D memory. Referring to Figure 1 , the method for generating the shallow trench isolation of the 2D memory includes the following steps:

[0038] S1: Form a tunneling oxide layer on a silicon substrate, and then form a memory cell region and a peripheral circuit region on the tunneling oxide layer;

[0039] S2: Generate an organic dielectric layer to cover the memory cell region, the peripheral circuit region and the tunneling oxide layer;

[0040] S3: Etch the organic dielectric layer until the tunneling oxide layer in the peripheral circuit region is exposed, and then etch the tunneling oxide layer and the silicon substrate;

[0041] S4: Remove the organic dielectric layer in the memory cell region, and etch the tunneling oxide layer and the silicon substrate again to form a second shallow trench isolation in the memory cell region and a first shallow trench isolation in the peripheral circuit region.

[0042] In some embodiments, forming the memory cell region and the peripheral circuit region on the tunneling oxide layer includes:

[0043] Form a material layer on the tunneling oxide layer;

[0044] Coat a photoresist on the material layer, and expose the photoresist to form a photoresist pattern;

[0045] Etch the material layer using the photoresist pattern as a mask to form the memory cell region and the peripheral circuit region, and then remove the photoresist pattern.

[0046] In some embodiments, forming the memory cell region and the peripheral circuit region on the tunneling oxide layer includes: forming at least two memory cells and at least one peripheral circuit on the tunneling oxide layer, having a first gap between the memory cells, having a second gap both between the peripheral circuits and between the memory cell region and the peripheral circuit region, and a width of the second gap being greater than a width of the first gap, wherein all the memory cells constitute the memory cell region and all the peripheral circuits constitute the peripheral circuit region.

[0047] Figure 2 This is a schematic structural diagram of a first intermediate structure in some embodiments of the present invention. Referring to Figure 2 , a tunneling oxide layer 200 is formed on a silicon substrate 100, then a material layer (not labeled in the figure) is formed on the tunneling oxide layer 200, a photoresist (not labeled in the figure) is coated on the material layer, the photoresist is exposed to form a photoresist pattern, and the material layer is etched using the photoresist pattern as a mask to form a memory cell region 300 and a peripheral circuit region 400, thereby forming a first intermediate structure. Among them, the memory cell region 300 includes four memory cells 301 arranged in sequence from left to right, having the first gap 302 between adjacent ones of the four memory cells 301, the peripheral circuit region 400 includes a peripheral circuit located on the right side of the rightmost memory cell 301, having a second gap 401 between the peripheral circuit 301 and the rightmost memory cell 301, and a width of the second gap 401 being greater than a width of the first gap 302.

[0048] In some embodiments, generating the organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer includes: generating an organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer, and filling the first gap and the second gap.

[0049] Figure 3 This is a schematic structural diagram of a second intermediate structure in some embodiments of the present invention. Referring to Figure 2 and Figure 3 , an organic dielectric layer 500 is generated to cover the memory cell region 300, the peripheral circuit region 400, and the tunneling oxide layer 200, and fill the first gap 302 and the second gap 401 to form a second intermediate structure.

[0050] In some embodiments, etching the organic dielectric layer until the tunneling oxide layer of the peripheral circuit region is exposed, and then etching the tunneling oxide layer and the silicon substrate includes:

[0051] Etching the organic dielectric layer until the surface of the tunneling oxide layer located in the second gap is exposed;

[0052] Using the storage unit and the peripheral circuit as a mask, etch the tunneling oxide layer exposed in the second void, and then etch the silicon substrate exposed in the second void to form an initial shallow trench isolation on the silicon substrate.

[0053] Figure 4 It is a schematic structural diagram of a third intermediate structure in some embodiments of the present invention. Refer to Figure 3 and Figure 4 , etch the organic dielectric layer 500 until the surface of the tunneling oxide layer 200 located in the second void is exposed to form a third intermediate structure. Among them, since the width of the first void is smaller than that of the second void, when etching the organic dielectric layer 500, the etching rate of the organic dielectric layer 500 in the first void is less than that of the organic dielectric layer 500 in the second void. Therefore, when the surface of the tunneling oxide layer 200 located in the second void is exposed, there is still part of the organic dielectric layer 500 in the first void.

[0054] Figure 5 It is a schematic structural diagram of a fourth intermediate structure in some embodiments of the present invention. Refer to Figure 4 and Figure 5 , using the silicon oxide layer at the top of the storage unit and the silicon oxide layer at the top of the peripheral circuit as a mask, etch the tunneling oxide layer 200 exposed in the second void, and then etch the silicon substrate 100 exposed in the second void to form an initial shallow trench isolation 402 on the silicon substrate, thereby forming a fourth intermediate structure. Among them, since there is still part of the organic dielectric layer 500 in the first void, the organic dielectric layer 500 protects the tunneling oxide layer 200 whose surface is located in the first void.

[0055] In some embodiments, removing the organic dielectric layer in the storage unit area, and etching the tunneling oxide layer and the silicon substrate again to form the second shallow trench isolation in the storage unit area and the first shallow trench isolation in the peripheral circuit area includes: removing the organic dielectric layer in the storage unit area, using the storage unit and the peripheral circuit as a mask, etching the silicon substrate to further form the first shallow trench isolation in the peripheral circuit area for the initial shallow trench isolation, and simultaneously etching the tunneling oxide layer exposed in the first void, and then etching the silicon substrate exposed in the first void to form the second shallow trench isolation in the storage unit area.

[0056] Figure 6 It is a schematic structural diagram of a fifth intermediate structure in some embodiments of the present invention. Refer to Figure 5 and Figure 6, remove the organic dielectric layer 500 in the memory cell region to form a fifth intermediate structure.

[0057] Figure 7 is a schematic structural diagram of a sixth intermediate structure in some embodiments of the present invention. Refer to Figure 6 and Figure 7 , using the silicon oxide layer on the top of the memory cell and the silicon oxide layer on the top of the peripheral circuit as masks, etch the silicon substrate 100 so that the initial shallow trench isolation 402 becomes the first shallow trench isolation 403 in the peripheral circuit region. At the same time, etch the tunneling oxide layer 200 exposed in the first void, and then etch the silicon substrate 100 exposed in the first void to form the second shallow trench isolation 303 in the memory cell region, so as to form a sixth intermediate structure.

[0058] In some embodiments, the first shallow trench isolation is formed by continuously etching the silicon substrate to increase the initial shallow trench isolation. Therefore, the depth of the first shallow trench isolation is affected by the depth of the initial shallow trench isolation. When etching the silicon substrate to form the initial shallow trench isolation, the organic dielectric layer in the first void protects the tunneling oxide layer and the memory cell. Therefore, when etching the silicon substrate to form the initial shallow trench isolation, the influence on the memory cell is reduced. When etching the silicon substrate so that the initial shallow trench isolation becomes the first shallow trench isolation in the peripheral circuit region, and at the same time etching the tunneling oxide layer exposed in the first void, and then etching the silicon substrate exposed in the first void to form the second shallow trench isolation in the memory cell region, since the depth requirement of the second shallow trench isolation is small, the etching amount is small when etching the second shallow trench isolation, and since the first shallow trench isolation is formed from the initial shallow trench isolation, the etching amount is also small. Therefore, the influence on the memory cell when the etching amount is large is avoided.

[0059] In some embodiments, the material of the organic dielectric layer is an organic insulating material.

[0060] In some embodiments, forming the material layer on the tunneling oxide layer includes: sequentially depositing a floating gate layer, a silicon nitride layer, and a silicon oxide layer on the tunneling oxide layer.

[0061] In some embodiments, refer to Figure 2 , the memory cell and the peripheral circuit are, from bottom to top, a floating gate layer 600, a silicon nitride layer 700, and a silicon oxide layer 800.

[0062] Although the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it should be understood that such modifications and variations are all within the scope and spirit of the present invention as described in the claims. Moreover, the present invention described herein can have other embodiments and can be implemented or realized in various ways.

Claims

1. A method for generating shallow trench isolation of a 2D memory, characterized in that, Including: Form a tunneling oxide layer on a silicon substrate, and then form a memory cell region and a peripheral circuit region on the tunneling oxide layer; Generate an organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer; Etch the organic dielectric layer until the tunneling oxide layer in the peripheral circuit region is exposed, and then etch the tunneling oxide layer and the silicon substrate; Remove the organic dielectric layer in the memory cell region, and etch the tunneling oxide layer and the silicon substrate again to form a second shallow trench isolation in the memory cell region and a first shallow trench isolation in the peripheral circuit region; The forming of the memory cell region and the peripheral circuit region on the tunneling oxide layer includes: forming at least two memory cells and at least one peripheral circuit on the tunneling oxide layer, having a first gap between the memory cells, having a second gap both between the peripheral circuits and between the memory cell region and the peripheral circuit region, and the width of the second gap is greater than the width of the first gap, wherein all the memory cells constitute the memory cell region, and all the peripheral circuits constitute the peripheral circuit region; The generating of the organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer includes: generating an organic dielectric layer to cover the memory cell region, the peripheral circuit region, and the tunneling oxide layer, and filling the first gap and the second gap; The etching of the organic dielectric layer until the tunneling oxide layer in the peripheral circuit region is exposed, and then etching the tunneling oxide layer and the silicon substrate includes: etching the organic dielectric layer until the surface of the tunneling oxide layer located in the second gap is exposed; using the memory cells and the peripheral circuits as masks to etch the tunneling oxide layer exposed in the second gap, and then etching the silicon substrate exposed in the second gap to form an initial shallow trench isolation on the silicon substrate.

2. The method for generating shallow trench isolation of a 2D memory according to claim 1, characterized in that, The forming of the memory cell region and the peripheral circuit region on the tunneling oxide layer includes: Form a material layer on the tunneling oxide layer; Coat a photoresist on the material layer, and expose the photoresist to form a photoresist pattern; Etch the material layer using the photoresist pattern as a mask to form the memory cell region and the peripheral circuit region, and then remove the photoresist pattern.

3. The method for generating shallow trench isolation of a 2D memory according to claim 2, characterized in that, The forming of the material layer on the tunneling oxide layer includes: Deposit a floating gate layer, a silicon nitride layer, and a silicon oxide layer in sequence on the tunneling oxide layer.

4. The method for generating shallow trench isolation of a 2D memory according to claim 1, characterized in that, The removing of the organic dielectric layer in the memory cell region, and etching the tunneling oxide layer and the silicon substrate again to form the second shallow trench isolation in the memory cell region and the first shallow trench isolation in the peripheral circuit region includes: Remove the organic dielectric layer in the memory cell region, use the memory cells and the peripheral circuits as masks to etch the silicon substrate, so that the initial shallow trench isolation further forms the first shallow trench isolation in the peripheral circuit region, and at the same time etch the tunneling oxide layer exposed in the first gap, and then etch the silicon substrate exposed in the first gap to form the second shallow trench isolation in the memory cell region.

5. The method for generating shallow trench isolation of a 2D memory according to claim 1, characterized in that, The material of the organic dielectric layer is an organic insulating material.

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