Method for filling dielectric material in gap structure and reaction chamber

Abstract

The present application relates to a method and a reaction chamber for filling a dielectric material in a gap structure. The method comprises: a doping deposition step: introducing a first deposition gas into the reaction chamber to form a doped silicon oxide loose layer through a high-density plasma chemical vapor deposition reaction, wherein the first deposition gas comprises a silicon precursor, a dopant precursor and an oxygen precursor; an undoped compaction deposition step: forming an undoped silicon oxide dense layer on the doped silicon oxide loose layer, wherein the lower electrode power set in the doping deposition step is less than the lower electrode power set in the undoped compaction deposition step. According to the present application, the dielectric material filled in the gap structure can have a low dielectric constant, which is beneficial to further improve the integration of integrated circuits.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for filling a dielectric material in a gap structure and a chemical vapor deposition reaction chamber for executing the method. Background Art

[0002] In the VLSI process, silicon dioxide, which has excellent thermal stability and moisture resistance, has always been the main insulating material used between metal interconnects, while metal aluminum and copper are the main materials for circuit interconnects in chips. However, with the miniaturization of components and the increase in integration, the number of conductor connections in the circuit continues to increase, resulting in serious transmission delays (RC delays) caused by the parasitic effects of resistance (R) and capacitance (C) in the conductor connection architecture, which has become the main factor limiting the signal transmission speed in the circuit in advanced integrated circuit technology.

[0003] In terms of reducing parasitic capacitance, due to the limitations of process and wire resistance, we cannot consider reducing parasitic capacitance by geometric changes. Therefore, filling the gap structure of integrated circuits with materials with low dielectric constant (also called low κ) has been continuously developed. The gap is the gap in the integrated circuit, and the gap structure refers to the structure with holes or grooves in the integrated circuit, which is different from the flat surface without grooves. Gap filling is called gap filling, that is, filling the gap.

[0004] There are usually two main methods used to reduce the dielectric constant of the filling material. The first method is to try to reduce the polarization of the material itself, including reducing the electronic polarization, ionic polarization and molecular polarization in the material. The other is to create voids in the dielectric material. In terms of technology, the manufacturing of low dielectric constant materials is divided into two main streams: chemical vapor deposition and spin coating, namely CVD and SOD.

[0005] The industry has successfully developed the technical capabilities to deposit a variety of low-k films, including fluorosilicate glass (FSG), carbon-doped silicon oxide (such as Black Diamond), and nitrogen-doped silicon carbide (such as BLOK). Black Diamond film is a chemical vapor deposition film based on silicon oxide with an effective dielectric constant of less than 3.0. BLOK is a low-k copper metal barrier and etch stop layer that can be used as a low-k alternative to silicon nitride in dual-damascene process applications. After the dual-damascene process is integrated with fluorosilicate glass and Black Diamond film, the capacitance value can be reduced by 25% to 35% compared to silicon oxide / silicon nitride materials. At present, in the field of low-k, it has been used to overcome the interface bonding problems between low-k films and between low-k films and metal wiring, greatly improving the adhesion coefficient (Adhesion Energy) between low-k films. Tests show that the adhesion coefficient between Black Diamond film and BLOK film is higher than 5.0J / m2. This technology has greatly improved the success rate of semiconductor back-end packaging processes. The optimization and adjustment of process parameters, such as pressure, gas flow, power, etc., significantly improves the mechanical strength of Black Diamond film. The hardness of Black Diamond film is higher than 2.0GPa, and the modulus is greater than 12.0GPa, which meets the requirements of ultra-large-scale integrated circuit process. The collapse of Black Diamond film under thermal cycle becomes extremely rare, thanks to the effective control of film stress (<40MPa). Extremely large film tensile stress will cause the film to easily break.

[0006] In addition, the industry has successfully achieved the integration of the simultaneous copper oxide removal step and the thin film deposition step in the BLOK process, which greatly improved the interface characteristics between the BLOK film and the copper metal, effectively overcoming the common electron migration and stress migration problems in semiconductor processes. The optimization of process constants has also greatly improved the copper barrier (Cu diffusion) performance, water vapor sealing (Hermeticity) performance, and copper wire leakage current (Leakage Current) performance.

[0007] Due to challenges in integration performance, especially many problems in the packaging field, the development of low dielectric constant materials is still quite slow.

[0008] In the related art, high density plasma chemical vapor deposition (HDPCVD) is used to fill the dielectric material. In the deposition step, the dielectric layer is compacted by bombardment to obtain a dense microstructure. However, this is not conducive to the preparation of materials with low dielectric constants. Summary of the invention

[0009] The purpose of the present application is to provide a method for filling a dielectric material in a gap structure and a chemical vapor deposition reaction chamber for executing the method, so as to solve the problem that the dielectric material filled in the gap structure has a large dielectric constant.

[0010] According to one aspect of the present application, a method for filling a dielectric material in a gap structure is provided, the method comprising:

[0011] Doping deposition step: introducing a first deposition gas into a reaction chamber to form a doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the first deposition gas includes a silicon precursor, a dopant precursor and an oxygen precursor;

[0012] Undoped compaction deposition step: introducing a second deposition gas into the reaction chamber to form an undoped silicon oxide dense layer on the doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the second deposition gas comprises a silicon precursor and an oxygen precursor;

[0013] Wherein, the lower electrode power set in the doped deposition step is smaller than the lower electrode power set in the undoped compaction deposition step.

[0014] In some optional implementations, the power range of the lower electrode set in the doping deposition step is 0-100W.

[0015] In some optional embodiments, the silicon precursor is a mixture of one or more of the following: silane, methylsilane, dimethylsilane, trimethylsilane, trimethyl (trifluoromethyl) silane, tetramethylsilane, dimethyldimethoxysilane, tetramethoxysilane, tetraethoxysilane, tetramethylcyclotetrasiloxane; and / or

[0016] The dopant precursor is a carbon precursor and / or a boron nitride precursor, and the carbon precursor is a mixture of one or more of the following: methane, methanol, methylamine, ethane, ethylene, acetylene, ethanol, ethylamine, propylene, propyne, cyclopropane, isopropanol, butane, benzene, toluene, xylene, ethylbenzene, anisole, etc., and the boron nitride precursor is a mixture of one or more of the following: ammonia, nitrogen, nitric oxide, nitrogen dioxide, laughing gas, carborane, diborane, triborane, tetraborane, pentaborane, hexaborane, boron trichloride, boron tribromide, etc.

[0017] In some optional embodiments, the first deposition gas further includes hydrogen, and the hydrogen is mixed with the dopant precursor and then introduced into the reaction chamber, and the concentration of the hydrogen in the mixture is 1% to 25%.

[0018] In some optional embodiments, after the doping deposition step and before the undoped compaction deposition step, the method further comprises:

[0019] Chemical etching step: introducing etching gas into the reaction chamber to chemically etch the doped silicon oxide loose layer.

[0020] In some optional embodiments, the method further comprises:

[0021] The doping deposition step and the chemical etching step are cyclically performed until the number of cycles reaches a first predetermined number of cycles, and then the undoped compaction deposition step is performed.

[0022] In some optional embodiments, before the doping deposition step, the method further comprises:

[0023] The undoped liner layer deposition step is as follows: a third deposition gas is introduced into the reaction chamber to form an undoped silicon oxide liner layer by chemical vapor deposition reaction, wherein the third deposition gas includes a silicon precursor, an oxygen precursor and hydrogen.

[0024] In some optional embodiments, after the doping deposition step and before the undoped compaction deposition step, the method further comprises:

[0025] Undoped deposition step: introducing a fourth deposition gas into the reaction chamber to form an undoped silicon oxide liner layer on the doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the fourth deposition gas includes a silicon precursor and an oxygen precursor;

[0026] The doping deposition step and the undoped deposition step are cyclically performed until the number of cycles reaches a second predetermined number of cycles, and then the undoped tamping deposition step is performed.

[0027] According to another aspect of the present application, a chemical vapor deposition reaction chamber is also provided, which is used to perform the method described above. The reaction chamber is provided with a central air inlet channel and an edge air inlet nozzle. The central air inlet channel is arranged at the center of the top of the reaction chamber, and the edge air inlet nozzle includes a plurality of air inlet nozzles arranged around the side wall of the reaction chamber, and the jet direction of each of the air inlet nozzles is adjustable.

[0028] In some optional embodiments, the plurality of air inlet nozzles are arranged in two or more layers surrounding the side wall, and the air inlet nozzles in different layers are used to introduce different gases.

[0029] In some optional embodiments, the plurality of air inlet nozzles are arranged in a layer surrounding the side wall and are divided into a plurality of groups, and the air inlet nozzles in different groups are arranged alternately, and the air inlet nozzles in different groups are used to introduce different gases.

[0030] The technical solution of the present application is that in the CVD process, in addition to introducing a silicon precursor and an oxygen precursor into the reaction chamber, a dopant precursor is also introduced to fill the doped silicon oxide in the gap structure. The doped material has a lower dielectric constant than conventional dielectric materials, and the lower electrode power set in the doped deposition step is less than the lower electrode power set in the undoped tamping deposition step, which can significantly reduce the bombardment effect and obtain a doped silicon oxide layer with a loose microstructure. The loose internal microstructure also further reduces its dielectric constant. Filling the gap structure with a dielectric material with a low dielectric constant can significantly reduce the parasitic capacitance in the conductor wiring architecture, alleviate the transmission delay caused by the large parasitic capacitance, and is conducive to further improving the integration of integrated circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The above and other objects, features and advantages of the present application will become more apparent through a more detailed description of exemplary embodiments of the present application in conjunction with the accompanying drawings, wherein the same reference numerals generally represent the same components in the exemplary embodiments of the present application.

[0032] Figure 1 A flow chart showing a method for filling a dielectric material in a gap structure according to an embodiment of the present application is shown.

[0033] Figure 2 A schematic diagram of a shallow trench isolation dielectric filling process according to an exemplary embodiment of the present application is shown.

[0034] Figure 3 A schematic diagram of an interlayer dielectric filling process according to an exemplary embodiment of the present application is shown.

[0035] Figure 4 A schematic diagram of an intermetallic dielectric filling process according to an exemplary embodiment of the present application is shown.

[0036] Figure 5 A cross-sectional schematic diagram of a CVD reaction chamber according to an exemplary embodiment of the present application is shown.

[0037] Figure 6 A projection schematic diagram of a two-layer edge intake nozzle according to an exemplary embodiment of the present application is shown.

[0038] Figure 7 A schematic diagram showing the arrangement of a layer of edge air intake nozzles according to an exemplary embodiment of the present application is shown.

[0039] Figure 8 (a), (b) and (c) are schematic diagrams showing direction adjustment of an edge intake nozzle according to an exemplary embodiment of the present application.

[0040] Fig. 9 A schematic diagram showing the relative positions of a lifting mechanism and an edge intake nozzle according to an exemplary embodiment of the present application is shown.

[0041] Fig.10 A schematic diagram showing the direction adjustment of two vertically arranged air intake nozzles according to an exemplary embodiment of the present application is shown.

[0042] Fig.11 (a) and (b) are schematic diagrams showing the connection between a gas cylinder and an edge intake nozzle according to two exemplary embodiments of the present application. DETAILED DESCRIPTION

[0043] The present application will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to make the present application more thorough and complete, and to fully convey the scope of the present application to those skilled in the art.

[0044] Figure 1 A flow chart of a method for filling a dielectric material in a gap structure according to an embodiment of the present application is shown. As shown in the figure, the method includes the following steps 101 and 102:

[0045] Step 101, a doping deposition step: introducing a first deposition gas into a reaction chamber to form a doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the first deposition gas includes a silicon precursor, a dopant precursor, and an oxygen precursor;

[0046] Step 102, an undoped compaction deposition step: introducing a second deposition gas into the reaction chamber to form an undoped silicon oxide dense layer on the doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the second deposition gas includes a silicon precursor and an oxygen precursor;

[0047] Wherein, the lower electrode power set in the doped deposition step is smaller than the lower electrode power set in the undoped compaction deposition step.

[0048] This embodiment changes the conventional CVD process formula. In the CVD process, in addition to introducing a silicon precursor and an oxygen precursor into the reaction chamber, a dopant precursor is also introduced to fill the doped silicon oxide in the gap structure. The doped material has a lower dielectric constant than the conventional dielectric material, and the lower electrode power set in the doped deposition step is less than the lower electrode power set in the undoped tamping deposition step, which can significantly reduce the bombardment effect and obtain a doped silicon oxide layer with a loose microstructure. The loose internal microstructure also further reduces its dielectric constant. Filling the gap structure with a dielectric material with a low dielectric constant can significantly reduce the parasitic capacitance in the conductor wiring architecture, alleviate the transmission delay caused by the large parasitic capacitance, and help to further improve the integration of integrated circuits.

[0049] In some possible embodiments, the silicon precursor is a mixture of one or more of the following: silane, methylsilane, dimethylsilane, trimethylsilane, trimethyl(trifluoromethyl)silane, tetramethylsilane, dimethyldimethoxysilane, tetramethoxysilane, tetraethoxysilane, and tetramethylcyclotetrasiloxane.

[0050] In some possible embodiments, the dopant precursor is a carbon precursor and / or a boron nitride precursor, and the carbon precursor is a mixture of one or more of the following: methane, methanol, methylamine, ethane, ethylene, acetylene, ethanol, ethylamine, propylene, propyne, cyclopropane, isopropanol, butane, benzene, toluene, xylene, ethylbenzene, anisole, etc., and the boron nitride precursor is a mixture of one or more of the following: ammonia, nitrogen, nitric oxide, nitrogen dioxide, laughing gas, carborane, diborane, triborane, diborane, pentaborane, hexaborane, boron trichloride, boron tribromide, etc. After in-depth research and a large number of experiments, the inventors found that the use of the above-mentioned dopant precursors for doping can effectively reduce the dielectric constant of the obtained doped silicon oxide loose layer.

[0051] In some possible implementations, the first deposition gas further includes hydrogen. The hydrogen is mixed with the dopant precursor and then introduced into the reaction chamber. The concentration of the hydrogen in the mixture is 1% to 25%.

[0052] After in-depth research and a large number of experiments, the inventors found that compared with hydrogen atoms in the silicon precursor, the hydrogen mixed in the above ratio can provide a better reducing environment for generating a loose silicon oxide layer. At the same time, using hydrogen to replace traditional argon gas can further reduce the bombardment effect, making the internal microstructure of the doped silicon oxide loose layer looser, and further reducing the dielectric constant of the dielectric material.

[0053] In some embodiments, after the doping deposition step and before the undoped compaction deposition step, the method further comprises:

[0054] Chemical etching step: introducing etching gas into the reaction chamber to chemically etch the doped silicon oxide loose layer.

[0055] Nitrogen trifluoride can be used as the etching gas. By adopting the above chemical etching steps, the sealing effect can be avoided in the gap structure filling process, and the gap filling capability can be achieved.

[0056] In some embodiments, the method further includes: cyclically performing the doping deposition step and the chemical etching step until the number of cycles reaches a first predetermined number of cycles, and then performing the undoped compaction deposition step.

[0057] By using multiple cycles, filling of gaps with large aspect ratios can be better achieved.

[0058] According to this embodiment, shallow trench isolation dielectric filling can be performed. Figure 2 An exemplary description is given of a shallow trench isolation dielectric filling process according to the present application.

[0059] First, thermal oxidation can be used to grow a silicon oxide substrate layer. The purpose of this layer is to repair the damage caused by shallow trench isolation etching. Figure 2 The shaded part in the middle represents silicon nitride, which is used as a stop layer in the subsequent chemical mechanical polishing. Then, the above-mentioned doping deposition step is performed to form a loose layer of doped silicon oxide. Since the aspect ratio of shallow trench isolation is relatively large, it is easy to seal at the opening, resulting in voids. Therefore, after the process time of the doping deposition step reaches the predetermined time, the above-mentioned chemical etching step is performed. Nitrogen trifluoride can be introduced into the reaction chamber as an etching gas to chemically etch the loose layer of doped silicon oxide. If the aspect ratio is too large, this deposition-etching can be performed alternately in a cycle. In this example, the first predetermined number of cycles is set to 3 times. When the number of cycles reaches the first predetermined number of cycles, the above-mentioned undoped compaction deposition step is performed to form a dense layer of undoped silicon oxide to fill the trench. As described above, in the undoped compaction deposition step, doped silicon oxide is not filled but undoped silicon oxide is filled, and a larger lower electrode power is used to generate high temperature on the one hand and a strong bombardment effect on the other hand to compact the thin film. Both effects can improve the surface density of the film layer and avoid the generation of more particles and other defects during subsequent chemical mechanical polishing. Figure 2 The portion between the two dotted lines in the rightmost image is the doped silicon oxide loose layer. In this example, the doping deposition step uses carbon doping, and a methane precursor is used as the dopant.

[0060] The preferred process recipe of this exemplary embodiment is shown in Table 1.

[0061] Table 1 Plasma etching process recipe

[0062]

[0063] The shallow trench isolation dielectric filling process parameters are as follows: chamber pressure range 1 ~ 200mTorr (mTorr), upper electrode center power range 200 ~ 20000W (watts), upper electrode edge power range 200 ~ 20000W, lower electrode power range 0 ~ 15000W, center NF3 flow range 10 ~ 1000sccm, center SiH4 flow range 10 ~ 1000sccm, edge O2 flow range 10 ~ 1000sccm, edge H2 flow range 10 ~ 1000sccm, edge CH4 flow range 10 ~ 1000sccm, base coolant temperature range -15 ~ 100℃, preferably 50℃.

[0064] Among them, the process parameter value ranges of the doping deposition step can be referred to as follows: the chamber pressure range is 3 to 30 mTorr, the upper electrode center power and the upper electrode edge power range are both 200 to 20000 W, the lower electrode power range is 0 to 100 W, and the process time is 1 second to 1000 seconds.

[0065] In some embodiments, before the doping deposition step, the method further comprises:

[0066] The undoped liner layer deposition step is as follows: a third deposition gas is introduced into the reaction chamber to form an undoped silicon oxide liner layer by chemical vapor deposition reaction, wherein the third deposition gas includes a silicon precursor, an oxygen precursor and hydrogen.

[0067] According to this embodiment, interlayer dielectric filling, intermetallic dielectric filling, and passivation dielectric filling can be performed.

[0068] Figure 3 A schematic diagram of interlayer dielectric filling according to an exemplary embodiment of the present application is shown. The main function of the undoped silicon oxide liner layer in this exemplary embodiment is to adjust stress. The preferred process formula of this exemplary embodiment is shown in Table 2. In this example, carbon doping is used in the doping deposition step.

[0069] Table 2 Plasma etching process recipe

[0070]

[0071] The values ​​of the interlayer dielectric filling process parameters are as follows: chamber pressure range 1~200mTorr, upper electrode center power range 500~15000W, upper electrode edge power range 500~15000W, lower electrode power range 0~15000W, center SiH4 flow range 10~1000sccm, edge O2 flow range 10~1000sccm, edge H2 flow range 10~1000sccm, edge CH4 flow range 10~1000sccm, base coolant temperature range -15~100℃, preferably 50℃.

[0072] Among them, the process parameter value ranges of the doping deposition step are as follows: the chamber pressure range is 3 to 30 mTorr, the upper electrode center power and the upper electrode edge power range are both 200 to 20000 W, the lower electrode power range is 0 to 100 W, and the process time is 1 second to 1000 seconds.

[0073] Figure 4A schematic diagram of intermetallic dielectric filling according to an exemplary embodiment of the present application is shown, in which the metal in the upper example is aluminum and the metal in the lower example is copper. The main function of the undoped silicon oxide liner layer in this exemplary embodiment is to adjust stress and prevent the metal surface from contacting the dopant precursor to prevent graphene from being generated on the metal surface. The preferred process formula of this exemplary embodiment is similar to Table 2. The range of values ​​of the process parameters is also similar to that of the process parameters for interlayer dielectric filling.

[0074] The passivation layer dielectric filling is similar to the intermetallic dielectric filling and will not be described in detail here.

[0075] In some embodiments, after the doping deposition step and before the undoped compaction deposition step, the method further comprises:

[0076] Undoped deposition step: introducing a fourth deposition gas into the reaction chamber to form an undoped silicon oxide liner layer on the doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the fourth deposition gas includes a silicon precursor and an oxygen precursor;

[0077] The doping deposition step and the undoped deposition step are cyclically performed until the number of cycles reaches a second predetermined number of cycles, and then the undoped tamping deposition step is performed.

[0078] The following is a preferred process recipe for performing a cycle of doped deposition-undoped deposition-chemical etching according to an exemplary embodiment of the present application, as shown in Table 3. The example shown in Table 3 is a shallow trench isolation dielectric filling, so in addition to the process steps of each cycle, in addition to doped deposition-undoped deposition, chemical etching is also included. When performing interlayer dielectric filling, intermetallic dielectric filling, and passivation dielectric filling, there is no need to set the chemical etching step in Table 3.

[0079] Table 3 Plasma etching process recipe

[0080]

[0081] Silicon precursors and oxygen precursors can react when in contact under normal temperature and pressure conditions. Therefore, in a CVD reaction chamber, a silicon precursor usually enters the reaction chamber from the top center air inlet channel, and an oxygen precursor enters the reaction chamber from an edge air inlet nozzle disposed around the side wall of the reaction chamber. The dopant precursors (such as carbon precursors, boron nitride precursors, etc.) introduced in this application are not easy to react directly with silicon precursors or oxygen precursors, and they can enter through the center air inlet channel or the edge air inlet nozzle. When an etching gas such as nitrogen trifluoride needs to be introduced according to process requirements, it can also enter the reaction chamber through the top center air inlet channel.

[0082] In some possible embodiments, the silicon precursor and the dopant precursor are introduced into the reaction chamber from a central gas inlet channel, and the oxygen precursor is introduced into the reaction chamber through an edge gas inlet nozzle. The central gas inlet channel is arranged at the center of the top of the reaction chamber, and the edge gas inlet nozzle includes a plurality of gas inlet nozzles arranged around the side wall of the reaction chamber.

[0083] The central air inlet channel may include only one air inlet nozzle, and the silicon precursor and the dopant precursor may be mixed and then enter the reaction chamber from the air inlet nozzle; the central air inlet channel may also include an air inlet nozzle located at the center of the circle and multiple air inlet nozzles arranged in a circle around the center of the circle, and the silicon precursor may enter the reaction chamber from the air inlet nozzle located at the center of the circle, and the dopant precursor may enter the reaction chamber from the air inlet nozzles arranged in a circle around the center of the circle, etc. All of these belong to the protection scope of the present application.

[0084] In some possible implementations, the silicon precursor is introduced into the reaction chamber from a central gas inlet channel, and the dopant precursor and the oxygen precursor are introduced into the reaction chamber from different edge gas inlet nozzles, the central gas inlet channel is arranged at the center of the top of the reaction chamber, and the edge gas inlet nozzles include a plurality of gas inlet nozzles arranged around the side wall of the reaction chamber. The dopant precursor and the oxygen precursor enter through different gas inlet nozzles, which can reduce the interference between the two gases.

[0085] In one example, the plurality of gas inlet nozzles are arranged in two or more layers surrounding the sidewall, and the dopant precursor and the oxygen precursor are introduced into the reaction chamber from gas inlet nozzles in different layers.

[0086] Figure 5 A schematic cross-sectional view of a CVD reaction chamber according to an exemplary embodiment of the present application is shown. As shown in the figure, the edge gas inlet nozzles are arranged in two layers, wherein edge gas inlet 1 represents the upper gas inlet nozzles, and edge gas inlet 2 represents the lower gas inlet nozzles. The projections of the two layers of gas inlet nozzles in the vertical direction may or may not overlap. The dopant precursor (a carbon precursor is used in this example) can be passed into the reaction chamber from the upper gas inlet nozzle, and the oxygen precursor can be passed into the reaction chamber from the lower gas inlet nozzle. The first deposition gas introduced in this example also includes hydrogen, which is mixed with the carbon precursor and then introduced into the reaction chamber from the upper gas inlet nozzle together with the carbon precursor.

[0087] Figure 6 A schematic diagram showing that the projections of the two layers of nozzles do not overlap. The solid line represents the upper layer of air inlet nozzles, which are also newly added air inlet nozzles, and the dotted line represents the lower layer of air inlet nozzles, which are also original air inlet nozzles. The dopant precursor can enter the reaction chamber from the upper layer of nozzles, and the oxygen precursor can enter the reaction chamber from the lower layer of nozzles.

[0088] In one example, the multiple gas inlet nozzles are arranged in a layer surrounding the side wall and are divided into two groups. The two groups of gas inlet nozzles are staggered, the impurity precursor is introduced into the reaction chamber from one group of the gas inlet nozzles, and the oxygen precursor is introduced into the reaction chamber from another group of the gas inlet nozzles.

[0089] Figure 7 A schematic diagram of the arrangement of a layer of edge air inlet nozzles according to an exemplary embodiment of the present application is shown. In the figure, every two closely adjacent air inlet nozzles are divided into different groups, and the air inlet nozzle on the left can be used to introduce a dopant precursor, and the air inlet nozzle on the right can be used to introduce an oxygen precursor.

[0090] In some embodiments, the jet direction of each of the air inlet nozzles is adjustable. The air inlet direction can be adjusted as needed to adjust the air flow field in the chamber. Figure 8 (a), (b) and (c) show schematic diagrams of the direction adjustment of the edge air intake nozzle according to an exemplary embodiment of the present application. The lifting rod is parallel to the chamber wall and does not affect each other. The gear is used for mutual connection when the lifting direction turns 90 degrees. For the specific implementation, please refer to the patent application CN 215896301 U. For the installation of the lifting device, it is sufficient to reserve the installation space without other special requirements.

[0091] Figure 8 In the examples shown in (a), (b) and (c), the lifting mechanism is located below the air inlet nozzle. Alternatively, the lifting mechanism may also be located above the air inlet nozzle, such as Fig. 9 shown.

[0092] Fig.10 A schematic diagram showing the direction adjustment of two vertically arranged intake nozzles in a double-layer intake nozzle example.

[0093] When it is desired that oxygen and silicon precursor react in advance according to process requirements, the edge air inlet nozzle can be set to be tilted upward, thereby reducing the silicon precursor supply in the center and reducing the oxygen precursor supply at the edge; when it is not desired that oxygen and silicon precursor react fully in advance, the edge air inlet nozzle can be set to be tilted downward; in some cases, the edge air inlet nozzle can be set horizontally. Similarly, when the dopant precursor also enters the reaction chamber through the edge air inlet nozzle, the jet direction of the edge air inlet nozzle used to introduce different gases is also determined according to whether the two gases need to be mixed in advance.

[0094] The air inlet nozzle needs to be connected to the gas cylinder. In the case where the direction of the edge air inlet nozzle is adjustable, if the air inlet nozzle and the gas cylinder are rigidly connected, it is easy to cause leakage. Therefore, in some examples, a magnetic fluid can be provided at the interface between each edge air inlet nozzle and the corresponding gas cylinder for sealing, such as Fig.11In other examples, the interface between the air inlet nozzle and the gas cylinder can be connected by a hose seal, such as Fig.11 (b) As shown. This can achieve a good seal and avoid gas leakage.

[0095] The embodiments of the present application have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for filling a dielectric material in a gap structure, characterized in that: The method comprises: Doping deposition step: introducing a first deposition gas into a reaction chamber to form a doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the first deposition gas includes a silicon precursor, a dopant precursor and an oxygen precursor; Undoped compaction deposition step: introducing a second deposition gas into the reaction chamber to form an undoped silicon oxide dense layer on the doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the second deposition gas comprises a silicon precursor and an oxygen precursor; Wherein, the lower electrode power set in the doped deposition step is smaller than the lower electrode power set in the undoped compaction deposition step. 2 . The method according to claim 1 , wherein the power range of the lower electrode set in the doping deposition step is 0 to 100 W.

3. The method according to claim 1, characterized in that: The silicon precursor is a mixture of one or more of the following: silane, methylsilane, dimethylsilane, trimethylsilane, trimethyl(trifluoromethyl)silane, tetramethylsilane, dimethyldimethoxysilane, tetramethoxysilane, tetraethoxysilane, tetramethylcyclotetrasiloxane; and / or The dopant precursor is a carbon precursor and / or a boron nitride precursor, and the carbon precursor is a mixture of one or more of the following: methane, methanol, methylamine, ethane, ethylene, acetylene, ethanol, ethylamine, propylene, propyne, cyclopropane, isopropanol, butane, benzene, toluene, xylene, ethylbenzene, anisole; the boron nitride precursor is a mixture of one or more of the following: ammonia, nitrogen, nitric oxide, nitrogen dioxide, laughing gas, carborane, diborane, triborane, tetraborane, pentaborane, hexaborane, boron trichloride, boron tribromide.

4. The method according to claim 1, characterized in that: The first deposition gas also includes hydrogen. The hydrogen is mixed with the dopant precursor and then introduced into the reaction chamber. The concentration of the hydrogen in the mixture is 1% to 25%.

5. The method according to claim 1, characterized in that After the doping deposition step and before the undoped compaction deposition step, the method further comprises: Chemical etching step: introducing etching gas into the reaction chamber to chemically etch the doped silicon oxide loose layer.

6. The method according to claim 5, characterized in that The method further comprises: The doping deposition step and the chemical etching step are cyclically performed until the number of cycles reaches a first predetermined number of cycles, and then the undoped compaction deposition step is performed.

7. The method according to claim 1, characterized in that Before the doping deposition step, the method further comprises: The undoped liner layer deposition step is as follows: a third deposition gas is introduced into the reaction chamber to form an undoped silicon oxide liner layer by chemical vapor deposition reaction, wherein the third deposition gas includes a silicon precursor, an oxygen precursor and hydrogen.

8. The method according to claim 1, characterized in that After the doping deposition step and before the undoped compaction deposition step, the method further comprises: Undoped deposition step: introducing a fourth deposition gas into the reaction chamber to form an undoped silicon oxide liner layer on the doped silicon oxide loose layer by chemical vapor deposition reaction, wherein the fourth deposition gas includes a silicon precursor and an oxygen precursor; The doping deposition step and the undoped deposition step are cyclically performed until the number of cycles reaches a second predetermined number of cycles, and then the undoped tamping deposition step is performed.

9. A chemical vapor deposition reaction chamber, characterized in that: The reaction chamber is used to perform the method described in any one of claims 1 to 8, and the reaction chamber is provided with a central air inlet channel and an edge air inlet nozzle, wherein the central air inlet channel is arranged at the center of the top of the reaction chamber, and the edge air inlet nozzle includes a plurality of air inlet nozzles arranged around the side wall of the reaction chamber, and the jet direction of each of the air inlet nozzles is adjustable.

10. The reaction chamber according to claim 9, characterized in that: The plurality of air inlet nozzles are arranged in two or more layers surrounding the side wall, and the air inlet nozzles in different layers are used to introduce different gases.

11. The reaction chamber according to claim 9, characterized in that: The plurality of air inlet nozzles are arranged in a layer surrounding the side wall and are divided into a plurality of groups. The air inlet nozzles in different groups are arranged in a staggered manner. The air inlet nozzles in different groups are used to introduce different gases.

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