Serial Image Data Training Method with Per-Line Timing Reset and Low Resource Occupancy

Abstract

A serial image data training method with low resource occupancy and row-by-row timing reset, which relates to a training method for a CMOS image sensor. It solves the problems that the existing image data training method conducts data training during the power-on stage, and the training operation allows to be completed within a relatively long time, which does not meet the requirement of performing word correction in a very short time during the image blanking stage of each row. At the same time, there are problems such as the fixed combination order of the output parallel data. In the imaging stage of the present invention, only the judgment of multiple synchronization word combinations is performed in parallel at three counting positions, and the parallel comparison of multiple delayed data can achieve the effect of comparison at multiple counting positions. Compared with the traditional training method, it can greatly reduce the time required for training and meet the requirements of applications with short blanking periods and high row frequencies. The training method of the present invention is applicable to applications in harsh space environments. The present invention ensures that the image data received after the row-by-row timing reset is the trained image data.

Description

Technical Field

[0001] The present invention relates to a training method for a CMOS image sensor, and more particularly to a serial image data training method with low resource occupancy rate under the timing reset state of each row for applications in harsh space environments. Background Art

[0002] When a CMOS detector is applied in orbit, especially in applications with extremely harsh space environments, high-energy particles are likely to disrupt the internal logic of the detector, resulting in timing errors. One method to improve the space environment adaptability is to perform timing reset on the detector for each row of imaging. Since the phase of the timing reset signal may vary with temperature and be different from that at the beginning of training for each row, the transmission start position of the output serial image data may change. Therefore, word correction and channeling need to be performed on the serial data output by the detector for each row.

[0003] Existing authorized patents, patent number 202110427323.9, patent name: A training method for high and low frequency serial image data, patent number 202010447392.1, patent name: An improved training method for CMOS image data based on alternating transform pulses, both use multiple groups of parallel image data for combination to generate correct parallel data. However, this method is used in the power-on stage and no training is performed after the power-on starts to capture and output the photosensitive image. The data valid signal is generated based on the delay of the timing drive signal; moreover, the training operation allows to be completed within a relatively long time and does not meet the requirement of performing word correction in a very short time during the image blanking stage of each row.

[0004] Existing authorized patent, patent number 202110427711.7, patent name: A serial image data training method based on a sync word. In this patent, the training system includes five stages, namely an idle stage, a bit correction stage based on an accompanying clock, a word correction stage based on an accompanying clock, a channel correction stage based on the sync word sync_code, and a stage for writing the training result. It also performs training based on the sync word sync_code in the power-on stage. The training operation allows to be completed within a relatively long time and does not meet the requirement of performing word correction and dynamic correction in a very short time (not exceeding the length of 3 pixel clocks) during the image blanking stage of each row. Additionally, the combination order of the output parallel data is constant and thus does not change with the detection of each row. Summary of the Invention

[0005] The present invention provides a serial image data training method with per-line timing reset and low resource occupancy to solve the problems of existing image data training methods, which perform data training during the power-on stage and allow the training operation to be completed over a long period of time, and do not meet the requirement of performing character correction in a very short time during the image blanking stage of each line. At the same time, there are problems such as the fixed combination order of output parallel data.

[0006] A serial image data training method with per-line timing reset and low resource occupancy, which is implemented by the following process: The timing reset signal clk_rst_n output by the imaging controller has a low-level reset pulse once during the power-on reset stage; during the training stage, it is at a constant high level; during the imaging stage of the output timing, a low-level reset pulse appears repeatedly for each b-spectrum timing, and this low-level reset pulse is generated before the positive pulse of the line synchronization signal sync_b of each b-spectrum.

[0007] Character correction needs to be performed once within each line period of each b-spectrum; each character correction is started by the line synchronization signal sync_b of the b-spectrum; the p-spectrum data valid signal and the b-spectrum data valid signal are generated after detecting four synchronization words.

[0008] The training of the detector includes two stages, namely the training stage after power-on reset and the training stage corresponding to the imaging stage of the output timing.

[0009] The training stage after power-on reset includes a bit correction stage, and the bit correction requires multiple pixel clock cycles to achieve.

[0010] The training stage corresponding to the imaging stage of the output timing has a duration less than or equal to three pixel clock cycles and is achieved by selecting combinations of parallel data with different delays.

[0011] The combination method of the output parallel data is: output parallel data combination according to whether the least significant bit (LSB) or the most significant bit (MSB) is in the front.

[0012] For the case where the least significant bit (LSB) is in the front, the currently received data is at the highest bit of a single word p bit, the lowest bit data of the original parallel data is shifted out from the parallel data, and the remaining bits in the original parallel data are shifted to the right; the update period is 1 pixel clock cycle.

[0013] For the case where the most significant bit (MSB) is in the front, the currently received data is at the lowest bit of a single word p bit, the highest bit data of the original parallel data is shifted out from the parallel data; the remaining bits in the original parallel data are shifted to the left; the update period is 1 pixel clock cycle.

[0014] When the LSB is in the front and the detected four-word parallel data r-1:r-4p is sync_code1&sync_code2&sync_code3&sync_code4, the output parallel data is r+p-1:r; where r is the number of bits of the parallel data, and the value is less than or equal to 6p; sync_code1, sync_code2, sync_code3, and sync_code4 are four sync words, and the & symbol represents parallelism.

[0015] When the high-order MSB is in the front and the detected four-word parallel data r-4p:r-1 is sync_code4&sync_code3&sync_code2&sync_code1, the output parallel data is r-5p:r-4p-1.

[0016] Advantages of the present invention:

[0017] 1. After the timing reset of each row, due to factors such as temperature drift, the change in the channel correction position is within 1 pixel position. Therefore, it is only necessary to perform the combined judgment of the sync words at a total of three positions, namely the original correct channel correction position and the two adjacent positions before and after, without the need to perform real-time judgment for all time periods. This can avoid the situation where the gray values of adjacent pixels in the photosensitive image happen to be the same as the combination of the sync words, resulting in an incorrect data valid signal indication and an error in the starting position of the valid data for that row.

[0018] 2. During the imaging stage, only the combined judgment of multiple sync word combinations is performed in parallel at three counting positions, and the parallel comparison of multiple delayed data can achieve the effect of comparison at multiple counting positions. Compared with the traditional training method, it can greatly reduce the training time required and meet the requirements of high line frequency applications with a short blanking period.

[0019] 3. During the power-on training stage, only bit correction is performed, without performing word correction and control correction. This can greatly reduce the control resources required for traditional word correction and channels, and reduce the resource occupancy rate. Description of the Drawings

[0020] Figure 1 It is the principle block diagram of the serial image data training system with each row timing reset and low resource occupancy rate according to the present invention;

[0021] Figure 2 It is the schematic diagram of the topological structure of the existing traditional training method;

[0022] Figure 3 It is the schematic diagram of the topological structure of the new training method;

[0023] Figure 4 It is the combined form diagram of the output parallel data when one word is 12;

[0024] Figure 5 It is a diagram of the parallel data arrangement form with the LSB (Least Significant Bit) in the front;

[0025] Figure 6 It is a diagram of the parallel data arrangement form with the MSB (Most Significant Bit) in the front. Specific implementation mode

[0026] Combined with Figure 1 , Figures 3 to 6 This implementation mode is described. A serial image data training method for row-by-row timing reset with low resource occupancy rate. This method is implemented by an imaging system with row-by-row timing as shown in Figure 1 . The imaging system includes an imaging detector, a driving and control circuit, an imaging controller, a memory, and a data transmission interface circuit; the driving and control signals generated by the imaging controller are sent to the imaging detector after passing through the driving and control circuit; among them, the generated timing reset signal performs timing reset on the detector for each row. The digital image data output by the imaging detector is output after being processed by the imaging controller and passing through the data transmission interface circuit. In the imaging state, the imaging detector outputs four sync_codes for each row first, and then outputs the photosensitive image data; the four sync_codes are not the same. In the first sync_code, the highest bit is 1 and the rest are 0; in the second sync_code, the lowest bit is 0 and the rest are 1; the third sync_code is the inversion of the training word (such as 98EH selected for 12-bit application), and the fourth sync_code is the inversion of the lowest bit of the training word.

[0027] In this implementation mode, the low-level pulse of the timing reset signal clk_rst_n is before the positive pulse of the row synchronization signal sync_b of the b-spectrum (multi-spectral spectral band).

[0028] As shown in Table 1, for the timing reset signal clk_rst_n, in the power-on reset stage, only one low-level reset pulse appears; in the training stage, it is at a constant high level; in the imaging stage of the output timing, each b-spectrum timing repeats and one low-level reset pulse appears, and this low-level reset pulse is before the positive pulse of sync_b of each b-spectrum.

[0029] Therefore, word correction needs to be performed once within each row period of each b-spectrum; each word correction is started using the sync_b signal of the b-spectrum; the data valid signals of the p-spectrum (full-color spectral band) and the b-spectrum are not generated according to the row synchronization signals sync_p and sync_b of the p-spectrum and the b-spectrum, but are generated after detecting four sync_codes (the four sync_codes are not the same. In the first sync_code, the highest bit is 1 and the rest are 0; in the second sync_code, the lowest bit is 0 and the rest are 1; the third sync_code is the inversion of the training word, and the fourth sync_code is the inversion of the lowest bit of the training word).

[0030] Table 1 Status of the timing reset signal at different stages

[0031]

[0032] In this embodiment, the training of the detector includes two stages, the training stage after power-on reset and the training stage corresponding to the imaging stage of the output timing; the operations performed in the training stage after power-on reset are different from the traditional training method, and only include the bit correction stage, and the bit correction requires multiple clock cycles to implement; while for the training stage corresponding to the imaging stage of the output timing, the duration does not exceed three pixel clock cycles, and is implemented by the combination selection of parallel data with different delays.

[0033] The combination method of the output parallel data is: the parallel data combination for output according to whether the LSB or the MSB is in the front;

[0034] For the case where the LSB is in the front, the low bit is in the front, and the currently received data is at the highest bit of a single word p bit; the parallel data moves to the right; the update period should be 1 pixel clock cycle (the number of high-speed serial clocks corresponding to 1 word);

[0035] When the LSB is in the front and the detected four-word parallel data (r-1:r-4p) is sync_code1&sync_code2&sync_code3&sync_code4, the output parallel data is (r+p-1:r); where r is the number of bits of the parallel data, and the value is less than or equal to 6p.

[0036] For the case where the MSB is in the front, the high bit is in the front, and the currently received data is at the lowest bit of a single word 12 bit; the parallel data moves to the left; the update period should be 1 pixel clock cycle (the number of high-speed serial clocks corresponding to 1 word);

[0037] When the MSB is in the front and the detected four-word parallel data (r-4p:r-1) is sync_code4&sync_code3&sync_code2&sync_code1, the output parallel data is (r-5p:r-4p-1).

[0038] Such as Figure 2As shown, to achieve word correction and channel correction for serial image data with low resource occupancy, based on the use of traditional delayers IODELY, dual-edge samplers IDDR, multiplexers MUX, shift registers shifer, and cross-clock domain RAMs, six-level delays D1 - D6 for outputting parallel data and a multiplexer MUX1 are added, and finally parallel data Trainparallel data is output. Bit correction uses traditional training methods and requires controlling IODELY and multiplexer MUX; while in the word correction and channel correction stages, the shifer and cross-clock domain RAM are not controlled with variable parameters, only the multiplexer MUX1 is controlled. The detection of parallel data is completed within only three pixel clocks, and the positions of these three pixel clocks are generated through the delay of sync_b. Among them, the control signals of IODELY include a reset signal rst, a delay enable signal ce, and a delay increase / decrease indication signal inc; the MUX selects whether to output the signal sampled from the rising or falling edge under the control of the selection signal Iddr control; the shifer is controlled by the word correction control signal bitslip to change the combination order of the output parallel image data; the RAM is controlled by the channel correction control signal chan_shift_inc to change the relative delay relationship between the input and output parallel data.

[0039] As Figure 3 shown, during the training stage corresponding to the imaging stage of the output timing, word and channel integrated correction is performed and completed within one pixel clock; by searching for the combination of four words (the four synchronous word combinations M1M2M3M4 in the figure, corresponding to 48bit when each word width is 12; corresponding to 4pbit when each word width is p) among six words (the six parallel data A, B, C, D, E, and F in the figure, corresponding to 72bit when each word width is 12; corresponding to 6pbit when each word width is p), the final output is the combination of three parallel data E, F, and G.

[0040] This combination form changes in real-time according to the detection results during both the training stage after power-on reset and the training stage corresponding to the imaging stage of the output timing. The starting position of the output valid data also changes according to the detection results of each training. If it is detected that 70downto 23 is the four synchronous word combination M1M2M3M4, then the output parallel data Dataout is 22downto11. The meaning of downto is from the high bit to the low bit.

[0041] In this embodiment, the imaging detector uses the TDICMOS detector of Changguang Chenxin Company; the data transmission interface circuit uses the TLK2711 chip; the driving and control circuit is mainly based on the level conversion chip 164245; the imaging controller mainly uses the FPGA and refresh chip of Shanghai Fudan Microelectronics Company.

Claims

1. A serial image data training method with sequential reset for each row, which is implemented by an imaging system. The imaging system includes an imaging detector, a driving and control circuit, an imaging controller, a memory, and a data transmission interface circuit. The imaging controller generates driving and control signals, which are sent to the imaging detector after passing through the driving and control circuit. The imaging controller generates a timing reset signal clk_rst_n, and the timing reset signal clk_rst_n performs timing reset on the imaging detector for each line; the imaging detector outputs digital image data, which is processed by the imaging controller and then output through the data transmission interface circuit; characterized in that: the timing reset signal clk_rst_n has a low-level reset pulse once during the power-on reset phase; during the training phase, it is at a constant high level; during the imaging phase of the output timing, a low-level reset pulse repeats once for each multi-spectral band b spectrum, and the low-level reset pulse of the b spectrum is generated before the positive pulse of the line synchronization signal sync_b of each b spectrum; During the imaging phase of the output timing, the imaging detector first outputs four synchronization words sync_code for each line, and then outputs digital image data composed of full-spectrum band P spectrum data and multi-spectral band b spectrum data; the P spectrum data and b spectrum data are generated after detecting the four synchronization words sync_code; The four synchronization words are not the same. The most significant bit of the first synchronization word is 1 and the rest are 0; the least significant bit of the second synchronization word is 0 and the rest are 1; the third synchronization word is the inversion of the training word, and the fourth synchronization word is the inversion of the least significant bit of the training word; The training method includes two stages, namely the training stage after power-on reset and the training stage corresponding to the imaging stage of the output timing; The training stage after power-on reset is the bit correction stage, and this stage is implemented by multiple pixel clock cycles; The training stage corresponding to the imaging stage of the output timing is the word correction stage, and word correction is performed once within each line period of each b spectrum; each word correction is started by the line synchronization signal sync_b of the b spectrum; the duration of the word correction stage is less than or equal to three pixel clock cycles, and is achieved by the combination selection of parallel data with different delays; The combination mode of outputting the parallel data is: the parallel data combination is output according to whether the least significant bit LSB or the most significant bit MSB is in the front; For the case where the least significant bit LSB is in the front, the currently received data is at the most significant bit of a single word p bit, and the update period is 1 pixel clock cycle; when the four-word parallel data r-1:r-4p detected is sync_code1&sync_code2&sync_code3&sync_code4, the output parallel data is r+p-1:r; r is the number of bits of the parallel data, and the value is less than or equal to 6p; sync_code1, sync_code2, sync_code3, and sync_code4 are the four synchronization words, and the & symbol represents parallel; For the case where the most significant bit MSB is in the front, the currently received data is at the least significant bit of a single word p bit, and the update period is 1 pixel clock cycle; when the four-word parallel data r-4p:r-1 detected is sync_code4&sync_code3&sync_code2&sync_code1, the output parallel data is r-5p:r-4p-1.

2. The method according to claim 1, wherein: The combined form of the parallel data is set to a constant central position during the training phase after power-on reset, and during the training phase corresponding to the imaging phase of the output timing, the combined form of the parallel data changes in real time according to the results of each training.

3. The method according to claim 1, wherein: The imaging controller further includes D flip-flops D1 - D6 with a 6-stage delay for outputting parallel data and a multiplexer MUX1; during the word correction phase, the multiplexer MUX1 is controlled.

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