Wafer testing apparatus, wiring inspection method and device, wafer testing apparatus and system

Abstract

A kind of wiring inspection method and device of wafer testing equipment, storage medium, wafer testing equipment and system, the method includes: the ground state of each free pin of the connector connected with the wafer testing equipment is detected, wherein the connector for testing different to-be-tested chips has different preset pin ground states;Whether the detected ground state is same with the preset pin ground state corresponding to the current to-be-tested chip is compared, if yes, it is judged that the wiring between the connector and the wafer testing equipment is correct, otherwise, it is judged that the wiring between the connector and the wafer testing equipment is wrong.By the scheme of the application, whether the wiring between wafer testing equipment and connector is correct can be efficiently and accurately judged.

Description

Technical Field

[0001] This invention relates to the field of semiconductor testing technology, and in particular to a wiring inspection method and apparatus for wafer testing equipment, wafer testing equipment, and wafer testing system. Background Technology

[0002] In existing technologies, when using a circuit probing (CP) system to test a wafer under test, the wafer probing equipment in the system is typically connected to connectors to acquire test signals from each chip under test (DUT) on the wafer. To improve testing efficiency, the circuit probing system usually employs a multi-DUT (Device Under Test) simultaneous testing approach. That is, the wafer probing equipment connects to multiple connectors simultaneously, with each connector corresponding to a different DUT, in order to acquire test signals from multiple DUTs at the same time.

[0003] However, since the wiring between wafer testing equipment and connectors is usually done manually, wiring errors are prone to occur, making it impossible to accurately determine which chip under test the test signal originates from. Therefore, after wiring is completed, manual wiring checks are required. This manual wiring check method is inefficient and prone to errors and omissions.

[0004] Therefore, there is an urgent need for a wiring inspection method for wafer testing equipment that can efficiently and accurately determine whether the wiring between the wafer testing equipment and the connector is correct. Summary of the Invention

[0005] The technical problem solved by this invention is to provide a wiring inspection method for wafer testing equipment, which can efficiently and accurately determine whether the wiring between the wafer testing equipment and the connector is correct.

[0006] To address the aforementioned technical problems, this invention provides a wiring inspection method for a wafer testing device. The method includes: detecting the grounding state of each idle pin of a connector connected to the wafer testing device, wherein connectors used to test different chips under test have different preset pin grounding states; comparing the detected grounding state with the preset pin grounding state corresponding to the current chip under test; if they are the same, determining that the wiring between the connector and the wafer testing device is correct; otherwise, determining that the wiring between the connector and the wafer testing device is incorrect.

[0007] Optionally, in the preset pin grounding state, at least a portion of the free pins of the connector are grounded.

[0008] Optionally, the wafer testing equipment and the connector are connected via a ribbon cable.

[0009] Optionally, the wafer testing equipment includes a test box, and the connector is connected to the test box.

[0010] Optionally, the grounding status of each idle pin of the connector can be detected using the test box.

[0011] Optionally, the detected grounding state is recorded in the test code, and the preset pin grounding state is recorded in the preset code.

[0012] Optionally, both the test code and the preset code are binary codes.

[0013] Optionally, the number of binary-coded symbols is the same as the number of idle pins.

[0014] To address the aforementioned technical problems, this invention also provides a wiring inspection device for a wafer testing equipment. The device includes: a detection module for detecting the grounding state of each idle pin of a connector connected to the wafer testing equipment, wherein connectors used to test different chips under test have different preset pin grounding states; and a judgment module for comparing whether the detected grounding state is the same as the preset pin grounding state corresponding to the current chip under test; if so, determining that the wiring between the connector and the wafer testing equipment is correct; otherwise, determining that the wiring between the connector and the wafer testing equipment is incorrect.

[0015] This invention also provides a storage medium storing a computer program, which, when run by a processor, executes the steps of the above-described wafer testing equipment wiring inspection method.

[0016] This invention also provides a wafer testing device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it executes the steps of the wiring inspection method of the wafer testing device described above.

[0017] This invention also provides a wafer testing system, the system comprising: a plurality of connectors, wherein the connectors for testing different chips under test have different preset pin grounding states; and a wafer testing device for connecting to at least a portion of the plurality of connectors.

[0018] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects:

[0019] In the embodiment of this invention, the wafer testing equipment is connected to multiple connectors. Since connectors testing different chips under test (DUTs) have different preset pin grounding states, the grounding state of each idle pin of the connector is detected, and then compared with the preset pin grounding state corresponding to the current DUT. If the detected grounding state is the same as the preset pin grounding state, it indicates that the connector is testing the current DUT, thus determining that the wiring between the connector and the wafer testing equipment is correct. Otherwise, it indicates that the connector is not testing the current DUT, thus determining that the wiring between the connector and the wafer testing equipment is incorrect. Therefore, the solution in this embodiment of the invention can efficiently and accurately determine whether the wiring between the wafer testing equipment and the connector is correct.

[0020] Furthermore, in the embodiment of the present invention, the grounding status of each idle pin of the connector is detected and recorded in the test code, and the grounding status of the preset pin is recorded in the preset code. Thus, by comparing the test code and the preset code, the detected grounding status and the preset pin grounding status can be compared more intuitively, thereby more efficiently determining whether the wiring between the wafer testing equipment and the connector is correct. Attached Figure Description

[0021] Figure 1 This is a schematic diagram illustrating an application scenario of a wiring inspection method for a wafer testing device according to an embodiment of the present invention.

[0022] Figure 2 This is a schematic flowchart of a wiring inspection method for a wafer testing device according to an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of the wiring inspection device of a wafer testing apparatus according to an embodiment of the present invention. Detailed Implementation

[0024] As mentioned above, when using a circuit probing (CP) system to test a wafer under test, the circuit probing equipment is typically connected to connectors to acquire test signals from each chip under test (DUT) on the wafer. To improve testing efficiency, circuit probing systems often employ a multi-DUT (Device Under Test) testing approach. That is, the circuit probing equipment is connected to multiple connectors, each connector connecting to a corresponding DUT, allowing the circuit probing equipment to acquire test signals from multiple DUTs simultaneously.

[0025] Reference Figure 1 , Figure 1 This is a schematic diagram illustrating an application scenario of a wiring inspection method for a wafer testing device according to an embodiment of the present invention. The following is in conjunction with... Figure 1The application scenarios of the wiring inspection method for wafer testing equipment in the embodiments of the present invention are described in a non-limiting manner.

[0026] The wafer under test 10 may include multiple chips under test, which may be of the same type. The wafer testing equipment 12 may include multiple test units, which can be used to process test signals from the chips under test, such as decoding and analyzing the test signals. A correspondence exists between the test units and the chips under test, and this correspondence may be predefined. More specifically, the correspondence may be pre-stored in the wafer testing equipment 12.

[0027] For example, the first test unit 121 processes the test signal of the first chip under test 101, the second test unit 122 processes the test signal of the second chip under test 102, and the Nth test unit processes the test signal of the Nth chip under test 103. Here, N is a preset positive integer. In other words, when performing wafer testing on the wafer under test 10, the test signals of N chips under test on the wafer under test 10 can be processed simultaneously. In a non-limiting embodiment of the present invention, the value of N is 32.

[0028] Furthermore, connectors are used to connect to the chip under test (DUT) for testing. For example, the connectors can be connected to the corresponding DUT via probes. Different connectors are used to test different DUTs. For example, the first connector 111 is used to test the first DUT 101, the second connector 112 is used to test the second DUT 102, and the Nth connector 113 is used to test the Nth DUT 103. In other words, the first connector 111 is connected to the first DUT 101, the second connector 112 is connected to the second DUT 102, and the Nth connector 113 is connected to the Nth DUT 103.

[0029] Furthermore, each test unit is connected to a connector to obtain the test signal of the chip under test corresponding to that test unit from the connector. For example, the first test unit 121 is connected to the first connector 111 to obtain the test signal of the first chip under test 101, the second test unit 122 is connected to the second connector 112 to obtain the test signal of the second chip under test 102, and the Nth test unit 123 is connected to the Nth connector 113 to obtain the test signal of the Nth chip under test 103.

[0030] However, since the wiring between the connector and the test unit is usually done manually, wiring errors are prone to occur. If the wiring between the connector and the test unit is incorrect, the test unit cannot determine the condition of the chip under test corresponding to that test unit based on the acquired test signal. For example, the first test unit 121 is used to process the test signal of the first chip under test 101, but the first test unit 121 may be incorrectly connected to the second connector 112. Since the second connector 112 is connected to the second chip under test 102, the first test unit 121 will acquire the test signal of the second chip under test 102. Therefore, it cannot determine the condition of the first chip under test 101 based on the test signal acquired by the first test unit 121, resulting in disordered test results.

[0031] Therefore, there is an urgent need for a wiring inspection method for wafer testing equipment that can efficiently and accurately determine whether the wiring between the wafer testing equipment and the connector is correct.

[0032] To address this technical problem, this invention provides a wiring inspection method for a wafer testing device. In this embodiment, the wafer testing device is connected to multiple connectors. Since connectors testing different chips under test (DUTs) have different preset pin grounding states, the method detects the grounding state of each idle pin of the connector and compares it with the preset pin grounding state corresponding to the current DUT. If the detected grounding state matches the preset pin grounding state, it indicates that the connector is testing the current DUT, thus determining that the wiring between the connector and the wafer testing device is correct. Otherwise, it indicates that the connector is not testing the current DUT, thus determining that the wiring between the connector and the wafer testing device is incorrect. Therefore, the solution in this embodiment can efficiently and accurately determine whether the wiring between the wafer testing device and the connector is correct.

[0033] To make the above-mentioned objectives, features and beneficial effects of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to other accompanying drawings.

[0034] refer to Figure 2 , Figure 2 This diagram illustrates a wiring inspection method for a wafer testing device according to an embodiment of the present invention. The method can be executed by a wafer testing device, which can be any suitable terminal with data receiving and processing capabilities, such as a computer, a wafer tester, etc., but is not limited thereto. Figure 2 The wiring inspection method shown may include the following steps:

[0035] Step S201: Detect the grounding status of each idle pin of the connector connected to the wafer testing equipment, wherein the connectors used to test different chips under test have different preset pin grounding statuses;

[0036] Step S202: Compare the detected grounding state with the preset pin grounding state corresponding to the chip under test. If they are the same, determine that the wiring between the connector and the wafer testing equipment is correct. Otherwise, determine that the wiring between the connector and the wafer testing equipment is incorrect.

[0037] In a specific implementation of step S201, the wafer testing equipment can be connected to multiple connectors. For example, the wafer testing equipment and the connectors can be connected via ribbon cables. Each connector is connected to the chip under test (DUT), for example, the connector can be connected to the DUT via probes.

[0038] Each connector has multiple pins, and at least a portion of these pins are used when testing the wafer under test (DUT). In other words, at least a portion of the pins has a predefined purpose for electrically connecting to the pins of the chip under test (DUT), and these can be referred to as test pins. For example, pin number 72 on the connector is the reset pin, and pin number 76 is the clock signal line (SCL) pin. That is, at least a portion of the connector's pins (i.e., test pins) are connected to predefined pins on the DUT according to predefined test rules to obtain test signals from the DUT or to apply signals to the DUT. It should be noted that when testing multiple DUTs simultaneously, the test pins of the connectors used to test different DUTs can be the same.

[0039] Furthermore, for each connector, the grounding status of each idle pin of the connector is detected. The idle pins can be at least a portion of the pins that are not used when testing the chip under test. Specifically, the unused pins refer to pins that are not predefined when testing the chip under test; that is, the idle pins can be at least a portion of pins other than the test pins, and the idle pins are not electrically connected to the chip under test.

[0040] It should be noted that when performing parallel testing on multiple chips under test (DUTs), the unused pins of the connectors used to test different DUTs are usually the same. Specifically, the multiple DUTs being tested simultaneously can be of the same type (i.e., having the same pins and internal structure). When using a connector to test multiple DUTs, the connector's test pins are identical. Therefore, several pins other than the test pins can be pre-selected as unused pins. For example, for the multiple DUTs currently being tested, pins with pin codes PIN75, PIN77, PIN79, PIN81, PIN83, and PIN85 on the connector can be selected as unused pins.

[0041] The grounding state of the idle pins can be preset, meaning the grounding state of the idle pins of each connector can be predetermined (i.e., a preset pin grounding state). Therefore, for connectors used to test different chips under test (DUTs), the idle pins are the same, but the preset pin grounding states are different. Different connectors have different preset pin grounding states, thus allowing for differentiation between DUTs when multiple DUTs are tested simultaneously, and consequently, between connectors testing different DUTs. Therefore, under correct connection conditions, the grounding state of the detected idle pins of a connector can be used to determine which connector it is (i.e., which DUT it is used to test).

[0042] Furthermore, the wafer testing equipment may include a test box, to which the connector is connected. The test box can be used to detect the grounding status of each unused pin of the connector. That is, the test box can be any suitable testing equipment with open / short circuit testing capabilities.

[0043] Furthermore, when detecting the grounding state of each pin of the connector, the detected grounding state of each idle pin can be recorded in the test code. In other words, the grounding state of each idle pin can be represented by the test code.

[0044] Specifically, the test code may include multiple symbols. The number of symbols may be the same as the number of idle pins, and each symbol corresponds to an idle pin. The value of each symbol is used to describe the grounding state of the corresponding idle pin.

[0045] In a non-limiting embodiment of the present invention, the test code is a binary code, and the number of binary code symbols is the same as the number of idle pins. For each code symbol, if the idle pin corresponding to the code symbol is grounded, the code symbol is valued as 1; otherwise, the code symbol is valued as 0.

[0046] Furthermore, the wafer testing equipment can pre-store multiple preset pin ground states. More specifically, the connectors used to test different chips under test have different preset pin ground states.

[0047] The preset pin grounding state can be the preset grounding state of each idle pin. In the preset pin grounding state, at least a portion of the idle pins of the connector can be grounded.

[0048] Furthermore, the preset pin grounding state can be pre-recorded in a preset code. In other words, the wafer testing equipment pre-stores a preset code, which is used to describe the preset pin state of each idle pin. The preset pin state can include grounded and ungrounded.

[0049] Specifically, the preset code can include multiple code elements, each corresponding to a free pin. The value of each code element describes the preset grounding state of the corresponding free pin. Taking binary encoding as an example, if the code element value is 1, the preset grounding state of the free pin is grounded; if the code element value is 0, the preset grounding state of the free pin is not grounded.

[0050] Furthermore, the encoding type of the preset encoding and the encoding type of the test encoding are the same. For example, both the preset encoding and the test encoding are binary encodings.

[0051] In a non-limiting embodiment of the present invention, the wafer testing equipment can simultaneously test 32 chips under test (DUTs). Table 1 shows the preset codes of the connectors used to test these 32 DUTs. The idle pins are PIN75, PIN77, PIN79, PIN81, PIN83, and PIN85, and their serial numbers are the connector serial numbers. The preset codes are binary codes. For example, the preset code for connector number 2 is 100000, meaning that the preset grounding state of the idle pin PIN75 is grounded, and the preset grounding state of the other idle pins is not grounded.

[0052] Table 1

[0053]

[0054]

[0055] In the specific implementation of step S202, the detected grounding state is compared with the preset grounding state corresponding to the chip under test. If they are the same, it is determined that the wiring between the connector and the wafer testing equipment is correct; otherwise, it is determined that the wiring between the connector and the wafer testing equipment is incorrect.

[0056] Specifically, a wafer testing device may include multiple test units, which are used to process test signals from the chip under test (DUT). There is a correspondence between the test units and the DUT; for each test unit, the DUT corresponding to that unit is designated as the current DUT, and the connector used to test the current DUT has a preset pin grounding state.

[0057] Furthermore, the detected grounding state of the connector connected to the test unit is compared with the preset pin grounding state to determine whether the connector connected to the test unit is the connector used to test the chip under test. If so, the wiring between the test unit and the connector is determined to be correct; otherwise, the wiring between the test unit and the connector is determined to be incorrect.

[0058] More specifically, for each test unit, the chip under test corresponding to that test unit is denoted as the current chip under test. The connector used to test the current chip under test has a preset code. The test code of the connector connected to the test unit is compared with the preset code to determine whether the connector connected to the test unit is the connector used to test the current chip under test.

[0059] When comparing the test code with the preset code, if the value of any code element is different, it is determined that the test code and the preset code are different.

[0060] Therefore, in the solution of this embodiment of the invention, the wafer testing equipment is connected to multiple connectors. Since connectors testing different chips under test have different preset pin grounding states, the grounding state of each idle pin of the connector is detected, and then compared with the preset pin grounding state corresponding to the current chip under test. If the detected grounding state is the same as the preset pin grounding state, it indicates that the connector is testing the current chip under test, and thus it can be determined that the wiring between the connector and the wafer testing equipment is correct. Otherwise, it indicates that the connector is not testing the current chip under test, and thus it can be determined that the wiring between the connector and the wafer testing equipment is incorrect. Therefore, the solution in this embodiment of the invention can efficiently and accurately determine whether the wiring between the wafer testing equipment and the connector is correct.

[0061] refer to Figure 3 , Figure 3 This is a schematic diagram of a wiring inspection device for a wafer testing equipment according to an embodiment of the present invention. The device may include:

[0062] The detection module 31 can be used to detect the grounding status of each idle pin of the connector connected to the wafer testing equipment, wherein the connectors used to test different chips under test have different preset pin grounding statuses; the judgment module 32 can be used to compare whether the detected grounding status is the same as the preset pin grounding status corresponding to the current chip under test; if so, it is determined that the wiring between the connector and the wafer testing equipment is correct; otherwise, it is determined that the wiring between the connector and the wafer testing equipment is incorrect.

[0063] For more information on the working scenarios, working principles, working methods, and beneficial effects of the wiring inspection device for the aforementioned wafer testing equipment, please refer to the above information. Figure 1 and Figure 2 The relevant descriptions will not be repeated here.

[0064] This invention also discloses a storage medium, which is a computer-readable storage medium storing a computer program. When the computer program is executed, it can perform the steps of the wiring inspection method for the aforementioned wafer testing equipment. The storage medium may include ROM, RAM, a disk, or an optical disk, etc. The storage medium may also include non-volatile memory or non-transitory memory, etc.

[0065] This invention also discloses a wafer testing device, including a memory and a processor. The memory stores a computer program that can run on the processor. When the processor runs the computer program, it executes the steps of the above-described wiring inspection method for wafer testing devices.

[0066] The processor can be a central processing unit (CPU), or it can be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor. The memory can be volatile memory or non-volatile memory, or it can include both. Non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of random access memory (RAM) are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous linked dynamic random access memory (Synchlink DRAM, SLDRAM), and direct memory bus RAM (DR RAM).

[0067] This invention also discloses a wafer testing system, comprising: a plurality of connectors, wherein connectors for testing different chips under test have different preset pin grounding states; and a wafer testing device for connecting to at least a portion of the plurality of connectors. The wafer testing device can be used to perform... Figure 2The steps for checking the wiring of the wafer testing equipment are shown. For more information on the working scenarios, working principles, working methods, and beneficial effects of wafer testing systems, please refer to the above information. Figure 1 and Figure 2 The relevant descriptions will not be repeated here.

[0068] It should be understood that the term "and / or" in this article is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this article indicates that the preceding and following related objects have an "or" relationship.

[0069] In the embodiments of this application, "multiple" refers to two or more.

[0070] The descriptions of "first," "second," etc., appearing in the embodiments of this application are for illustrative purposes and to distinguish the objects being described. They have no order and do not indicate any special limitation on the number of devices in the embodiments of this application, nor do they constitute any limitation on the embodiments of this application.

[0071] In this application, the term "connection" refers to various connection methods, such as direct connection or indirect connection, to achieve communication between devices. This application does not impose any limitations on this.

[0072] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A wiring inspection method for a wafer testing device, characterized in that, The wafer testing equipment is simultaneously connected to multiple connectors, and the method includes: The grounding state of each idle pin of the connector connected to the wafer testing equipment is detected. The idle pins of the connectors used to test different chips under test have different preset pin grounding states, while the idle pins of the connectors used to test different chips under test are the same. The detected grounding state is compared with the preset pin grounding state corresponding to the chip under test. If they are the same, it is determined that the wiring between the connector and the wafer testing equipment is correct; otherwise, it is determined that the wiring between the connector and the wafer testing equipment is incorrect. The grounding status of each detected idle pin is recorded in the test code, and the preset pin grounding status of each idle pin is pre-recorded in the preset code.

2. The wiring inspection method for wafer testing equipment according to claim 1, characterized in that, In the preset pin grounding state, at least a portion of the free pins of the connector are grounded.

3. The wiring inspection method for wafer testing equipment according to claim 1, characterized in that, The wafer testing equipment and the connector are connected by a ribbon cable.

4. The wiring inspection method for wafer testing equipment according to claim 1, characterized in that, The wafer testing equipment includes a test box, and the connector is connected to the test box.

5. The wiring inspection method for wafer testing equipment according to claim 4, characterized in that, The grounding status of each idle pin of the connector is detected by the test box.

6. The wiring inspection method for wafer testing equipment according to claim 1, characterized in that, Both the test code and the preset code are binary codes.

7. The wiring inspection method for wafer testing equipment according to claim 6, characterized in that, The number of binary-coded symbols is the same as the number of idle pins.

8. A wiring inspection device for wafer testing equipment, characterized in that, The wafer testing equipment is simultaneously connected to multiple connectors, and the device includes: The detection module is used to detect the grounding status of each idle pin of the connector connected to the wafer testing equipment. The idle pins of the connector used to test different chips under test have different preset pin grounding statuses, while the idle pins of the connector used to test different chips under test are the same. The judgment module is used to compare whether the detected grounding state is the same as the preset pin grounding state corresponding to the chip under test; if so, it is determined that the wiring between the connector and the wafer testing equipment is correct; otherwise, it is determined that the wiring between the connector and the wafer testing equipment is incorrect. The grounding status of each detected idle pin is recorded in the test code, and the preset pin grounding status of each idle pin is pre-recorded in the preset code.

9. A storage medium having a computer program stored thereon, characterized in that, When the computer program is run by the processor, it performs the steps of the wiring inspection method for the wafer testing equipment according to any one of claims 1 to 7.

10. A wafer testing apparatus, comprising a memory and a processor, wherein the memory stores a computer program capable of running on the processor, characterized in that, When the processor runs the computer program, it performs the steps of the wiring inspection method for the wafer testing equipment according to any one of claims 1 to 7.

11. A wafer testing system, characterized in that, The system includes: Multiple connectors, wherein the connectors used to test different chips under test have different preset pin grounding states; The wafer testing equipment as claimed in claim 10 is used to connect to at least a portion of the plurality of connectors.

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