Interface device and radar based on srlo interface

Abstract

The application discloses an interface device based on an SRIO interface and a radar, and relates to the field of radar main control system hardware. The interface device comprises an FPGA programmable logic device, a receiving module, a sending module and a differential crystal oscillator, the FPGA programmable logic device is connected with a first interface of the receiving module, a first interface of the sending module and a first interface of the differential crystal oscillator respectively, the FPGA programmable logic device is used for data communication with an external computer through an SRIO interface, the receiving module is used for receiving external device information, and the sending module is used for sending information to external devices. The scheme adopts the FPGA as a core device, cooperates with a mature IP module and a self-developed logic module, supports conversion of a radar sub-system into an SRIO interface through an HDLC synchronous serial port, and realizes data communication with a single-board computer of a radar main control system.

Description

Technical Field

[0001] This invention relates to the field of radar main control system hardware, and in particular to an interface device and radar based on SRIO (Serial RapidIO). Background Technology

[0002] The core processing and control unit of the radar main control system is a general-purpose single-board computer. Currently, there are several VPX single-board computers on the market that conform to the VITA65 specification. However, most of the external interfaces of VPX single-board computers are general-purpose computer interfaces, such as USB, display, asynchronous serial port (UART), etc., and there is no synchronous serial port. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide an interface device and radar based on SRIO (Serial RapidIO) interface to address the shortcomings of the prior art.

[0004] The technical solution of the present invention to solve the above-mentioned technical problems is as follows:

[0005] An interface device based on an SRIO interface includes: an FPGA programmable logic controller, a receiving module, a transmitting module, and a differential crystal oscillator;

[0006] The FPGA programmable logic device is connected to the first interface of the receiving module, the first interface of the transmitting module, and the first interface of the differential crystal oscillator, respectively.

[0007] The FPGA programmable logic device is used to communicate data with an external computer via the SRIO interface.

[0008] The receiving module is used to receive HDLC (High Level Data Link Communication) information from an external device, wherein the information may include: the external device clock and data synchronized with the external device clock;

[0009] The transmitting module is used to send HDLC information (transmit clock and data synchronized with the transmit clock) to external devices.

[0010] The beneficial effects of this invention are: This solution uses FPGA as the core device, combined with mature IP (Intelligent Property) modules and self-developed logic modules, to support the radar subsystem in converting the HDLC synchronous serial port to an SRIO interface and realizing data communication with the single-board computer of the radar main control system.

[0011] Furthermore, the FPGA programmable logic device includes:

[0012] SRIO IP module, SWRITE transaction module, HDLC register configuration module, transmit FIFO module, HDLC transmit module, HDLC receive module, receive FIFO module, and NREAD transaction module;

[0013] The first interface of the SRIO IP module is sequentially connected to the SWRITE transaction module, the HDLC register configuration module, the HDLC transmission module, and the transmission FIFO module;

[0014] The second interface of the SRIO IP module is sequentially connected to the NREAD transaction module, the receive FIFO module, and the HDLC receive module;

[0015] The FPGA programmable logic device is specifically used for data communication with an external computer through the SRIO IP module;

[0016] The SRIO IP module is connected to the first interface of the differential crystal oscillator;

[0017] The sending FIFO module is connected to the first interface of the sending module;

[0018] The HDLC receiving module is connected to the first interface of the receiving module.

[0019] Furthermore, the external computer includes a single-board computer for the radar main control system.

[0020] Furthermore, the FPGA programmable logic device includes a chip with the model number JFM7K325T.

[0021] Furthermore, the receiving module includes a chip with the model number SM3096.

[0022] Furthermore, the transmitting module includes a chip with the model number SM3030.

[0023] Furthermore, the power module includes a chip with the model number SM4644MPY;

[0024] Furthermore, the differential crystal oscillator includes a differential crystal oscillator frequency of 125MHz;

[0025] Furthermore, it also includes a power supply module, which is connected to the power interface of the FPGA programmable logic device, the power interface of the receiving module, the power interface of the transmitting module, and the power interface of the differential crystal oscillator.

[0026] Furthermore, the HDLC register configuration module is also connected to the transmit FIFO module.

[0027] The advantages of additional aspects of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. Attached Figure Description

[0028] Figure 1 A flowchart illustrating an interface device based on an SRIO interface, provided for an embodiment of the present invention;

[0029] Figure 2 A schematic diagram of an interface board based on an SRIO interface is provided for other embodiments of the present invention;

[0030] Figure 3 A schematic diagram of the internal structure of an FPGA provided for an embodiment of the present invention. Detailed Implementation

[0031] The principles and features of the present invention are described below with reference to the accompanying drawings. The embodiments described are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0032] like Figure 1 As shown, an interface device based on an SRIO interface provided in an embodiment of the present invention includes: an FPGA programmable logic controller 1101, a receiving module 1102, a transmitting module 1103, and a differential crystal oscillator 1104.

[0033] The FPGA programmable logic device 1101 is connected to the first interface of the receiving module, the first interface of the transmitting module, and the first interface of the differential crystal oscillator, respectively.

[0034] The FPGA programmable logic device 1101 is used to communicate data with an external computer via the SRIO interface.

[0035] The receiving module 1102 is used to receive information from external devices;

[0036] The sending module 1103 is used to send information to external devices.

[0037] Optionally, in one of the above embodiments, such as Figure 2As shown, an interface board based on SRIO (Serial RapidIO) interface uses a domestically produced FPGA programmable logic controller as the core processor, model JFM7K325T. The external supporting circuits include a domestically produced RS422 receiver chip, model SM3096; an RS422 transmitter chip, model SM3030; a differential crystal oscillator with a frequency of 125MHz; and a domestically produced power supply chip, model SM4644MPY.

[0038] This solution uses FPGA as the core device, along with mature IP modules and self-developed logic modules, to support the radar subsystem in communicating with the radar main control system's single-board computer via HDLC synchronous serial port to SRIO interface.

[0039] Optionally, in one of the above embodiments, the FPGA programmable logic device 1101 includes:

[0040] SRIO IP module, SWRITE transaction module, HDLC register configuration module, transmit FIFO module, HDLC transmit module, HDLC receive module, receive FIFO module, and NREAD transaction module;

[0041] The first interface of the SRIO IP module is sequentially connected to the SWRITE transaction module, the HDLC register configuration module, the HDLC transmission module, and the transmission FIFO module;

[0042] The HDLC register configuration module is also connected to the transmit FIFO module;

[0043] The second interface of the SRIO IP module is sequentially connected to the NREAD transaction module, the receive FIFO module, and the HDLC receive module;

[0044] The FPGA programmable logic device is specifically used for data communication with an external computer through the SRIO IP module;

[0045] The SRIO IP module is connected to the first interface of the differential crystal oscillator;

[0046] The sending FIFO module is connected to the first interface of the sending module;

[0047] The HDLC receiving module is connected to the first interface of the receiving module. Optionally, in one embodiment, as shown... Figure 3 As shown, the FPGA internally implements the following logic modules, and the data flow is as follows:

[0048] The SRIO IP used is Xilinx's "Serial RapidIO Gen2 (version 4.0)" integrated into the Vivado 2016.4 FPGA development environment. This IP is instantiated as an SRIO IP interface module with a transmission frequency of 3.125 GHz. The SRIO IP's reference clock comes from a 125 MHz differential crystal oscillator. The SRIO IP interface module can respond to SRIOIO logic operations including SWRITE (write to non-shared memory) and NREAD (read from non-shared memory). SRIOIO logic operations are sent or received in "data packet" format, with a data width of 64 bits.

[0049] The single-board computer sends a "write transaction data packet" to the SWRITE transaction module via SRIO IP. The data packet is formatted as "write data packet header" + "write data area". The "write data packet header" contains the "write address", "write data length", and "write data address", while the "write data area" contains the data sent by the SWRITE transaction.

[0050] The SWRITE transaction module is used to parse logical operation transactions from SRIO IP and receive the data in the "write data packet header" + "data area" of the "write transaction data packet" from the SRIO IP interface;

[0051] The HDLC register configuration module receives the "write data packet header" + "data area" data from the SWRITE transaction module. Based on the "write address" in the corresponding "write data packet header", it distinguishes whether the currently received "write transaction data packet" is data to be output to the HDLC sending module or data to be output to the sending FIFO module.

[0052] If the HDLC register configuration module receives data that is output to the HDLC transmitting module, then the HDLC register configuration module outputs data to the HDLC transmitting module. Based on the received data, the HDLC transmitting module performs the following functions, including configuring the transmitting synchronization clock frequency of the HDLC transmitting module, setting the number of bytes of transmitted data, and outputting a reset signal to the transmitting FIFO module.

[0053] If the HDLC register configuration module receives data that is to be output to the transmit FIFO module, then the HDLC register configuration module outputs data to the transmit FIFO module.

[0054] The transmitting FIFO module converts the received 64-bit data from parallel data to serial data. Following the HDLC transmission format, it adds the frame flag code "01111110" (0x7E) at the beginning and end of the serial data before outputting it to the RS422 transmitting chip. The HDLC receiving module monitors the serial data from the RS422 transmitting chip. When the monitored serial data contains the HDLC frame flag code "01111110" (0x7E), it indicates that a frame of HDLC data has been received. It then converts the serial data following the frame flag code from serial data to parallel data, converting it into continuous 64-bit data, and outputs it to the receiving FIFO module. The HDLC receiving module also records the number of received 64-bit data segments and sets the received data flag to logic "1," outputting it to the receiving FIFO module.

[0055] The receive FIFO module is used to buffer the 64-bit data output by the HDLC receive module, the number of 64-bit data outputs by the HDLC receive module, and the receive data flags output by the HDLC receive module.

[0056] The single-board computer sends a "read request packet" for the NREAD transaction to the NREAD transaction module through SRIO IP. The packet format is a "read packet header", which contains the "read address", "read data length", and "read data address".

[0057] The NREAD transaction module responds to the "read packet header" from the SRIO IP, distinguishing the required function based on the "read address". If the function of the "read address" is to read the receive data flag and the number of received 64-bit data from the receive FIFO module, the NREAD transaction module reads the number of 64-bit data and the receive data flag buffered in the FIFO module, encapsulates them into a "read response packet", and outputs it to the SRIO IP. The SRIO IP then outputs this "read response packet" to the single-board computer. If the function of the "read address" is to read the 64-bit data buffered in the FIFO module, the NREAD transaction module reads the 64-bit data buffered in the FIFO module, encapsulates it into a "read response packet", and outputs it to the SRIO IP. The SRIO IP then outputs this "read response packet" to the single-board computer.

[0058] Optionally, in one of the above embodiments, the external computer includes: a single-board computer of the radar main control system.

[0059] Optionally, in one of the above embodiments, the FPGA programmable logic device 1101 includes a chip of model JFM7K325T.

[0060] Optionally, in one of the above embodiments, the receiving module includes a chip of model SM3096.

[0061] Optionally, in one of the above embodiments, the transmitting module includes a chip of model SM3030.

[0062] Optionally, in one of the above embodiments, the power module includes a chip with the model number SM4644MPY.

[0063] Optionally, in one of the above embodiments, the differential crystal oscillator includes a differential crystal oscillator frequency of 125MHz.

[0064] Optionally, in one of the above embodiments, it further includes a power module 1105, which is connected to the power interface of the FPGA programmable logic device 1101, the power interface of the receiving module 1102, the power interface of the transmitting module 1103, and the power interface of the differential crystal oscillator 1104.

[0065] Readers should understand that in the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0066] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the method embodiments described above are merely illustrative. For instance, the division of steps is only a logical functional division, and there may be other division methods in actual implementation. For example, multiple steps may be combined or integrated into another step, or some features may be ignored or not executed.

[0067] If the above methods are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this invention, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0068] The above are merely specific embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and these modifications or substitutions should all be covered within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. An interface device based on SRIO interface, characterized in that, It comprises an FPGA programmable logic device, a receiving module, a sending module and a differential crystal oscillator. The FPGA programmable logic device is connected with a first interface of the receiving module, a first interface of the sending module and a first interface of the differential crystal oscillator respectively. The FPGA programmable logic device is configured to communicate data with an external computer through an SRIO interface. The receiving module is configured to receive external device information. The sending module is configured to send information to an external device. The FPGA programmable logic device comprises: An SRIO IP module, an SWRITE transaction module, an HDLC register configuration module, a sending FIFO module, an HDLC sending module, an HDLC receiving module, a receiving FIFO module and an NREAD transaction module. A first interface of the SRIO IP module is connected with the SWRITE transaction module, the HDLC register configuration module, the HDLC sending module and the sending FIFO module in sequence. A second interface of the SRIO IP module is connected with the NREAD transaction module, the receiving FIFO module and the HDLC receiving module in sequence. The FPGA programmable logic device is configured to communicate data with an external computer through the SRIO IP module. The SRIO IP module is connected with a first interface of the differential crystal oscillator. The sending FIFO module is connected with a first interface of the sending module. The HDLC receiving module is connected with a first interface of the receiving module, receives a write data packet header and data from the SWRITE transaction module, and distinguishes whether the current received write transaction data packet is data output to the HDLC sending module or data output to the sending FIFO module according to a write address in the corresponding write data packet header. The differential crystal oscillator has a frequency of 125MHz, a reference clock of the SRIO IP module comes from the differential crystal oscillator with a frequency of 125MHz, and SRIO IO logic operation transactions responded by the SRIO IP module include SWRITE transactions and NREAD transactions.

2. The interface device based on SRIO interface according to claim 1, characterized in that, The external computer comprises a single board computer of a radar master control system.

3. The interface device based on SRIO interface according to claim 1, characterized in that, The FPGA programmable logic device comprises a JFM7K325T chip.

4. The interface device based on SRIO interface according to claim 1, characterized in that, The receiving module comprises a chip with a model of SM3096.

5. The interface device based on SRIO interface according to claim 1, characterized in that, The sending module comprises a chip with a model of SM3030.

6. The interface device based on SRIO interface according to claim 1, characterized in that, Further comprising: A power module comprising a chip with a model of SM4644.

7. The interface device based on SRIO interface according to claim 1, characterized in that, Further comprising: A power module connected with a power interface of the FPGA programmable logic device, a power interface of the receiving module, a power interface of the sending module and a power interface of the differential crystal oscillator respectively.

8. The interface device based on SRIO interface according to claim 1, characterized in that, Further comprising: The HDLC register configuration module is further connected with the sending FIFO module.

9. A radar, characterized by An interface device based on an SRIO interface according to any one of claims 1 to 8.

Images