Data transmission circuit, method and storage device

Abstract

The present application relates to a data transmission circuit, method and storage device. In the circuit: an encoding module is used to generate check code data according to first data on a first data line; a comparison module is used to compare the first data with second data on a second data line and output a comparison result indicating whether the number of bits where the first data is different from the second data exceeds a preset threshold; a buffer module is used to transmit the first data or the opposite data of the first data to the second data line according to the comparison result; the buffer module is further used to transmit the check code data to the second data line; a first read / write conversion unit is used to transmit the first data or the opposite data of the first data transmitted to the second data line to a third data line according to the comparison result; a second read / write conversion unit is used to transmit the check code data to the third data line. The present application reduces the power consumption during the data writing transmission process.

Description

Technical Field

[0001] This application relates to the field of semiconductor storage technologies, and particularly to a data transmission circuit, method, and storage device. Background Art

[0002] With the rapid development of semiconductor technologies, the density and quantity of memory cells in the memory cell array of semiconductor storage devices have been continuously increasing to meet the market's demand for the storage capacity of semiconductor storage devices. As a result, the width and length of the data transmission path for the data written to the storage array area have increased, leading to a significant increase in the power consumption of the data transmission path between the data pad and the storage array area; moreover, the increase in the data transmission path will increase the probability of anomalies occurring during data transmission, resulting in a decrease in the accuracy of data transmission.

[0003] How to reduce the power consumption of the data written to the storage array area during data transmission and improve the accuracy of the data written to the storage array area without reducing the density and quantity of the memory cells in the semiconductor memory cell array has become one of the technical problems that urgently need to be solved in the process of further improving the energy-saving performance and storage performance of semiconductor storage devices. Summary of the Invention

[0004] Based on this, in view of the technical problems in the above background art, it is necessary to provide a data transmission circuit, method, and storage device that, without reducing the density and quantity of the memory cells in the memory cell array, can reduce the power consumption of the data written to the storage array area during data transmission while improving the accuracy of the data written to the storage array area, so as to further improve the energy-saving performance and storage performance of semiconductor storage devices.

[0005] To achieve the above and other objects, a first aspect of the present application provides a data transmission circuit, including an encoding module, a comparison module, a buffer module, a first read / write conversion unit, and a second read / write conversion unit. The encoding module is configured to generate checksum data based on the first data on the first data line. The comparison module is configured to receive the first data on the first data line and the second data on the second data line, and compare the first data and the second data to output a comparison result indicating whether the number of bits in which the first data and the second data are different exceeds a preset threshold, wherein the first data and the second data have the same preset bit width. The buffer module is electrically connected to the first data line, the comparison module, the encoding module, and the second data line, and is configured to, when the comparison result exceeds the preset threshold, transmit the inverted data of the first data to the second data line, and when the comparison result does not exceed the preset threshold, transmit the first data to the second data line. The buffer module is further configured to transmit the checksum data to the second data line. The first read / write conversion unit is electrically connected to the second data line and the third data line, and is configured to, when the comparison result exceeds the preset threshold, invert the inverted data of the first data transmitted to the second data line and then transmit it to the third data line, and when the comparison result does not exceed the preset threshold, transmit the first data transmitted to the second data line to the third data line. The second read / write conversion unit is electrically connected to the second data line and the third data line, and is configured to transmit the checksum data on the second data line to the third data line. Wherein, the transmission path between the buffer module and the first read / write conversion unit has a first length, the transmission path between the buffer module and the second read / write conversion unit has a second length, and the first length is not less than the second length.

[0006] In the data transmission circuit of the above embodiments, by setting an encoding module to generate check code data according to the first data on the first data line, it is convenient to perform error detection and / or error correction on the data in the storage array area based on the check code data later, thereby improving the accuracy of the stored data; by a comparison module, the first data on the first data line and the second data on the second data line are compared to output a comparison result indicating whether the number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; then, when the comparison result exceeds the preset threshold, a buffer module is used to transmit the inverted data of the first data to the second data line, and when the comparison result does not exceed the preset threshold, the first data is transmitted to the second data line, wherein the buffer module is further used to transmit the check code data to the second data line; such that the first read / write conversion unit can, when the comparison result exceeds the preset threshold, invert the inverted data of the first data transmitted to the second data line and then transmit it to the third data line, and when the comparison result does not exceed the preset threshold, transmit the first data transmitted to the second data line to the third data line, so as to restore the first data flipped on the second data line, and at the same time use the second read / write conversion unit to transmit the check code data on the second data line to the third data line, so as to perform error detection and / or error correction on the data on the third data line based on the check code data, thereby improving the accuracy of the written data. By setting the length of the transmission path between the buffer module and the first read / write conversion unit to be not less than the length of the transmission path between the buffer module and the second read / write conversion unit, the writing path length of the check code data is reduced, and the writing time of the check code data is shortened, thereby compensating for the time spent in generating the check code data, enabling the data and the check code to complete the writing operation asynchronously as possible, and improving the writing speed. Since the transmitted data generally includes a data string composed of 0s and 1s, by applying a power-saving algorithm in the process of writing data transmission, without changing the writing data transmission path, the number of flips of the data written into the storage device during transmission is reduced, effectively reducing the power consumption during the transmission of the write data. In this embodiment, without reducing the density and quantity of the storage units in the storage unit array, while reducing the power consumption of the data written into the storage array area during data transmission, the accuracy of the data written into the storage array area is improved, which can further improve the energy-saving performance and storage performance of the semiconductor storage device.

[0007] In one embodiment, the buffer module includes a data conversion module and a data bus buffer module; the data conversion module is electrically connected to the first data line, the comparison module, and the data bus buffer module, and is configured to transmit the inverted data of the first data to the data bus buffer module when the comparison result exceeds a preset threshold, and transmit the first data to the data bus buffer module when the comparison result does not exceed the preset threshold; the data bus buffer module is electrically connected to the encoding module, the data conversion module, the comparison module, and the second data line, and is configured to generate a data polarity identification signal according to the comparison result, and is further configured to transmit the first data or the inverted data of the first data to the second data line.

[0008] In one embodiment, the preset threshold is half of the preset bit width; the comparison module includes a comparison unit and a status identification unit. The comparison unit is configured to perform a bit-by-bit comparison on the first data on the first data line and the second data on the second data line, and output the comparison status data of each bit; the status identification unit is electrically connected to the comparison unit and the data conversion module, and is configured to count the comparison status data of each bit and generate the comparison result according to the statistical result.

[0009] In one embodiment, the data conversion module includes a first transmission unit, a first inverting unit, a second transmission unit, and a second inverting unit. The first transmission unit is electrically connected to the first data line, the data bus buffer module, and the output end of the status identification unit through the first inverting unit, and is configured to transmit the first data on the first data line to the data bus buffer module when the comparison result does not exceed the preset threshold; the second transmission unit is electrically connected to the data bus buffer module, the output end of the status identification unit, and the first data line through the second inverting unit, and is configured to transmit the inverted data of the first data to the data bus buffer module when the comparison result exceeds the preset threshold.

[0010] In one embodiment, the first read-write conversion unit includes a read-write conversion circuit. The read-write conversion circuit is electrically connected to both the second data line and the third data line, and is configured to, when the comparison result exceeds a preset threshold, invert the opposite data of the first data transmitted to the second data line and then transmit it to the third data line, and when the comparison result does not exceed the preset threshold, transmit the first data transmitted to the second data line to the third data line. In one embodiment, the second data line includes a global data line and a complementary global data line, and the global data line and the complementary global data line transmit signals that are in opposite phases; the third data line includes a local data line and a complementary local data line, and the local data line and the complementary local data line transmit signals that are in opposite phases; the step of inverting the opposite data of the first data transmitted to the second data line and then transmitting it to the third data line includes: inverting the opposite data of the first data transmitted to the global data line and then transmitting it to the local data line; the step of transmitting the first data transmitted to the second data line to the third data line includes: transmitting the first data transmitted to the global data line to the local data line.

[0011] In one embodiment, the read-write conversion circuit includes a write enable module and a write driver circuit. The write enable module generates a write enable signal and a write enable inverse signal according to the data polarity identification signal and the initial write enable signal; the write driver circuit is configured to generate a third data according to the write enable signal, the write enable inverse signal, and the first data or the opposite data of the first data transmitted to the second data line, and transmit the third data to the third data line.

[0012] In one embodiment, the write enable module includes a first inverter, a first nor gate, a second inverter, and a second nor gate. The first inverter is configured to: have its input terminal electrically connected to the initial write enable signal and its output terminal output a first write enable inverse signal; the first nor gate is configured to: have its input terminals electrically connected to the data polarity identification signal and the output terminal of the first inverter, and its output terminal output a write enable signal; the second inverter is configured to: have its input terminal electrically connected to the data polarity identification signal and its output terminal output a data polarity identification inverse signal; the second nor gate is configured to: have its input terminals electrically connected to the output terminal of the second inverter and the output terminal of the first inverter, and its output terminal output a write enable inverse signal.

[0013] In one embodiment, the write driving circuit includes a first switch unit, a second switch unit, a third switch unit, and a fourth switch unit. The first switch unit is configured to electrically connect the local data line and the global data line according to the write enable signal; the second switch unit is configured to electrically connect the local data line and the complementary global data line according to the inverted write enable signal; the third switch unit is configured to electrically connect the complementary local data line and the global data line according to the inverted write enable signal; and the fourth switch unit is configured to electrically connect the complementary local data line and the complementary global data line according to the write enable signal.

[0014] In one embodiment, the read / write conversion circuit further includes a read driving circuit. The read driving circuit includes a fifth switch unit, a sixth switch unit, a seventh switch unit, and an eighth switch unit. The control terminal of the fifth switch unit is electrically connected to the local data line and is configured to electrically connect the complementary global data line and the first node according to a control terminal signal; the sixth switch unit is configured to electrically connect the first node and the ground terminal according to the read enable signal; the control terminal of the seventh switch unit is electrically connected to the complementary local data line and is configured to electrically connect the global data line and the second node according to a control terminal signal; and the eighth switch unit is configured to electrically connect the second node and the ground terminal according to the read enable signal.

[0015] In one embodiment, the data transmission circuit further includes a read unit and a correction module. The read unit is electrically connected to the second data line and is configured to read the second data and the check code data on the second data line; the correction module is electrically connected to both the first data line and the read unit and is configured to receive the second data and the check code data on the second data line, and perform error detection and / or error correction on the second data according to the check code data to generate corrected data, so as to transmit the corrected data to the first data line.

[0016] In one embodiment, the encoding module includes an ECC encoding unit.

[0017] A second aspect of the present application provides a storage device, including the data transmission circuit in any embodiment of the present application, configured to store and transmit data for read operations or write operations.

[0018] A third aspect of the present application provides a data transmission method, including:

[0019] Generating check code data according to first data on a first data line;

[0020] Comparing the first data on the first data line with second data on a second data line to output a comparison result indicating whether the number of bits in which the first data and the second data are different exceeds a preset threshold, where the first data and the second data have the same preset bit width;

[0021] The control buffer module transmits the opposite data of the first data to the second data line when the comparison result exceeds a preset threshold, and transmits the first data to the second data line when the comparison result does not exceed the preset threshold; wherein, the buffer module is further configured to transmit the check code data to the second data line;

[0022] Control the first read / write conversion unit to invert the opposite data of the first data transmitted to the second data line and then transmit it to the third data line when the comparison result exceeds a preset threshold, and transmit the first data transmitted to the second data line to the third data line when the comparison result does not exceed the preset threshold; and control the second read / write conversion unit to transmit the check code data on the second data line to the third data line; wherein, the transmission path between the buffer module and the first read / write conversion unit has a first length, the transmission path between the buffer module and the second read / write conversion unit has a second length, and the first length is not less than the second length.

[0023] In one embodiment, the preset threshold is half of the preset bit width; the method further includes:

[0024] Receive the second data and the check code data on the second data line, perform error detection and / or error correction on the second data according to the check code data, generate corrected data, and transmit the corrected data to the first data line. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1 It is a schematic circuit diagram of a data transmission circuit provided in the first embodiment of the present application;

[0027] Figure 2 It is a schematic circuit diagram of a data transmission circuit provided in the second embodiment of the present application;

[0028] Figure 3 It is a schematic circuit diagram of a data transmission circuit provided in the third embodiment of the present application;

[0029] Figure 4aSchematic diagram of the circuit principle of a data transmission circuit provided in the fourth embodiment of the present application;

[0030] Figure 4b is Figure 4a a schematic diagram of an implementation manner;

[0031] Figure 5 Schematic diagram of the circuit principle of a data transmission circuit provided in the fifth embodiment of the present application;

[0032] Figure 6 Schematic diagram of the circuit principle of a data transmission circuit provided in the sixth embodiment of the present application;

[0033] Figure 7 Schematic diagram of the circuit of a write enable module in a data transmission circuit provided in an embodiment of the present application;

[0034] Figure 8 Schematic diagram of the circuit of a write driving circuit in a data transmission circuit provided in an embodiment of the present application;

[0035] Figure 9 Schematic diagram of the circuit principle of a data transmission circuit provided in the seventh embodiment of the present application;

[0036] Figure 10 Schematic diagram of the flow of a data transmission method provided in an embodiment of the present application;

[0037] Figure 11 Schematic diagram of the flow of a data transmission method provided in another embodiment of the present application.

[0038] Description of reference numerals:

[0039] 100. Transmission circuit; 10. Comparison module; 20. Buffer module; 30. First data line; 31. Encoding module; 40. Second data line; 41. Global data line; 42. Complementary global data line; 51. First read / write conversion unit; 52. Second read / write conversion unit; 60. Third data line; 61. Local data line; 62. Complementary local data line; 11. Comparison unit; 12. Status recognition unit; 21. Data conversion module; 22. Data bus buffer module; 211. First transmission unit; 212. First inverter unit; 213. Second transmission unit; 214. Second inverter unit; 511. Read / write conversion circuit; 5111. Write enable module; 5112. Write drive circuit; 5113. Read drive circuit; 51121. First switch unit; 51122. Second switch unit; 51123. Third switch unit; 51124. Fourth switch unit; 51131. Fifth switch unit; 51132. Sixth switch unit; 51133. Seventh switch unit; 51134. Eighth switch unit; 70. Read unit; 80. Correction module. Detailed implementation manners

[0040] For ease of understanding of this application, the following will describe this application more comprehensively with reference to the relevant drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used in the description of this application in this specification are only for the purpose of describing specific embodiments and are not intended to limit this application. Additionally, certain terms used throughout the specification and the following claims refer to specific elements. Those skilled in the art will understand that manufacturers may use different names to refer to elements. This document does not intend to distinguish between elements that have different names but the same function. In the following description and embodiments, the terms "comprising" and "including" are used in an open-ended manner and should be interpreted as "including, but not limited to...". Similarly, the term "connected" is intended to express an indirect or direct electrical connection. Accordingly, if a device is connected to another device, the connection can be accomplished through a direct electrical connection or through an indirect electrical connection via other devices and connectors.

[0042] It should be understood that although terms such as "first" and "second" may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present application, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0043] Please refer to Figure 1 , in an embodiment of the present application, a data transmission circuit 100 is provided, including a comparison module 10, a buffer module 20, an encoding module 31, a first read / write conversion unit 51, and a second read / write conversion unit 52. The encoding module 31 is configured to generate check code data Check_data1 according to the first data on the first data line 30; the comparison module 10 is configured to receive the first data on the first data line 30 and the second data on the second data line 40, and compare the first data and the second data to output a comparison result indicating whether the number of different bits between the first data and the second data exceeds a preset threshold, where the first data and the second data have the same preset bit width; the buffer module 20 is electrically connected to the first data line 30, the comparison module 10, the encoding module 31, and the second data line 40, and is configured to transmit the opposite data of the first data to the second data line 40 when the comparison result exceeds the preset threshold, and transmit the first data to the second data line 40 when the comparison result does not exceed the preset threshold; the buffer module 20 is further configured to transmit the check code data Check_data1 to the second data line 40; the first read / write conversion unit 51 is electrically connected to the second data line 40 and the third data line 60, and is configured to invert and then transmit the opposite data of the first data transmitted to the second data line 40 to the third data line 60 when the comparison result exceeds the preset threshold, and transmit the first data transmitted to the second data line 40 to the third data line 60 when the comparison result does not exceed the preset threshold; the second read / write conversion unit 52 is electrically connected to the second data line 40 and the third data line 60, and is configured to transmit the check code data Check_data2 on the second data line 40 to the third data line 60; wherein, the transmission path between the buffer module 20 and the first read / write conversion unit 51 has a first length L1, and the transmission path between the buffer module 20 and the second read / write conversion unit 52 has a second length L2, and L1≥L2.

[0044] As an example, please continue to refer to Figure 1, by setting the encoding module 31 to generate check code data Check_data1 based on the first data on the first data line 30, it is convenient to perform error detection and / or error correction on the data in the storage array area according to the check code data Check_data1 later, improving the accuracy of the stored data; by using the comparison module 10 to compare the first data on the first data line 30 with the second data on the second data line 40 to output a comparison result indicating whether the number of different bits between the first data and the second data exceeds a preset threshold, where the first data and the second data have the same preset bit width; then using the buffer module 20 to transmit the inverted data of the first data to the second data line 40 when the comparison result exceeds the preset threshold, and transmit the first data to the second data line 40 when the comparison result does not exceed the preset threshold, where the buffer module 20 is also used to transmit the check code data Check_data1 to the second data line 40; enabling the first read / write conversion unit 51 to invert and then transmit the inverted data of the first data transmitted to the second data line 40 to the third data line 60 when the comparison result exceeds the preset threshold, and transmit the first data transmitted to the second data line 40 to the third data line 60 when the comparison result does not exceed the preset threshold, to restore the first data flipped on the second data line 40, and at the same time using the second read / write conversion unit 52 to transmit the check code data Check_data2 on the second data line 40 to the third data line 60, so as to perform error detection and / or error correction on the data on the third data line 60 according to the check code data Check_data2, improving the accuracy of writing data to the storage array area. The check code data Check_data1 and the check code data Check_data2 can be the same or satisfy a preset algorithm. By setting the length L1 of the transmission path between the buffer module 20 and the first read / write conversion unit 51 to be not less than the length L2 of the transmission path between the buffer module 20 and the second read / write conversion unit 52, it is convenient to perform error detection and / or error correction on the read data at a position close to the data pad, improving the accuracy of reading data from the storage device. Since the transmitted data generally includes a data string composed of 0s and 1s, by applying a power-saving algorithm during the process of writing data transmission, the number of flips of the data written into the storage device during transmission is reduced without changing the writing data transmission path, effectively reducing the power consumption during the transmission of write data. In this embodiment, without reducing the density and quantity of the storage units in the storage cell array, while reducing the power consumption of the data written into the storage array area during data transmission, the accuracy of writing data to the storage array area is improved, which can further improve the energy-saving performance and storage performance of the semiconductor storage device.

[0045] As an example, please continue to refer to Figure 1, in an embodiment of the present application, it may be set that the encoding module 31 includes an ECC encoding unit, and the ECC encoding unit is used to generate ECC check code data according to the first data on the first data line 30, so as to facilitate subsequent error detection and / or error correction of the data in the storage array area according to the ECC check code data, and improve the accuracy of the stored data.

[0046] It should be noted that the second data on the second data line described in the present application does not include the check code data on the second data line.

[0047] Furthermore, please refer to Figure 2 , in an embodiment of the present application, the buffer module 20 includes a data conversion module 21 and a data bus buffer module 22; the data conversion module 21 is electrically connected to the first data line 30, the comparison module 10, and the data bus buffer module 22, and is used to transmit the opposite data of the first data on the first data line 30 to the data bus buffer module 22 when the comparison result exceeds a preset threshold, and transmit the first data on the first data line 30 to the data bus buffer module 22 when the comparison result does not exceed the preset threshold; the data bus buffer module 22 is electrically connected to the encoding module 31, the data conversion module 21, the comparison module 10, and the second data line 40, and is used to generate a data polarity identification signal pl according to the comparison result, and is also used to transmit the first data or the opposite data of the first data to the second data line 40. It is convenient to restore the flipped data according to the data polarity identification signal pl subsequently to ensure the accuracy of data transmission.

[0048] Furthermore, please refer to Figure 3 , in an embodiment of the present application, it may be set that the preset threshold is half of the preset bit width; wherein, the comparison module 10 includes a comparison unit 11 and a status recognition unit 12, the comparison unit 11 is used to perform a bit-by-bit comparison of the first data on the first data line 30 and the second data on the second data line 40, and output the comparison status data of each bit; the status recognition unit 12 is electrically connected to the comparison unit 11 and the data conversion module 21, and is used to count the comparison status data of each bit and generate a comparison result according to the statistical result, so that the data conversion module 21 transmits the opposite data of the first data on the first data line 30 to the data bus buffer module 22 when the comparison result exceeds the preset threshold, and transmits the first data on the first data line 30 to the data bus buffer module 22 when the comparison result does not exceed the preset threshold, reducing the number of data flips on the premise of ensuring the data transmission accuracy, so as to effectively reduce the power consumption during the data transmission process.

[0049] Furthermore, please refer to Figure 4a and Figure 4b, in an embodiment of the present application, the data conversion module 21 includes a first transmission unit 211, a first inverting unit 212, a second transmission unit 213, and a second inverting unit 214. The first transmission unit 211 is electrically connected to the first data line 30, the data bus buffer module 22, and is electrically connected to the output end of the status recognition unit 12 through the first inverting unit 212, and is used for transmitting the first data on the first data line 30 to the data bus buffer module 22 when the comparison result does not exceed the preset threshold; the second transmission unit 213 is electrically connected to the data bus buffer module 22, the output end of the status recognition unit 12, and is electrically connected to the first data line 30 through the second inverting unit 214, and is used for transmitting the inverted data of the first data to the data bus buffer module 22 when the comparison result exceeds the preset threshold. This embodiment reduces the number of write data flips on the premise of ensuring the transmission accuracy of the write data, and can effectively reduce the power consumption of the write data during the transmission process.

[0050] Further, please refer to Figure 5 , in an embodiment of the present application, the first read / write conversion unit 51 includes a read / write conversion circuit 511. The read / write conversion circuit 511 is electrically connected to both the second data line 40 and the third data line 60, and is used for inverting the inverted data of the first data transmitted to the second data line 40 and then transmitting it to the third data line 60 when the comparison result exceeds the preset threshold, and transmitting the first data transmitted to the second data line 40 to the third data line 60 when the comparison result does not exceed the preset threshold.

[0051] Further, please refer to Figure 6 , in an embodiment of the present application, the second data line 40 includes a global data line 41 and a complementary global data line 42. The global data line 41 and the complementary global data line 42 transmit signals that are inverted with each other; the third data line 60 includes a local data line 61 and a complementary local data line 62. The local data line 61 and the complementary local data line 62 transmit signals that are inverted with each other; inverting the inverted data of the first data transmitted to the second data line 40 and then transmitting it to the third data line 60 includes: inverting the inverted data of the first data transmitted to the global data line 41 and then transmitting it to the local data line 61; transmitting the first data transmitted to the second data line 40 to the third data line 60 includes: transmitting the first data transmitted to the global data line 41 to the local data line 61.

[0052] As an example, please continue to refer to Figure 6, in an embodiment of the present application, the read-write conversion circuit 511 includes a write enable module 5111 and a write driving circuit 5112. The write enable module 5111 generates a write enable signal WrEn and a write enable inverse signal WrEn_ according to the data polarity identification signal pl and the initial write enable signal we. The write driving circuit 5112 is configured to generate a third data according to the write enable signal WrEn, the write enable inverse signal WrEn_, and the first data or the opposite data of the first data transmitted to the second data line 40, and transmit the third data to the third data line.

[0053] As an example, please refer to Figure 7 , in an embodiment of the present application, the write enable module 5111 includes a first inverter Inv1, a first nor gate Nor1, a second inverter Inv2, and a second nor gate Nor2. The first inverter Inv1 is configured such that its input terminal is electrically connected to the initial write enable signal we, and its output terminal outputs a first write enable inverse signal We1_. The first nor gate Nor1 is configured such that its input terminals are electrically connected to the data polarity identification signal pl and the output terminal of the first inverter Inv1, and its output terminal outputs the write enable signal WrEn. The second inverter Inv2 is configured such that its input terminal is electrically connected to the data polarity identification signal pl, and its output terminal outputs a data polarity identification inverse signal Pl_. The second nor gate Nor2 is configured such that its input terminals are electrically connected to the output terminal of the second inverter Inv2 and the output terminal of the first inverter Inv1, and its output terminal outputs the write enable inverse signal WrEn_.

[0054] As an example, please refer to Figure 8 , in an embodiment of the present application, the write driving circuit 5112 includes a first switch unit 51121, a second switch unit 51122, a third switch unit 51123, and a fourth switch unit 51124. The first switch unit 51121 is configured to electrically connect the local data line LIO and the global data line YIO according to the write enable signal WrEn. The second switch unit 51122 is configured to electrically connect the local data line LIO and the complementary global data line YIO_ according to the write enable inverse signal WrEn_. The third switch unit 51123 is configured to electrically connect the complementary local data line LIO_ and the global data line YIO according to the write enable inverse signal WrEn_. The fourth switch unit 51124 is configured to electrically connect the complementary local data line LIO_ and the complementary global data line YIO_ according to the write enable signal WrEn.

[0055] As an example, please continue to refer to Figure 8, in an embodiment of the present application, the read-write conversion circuit 511 further includes a read driving circuit 5113. The read driving circuit 5113 includes a fifth switch unit 51131, a sixth switch unit 51132, a seventh switch unit 51133, and an eighth switch unit 51134. The control end of the fifth switch unit 51131 is electrically connected to the local data line LIO, and is used to electrically connect the complementary global data line YIO_ and the first node a according to the control end signal; the sixth switch unit 51132 is used to electrically connect the first node a and the ground end according to the read enable signal; the control end of the seventh switch unit 51133 is electrically connected to the complementary local data line LIO_, and is used to electrically connect the global data line YIO and the second node b according to the control end signal; the eighth switch unit 51134 is used to electrically connect the second node b and the ground end according to the read enable signal.

[0056] Further, please refer to Figure 9 , in an embodiment of the present application, the data transmission circuit 100 further includes a read unit 70 and a correction module 80. The read unit 70 is electrically connected to the second data line 40, and is used to read the second data and the check code data Check_data2 on the second data line 40; the correction module 80 is electrically connected to both the first data line 30 and the read unit 70, and is used to receive the second data and the check code data Check_data2 on the second data line 40, and perform error detection and / or error correction on the second data according to the check code data Check_data2 to generate corrected data, so as to transmit the corrected data to the first data line 30. This embodiment can effectively improve the accuracy of reading data from the storage device.

[0057] Further, in an embodiment of the present application, a storage device is provided, including the data transmission circuit described in any embodiment of the present application, and is used to store and transmit data of a read operation or a read operation. By applying a power-saving algorithm in the process of writing data transmission, without changing the writing data transmission path, the number of flips of the data written into the storage device during transmission is reduced. While effectively reducing the power consumption of the write data during transmission, the check code data generated by the encoding module according to the first data on the first data line is transmitted in parallel to the subsequent data line, which can avoid reducing the data transmission efficiency due to the introduction of the encoding module while ensuring the accuracy of the written data. This embodiment reduces the power consumption of the data written into the storage array area during data transmission and improves the accuracy of writing data into the storage array area without reducing the density and quantity of the storage units in the storage unit array, and can further improve the energy-saving performance and storage performance of the semiconductor storage device.

[0058] Further, please refer to Figure 10 , in an embodiment of the present application, a data transmission method is provided, including:

[0059] Step 102: Generate check code data based on the first data on the first data line;

[0060] Step 104: Compare the first data on the first data line with the second data on the second data line to output a comparison result indicating whether the number of different bits between the first data and the second data exceeds a preset threshold, where the first data and the second data have the same preset bit width;

[0061] Step 106: Control the buffer module to transmit the inverted data of the first data to the second data line when the comparison result exceeds the preset threshold, and transmit the first data to the second data line when the comparison result does not exceed the preset threshold; wherein, the buffer module is further configured to transmit the check code data to the second data line;

[0062] Step 108: Control the first read / write conversion unit to invert the inverted data of the first data transmitted to the second data line and then transmit it to the third data line when the comparison result exceeds the preset threshold, and transmit the first data transmitted to the second data line to the third data line when the comparison result does not exceed the preset threshold; and control the second read / write conversion unit to transmit the check code data on the second data line to the third data line; wherein, the transmission path between the buffer module and the first read / write conversion unit has a first length, the transmission path between the buffer module and the second read / write conversion unit has a second length, and the first length is not less than the second length.

[0063] Specifically, please continue to refer to Figure 10, during the generation of the check code data based on the first data on the first data line, an energy-saving algorithm is applied to the process of writing data transmission. Without changing the writing data transmission path, the number of flips of the data written into the storage device during transmission is reduced, effectively reducing the power consumption during the transmission of the write data. At the same time, the check code data is transmitted in parallel to the subsequent data line, which can avoid reducing the data transmission efficiency due to data verification while ensuring the accuracy of the written data. By setting the length of the transmission path between the buffer module and the first read-write conversion unit to be not less than the length of the transmission path between the buffer module and the second read-write conversion unit, the writing path length of the check code data is reduced, and the writing time of the check code data is shortened, thereby compensating for the time spent generating the check code data, enabling the data and the check code to complete the writing operation asynchronously as possible, and improving the writing speed. In this embodiment, without reducing the density and quantity of the storage units in the storage unit array, while reducing the power consumption of the data written into the storage array area during data transmission, the accuracy of writing data into the storage array area is improved, which can further improve the energy-saving performance and storage performance of the semiconductor storage device.

[0064] Further, please refer to Figure 11 , in an embodiment of the present application, the preset threshold can be set to half of the preset bit width; the method further includes:

[0065] Step 109, receiving the second data and the check code data on the second data line, performing error detection and / or error correction on the second data according to the check code data to generate corrected data, and transmitting the corrected data to the first data line.

[0066] Specifically, please continue to refer to Figure 11 , since the written data is prone to anomalies during transmission due to various factors, resulting in a difference between the written data written and stored in the storage device and the initially written data. By performing error detection and / or error correction on the second data on the second data line, such as the global data on the global data line, according to the check code data during the process of reading data from the storage device, generating corrected data, and transmitting the corrected data to the first data line, such as the data bus, for output via the data pad of the storage device, the accuracy of the data read from the storage device can be effectively improved.

[0067] In an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it implements the data transmission method described in any embodiment of the present application.

[0068] It should be understood that although Figure 10 、 Figure 11The steps in the flowchart are shown in sequence according to the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, although Figure 10 and Figure 11 at least some of the steps may include multiple steps or multiple stages, and these steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least some of the steps or stages in other steps or other steps.

[0069] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, storage, database, or other medium used in the embodiments provided in this application can include non-volatile and / or volatile memories. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and Rambus dynamic RAM (RDRAM), etc.

[0070] Please note that the above embodiments are for illustrative purposes only and do not imply any limitation to the present invention.

[0071] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0072] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation to the scope of the patented application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all fall within the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A data transmission circuit, characterized in that, Including: An encoding module, configured to generate check code data according to the first data on the first data line; A comparison module, configured to receive the first data on the first data line and the second data on the second data line, and configured to compare the first data and the second data to output a comparison result indicating whether the number of different bits between the first data and the second data exceeds a preset threshold, wherein the first data and the second data have the same preset bit width; A buffer module, electrically connected to the first data line, the comparison module, the encoding module, and the second data line, configured to transmit the inverted data of the first data to the second data line when the comparison result exceeds the preset threshold, and configured to transmit the first data to the second data line when the comparison result does not exceed the preset threshold; the buffer module is further configured to transmit the check code data to the second data line; A first read-write conversion unit, electrically connected to the second data line and the third data line, configured to invert and then transmit the inverted data of the first data transmitted to the second data line to the third data line when the comparison result exceeds the preset threshold, and configured to transmit the first data transmitted to the second data line to the third data line when the comparison result does not exceed the preset threshold; A second read-write conversion unit, electrically connected to the second data line and the third data line, configured to transmit the check code data on the second data line to the third data line; Wherein, a transmission path between the buffer module and the first read-write conversion unit has a first length, a transmission path between the buffer module and the second read-write conversion unit has a second length, and the first length is not less than the second length.

2. The data transmission circuit according to claim 1, wherein The buffer module includes a data conversion module and a data bus buffer module; The data conversion module is electrically connected to the first data line, the comparison module, and the data bus buffer module, configured to transmit the inverted data of the first data to the data bus buffer module when the comparison result exceeds the preset threshold, and configured to transmit the first data to the data bus buffer module when the comparison result does not exceed the preset threshold; The data bus buffer module is electrically connected to the encoding module, the data conversion module, the comparison module, and the second data line, configured to generate a data polarity identification signal according to the comparison result, and further configured to transmit the first data or the inverted data of the first data to the second data line.

3. The data transmission circuit according to claim 2, wherein The preset threshold is half of the preset bit width; the comparison module includes: A comparison unit, configured to perform bit-by-bit comparison on the first data on the first data line and the second data on the second data line, and output comparison status data for each bit; A status recognition unit, electrically connected to the comparison unit and the data conversion module, configured to count the comparison status data for each bit, and generate the comparison result according to the counting result.

4. The data transmission circuit according to claim 3, wherein, The data conversion module includes: The first transmission unit is electrically connected to the first data line, the data bus buffer module, and is electrically connected to the output end of the state recognition unit through a first inverter unit, and is configured to transmit the first data on the first data line to the data bus buffer module when the comparison result does not exceed the preset threshold; The second transmission unit is electrically connected to the data bus buffer module, the output end of the state recognition unit, and is electrically connected to the first data line through a second inverter unit, and is configured to transmit the opposite data of the first data to the data bus buffer module when the comparison result exceeds the preset threshold.

5. The data transmission circuit according to any one of claims 2-4, characterized in that, The first read / write conversion unit includes: A read / write conversion circuit, which is electrically connected to both the second data line and the third data line, and is configured to invert the opposite data of the first data transmitted to the second data line and then transmit it to the third data line when the comparison result exceeds the preset threshold, and transmit the first data transmitted to the second data line to the third data line when the comparison result does not exceed the preset threshold.

6. The data transmission circuit according to claim 5, wherein The second data line includes a global data line and a complementary global data line, and the global data line and the complementary global data line transmit signals that are inverted with respect to each other; the third data line includes a local data line and a complementary local data line, and the local data line and the complementary local data line transmit signals that are inverted with respect to each other; The step of inverting the opposite data of the first data transmitted to the second data line and then transmitting it to the third data line includes: Inverting the opposite data of the first data transmitted to the global data line and then transmitting it to the local data line; The step of transmitting the first data transmitted to the second data line to the third data line includes: Transmitting the first data transmitted to the global data line to the local data line.

7. The data transmission circuit according to claim 6, characterized in that, The read / write conversion circuit includes: A write enable module, configured to generate a write enable signal and a write enable inverse signal according to the data polarity identification signal and the initial write enable signal; A write driver circuit, configured to generate a third data according to the write enable signal, the write enable inverse signal, and the first data or the opposite data of the first data transmitted to the second data line, and transmit the third data to the third data line.

8. The data transmission circuit according to claim 7, wherein The write enable module includes: A first inverter, configured such that: its input end is electrically connected to the initial write enable signal, and its output end outputs a first write enable inverse signal; A first NOR gate, configured such that: its input ends are electrically connected to the data polarity identification signal and the output end of the first inverter, and its output end outputs a write enable signal; A second inverter, configured such that: its input end is electrically connected to the data polarity identification signal, and its output end outputs a data polarity identification inverse signal; A second NOR gate, configured such that: its input ends are electrically connected to the output end of the second inverter and the output end of the first inverter, and its output end outputs a write enable inverse signal.

9. The data transmission circuit according to claim 8, wherein The write driver circuit includes: A first switch unit, configured to electrically connect the local data line and the global data line according to the write enable signal; A second switch unit, configured to electrically connect the local data line and the complementary global data line according to the write enable inverse signal; A third switch unit, configured to electrically connect the complementary local data line and the global data line according to the write enable inverse signal; A fourth switch unit, configured to electrically connect the complementary local data line and the complementary global data line according to the write enable signal.

10. The data transmission circuit according to claim 9, wherein The read-write conversion circuit further includes a read driving circuit, and the read driving circuit includes: A fifth switch unit, whose control terminal is electrically connected to the local data line, and is configured to electrically connect the complementary global data line and a first node according to a control terminal signal; A sixth switch unit, configured to electrically connect the first node and the ground terminal according to a read enable signal; A seventh switch unit, whose control terminal is electrically connected to the complementary local data line, and is configured to electrically connect the global data line and a second node according to a control terminal signal; An eighth switch unit, configured to electrically connect the second node and the ground terminal according to a read enable signal.

11. The data transmission circuit according to any one of claims 1-4, characterized in that, It further includes: A read unit, electrically connected to the second data line, and configured to read the second data and the check code data on the second data line; A correction module, electrically connected to both the first data line and the read unit, and configured to receive the second data and the check code data on the second data line, and perform error detection and / or error correction on the second data according to the check code data to generate corrected data, so as to transmit the corrected data to the first data line.

12. The data transmission circuit according to any one of claims 1-4, characterized in that The encoding module includes an ECC encoding unit.

13. A storage device, characterized in that, It includes: The data transmission circuit according to any one of claims 1-12, configured to store and transmit data of a read operation or a write operation.

14. A data transmission method, characterized in that, It includes: Generating check code data according to the first data on the first data line; Comparing the first data on the first data line with the second data on the second data line to output a comparison result of whether the number of different bits between the first data and the second data exceeds a preset threshold, where the first data and the second data have the same preset bit width; Controlling the buffer module to transmit the inverse data of the first data to the second data line when the comparison result exceeds the preset threshold, and transmit the first data to the second data line when the comparison result does not exceed the preset threshold; wherein, the buffer module is further configured to transmit the check code data to the second data line; Controlling the first read-write conversion unit to invert the inverse data of the first data transmitted to the second data line and then transmit it to the third data line when the comparison result exceeds the preset threshold, and transmit the first data transmitted to the second data line to the third data line when the comparison result does not exceed the preset threshold; and controlling the second read-write conversion unit to transmit the check code data on the second data line to the third data line; wherein, the transmission path between the buffer module and the first read-write conversion unit has a first length, the transmission path between the buffer module and the second read-write conversion unit has a second length, and the first length is not less than the second length.

15. The data transmission method according to claim 14, wherein The preset threshold is half of the preset bit width; the method further includes: Receiving the second data and the check code data on the second data line, performing error detection and / or error correction on the second data according to the check code data, generating corrected data, and transmitting the corrected data to the first data line.

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