Semiconductor circuit having improved bonding force between substrate and sealing layer and method of manufacturing the same

Abstract

The application relates to a semiconductor circuit with improved bonding force between a substrate and a sealing layer and a manufacturing method thereof, which comprises a substrate, a plurality of electronic components, a plurality of pins and a sealing layer. The side surface of the substrate is provided with a plurality of arc-shaped protrusions, the protrusions are cylindrical surfaces, and the protrusions are curved along the side surface length direction. The plurality of electronic components are arranged on the component mounting positions of a circuit wiring layer. The plurality of pins are arranged on at least one side of the substrate, and one end of the plurality of pins is connected with the circuit wiring layer. The sealing layer covers one side of the substrate on which the electronic components are arranged, and covers the plurality of electronic components. The other side of the substrate is exposed from the sealing layer, and the other end of the plurality of pins is exposed from the sealing layer. The side surface of the substrate is provided with a plurality of outward protruding arc surfaces, so that the sealing layer material can smoothly flow along the side surface to the bottom of the substrate, so that the substrate and the sealing layer are tightly combined, the gap between the substrate and the sealing layer is greatly reduced, the external moisture is prevented from entering the semiconductor, and the working reliability of the semiconductor is improved.

Description

Technical Field

[0001] This invention relates to a semiconductor circuit and its manufacturing method for improving the bonding strength between the substrate and the sealing layer, belonging to the field of semiconductor circuit application technology. Background Technology

[0002] Semiconductor circuits are power-driven products that combine power electronics and integrated circuit technology. The outer surface of a semiconductor circuit is typically encapsulated by a resin material formed through injection molding, creating a sealing layer that seals the circuit board and electronic components based on the substrate. Leads extend from one or both sides of the sealing layer. During the traditional substrate manufacturing process, cutting creates convex edges on the side surfaces. These edges affect the flowability of the injection molding material on the substrate surface during the sealing layer formation, hindering the downward flow of molten injection molding material. This can lead to tiny gaps between the injection molding material and the substrate surface, allowing external moisture to easily enter the semiconductor circuit and cause malfunctions. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to solve the problem of semiconductor circuit failure caused by the convex edge on the side of the substrate of existing semiconductor circuits, which leads to the separation of the substrate and the sealing layer.

[0004] Specifically, this invention discloses a semiconductor circuit for improving the bonding strength between a substrate and a sealing layer, comprising:

[0005] The substrate includes a mounting surface and a heat dissipation surface. The mounting surface is provided with a circuit wiring layer, which includes multiple component mounting positions and multiple pads. The side of the substrate is provided with multiple arc-shaped protrusions, wherein the protrusions are cylindrical surfaces that are bent along the side length direction.

[0006] Multiple electronic components are located in the component mounting positions of the circuit wiring layer;

[0007] Multiple pins are disposed on at least one side of the substrate, and one end of the multiple pins is connected to the circuit wiring layer;

[0008] A sealing layer covers one side of the substrate on which electronic components are mounted, and covers multiple electronic components. The other side of the substrate is exposed from the sealing layer, and the other ends of multiple pins are exposed from the sealing layer.

[0009] Optionally, the protrusions are continuously spaced on the side of the substrate.

[0010] Optionally, in the cross-section of the substrate in the thickness direction, the arc angle of the arc formed by the protrusion is greater than 90 degrees and less than 270 degrees.

[0011] Optionally, the length of one side of the cross section is 5 to 20 times the radius of the arc.

[0012] Optionally, the distance between the center of the arc and the straight line formed on the cross section connecting the two protrusions is half the radius of the arc.

[0013] Optionally, multiple electronic components include power devices that generate heat, and an auxiliary heat sink is provided between the power devices and the circuit wiring layer.

[0014] Optionally, the semiconductor circuit also includes bonding wires that connect multiple electronic components, circuit wiring layers, and multiple pins.

[0015] The present invention also proposes a manufacturing method based on the above-described semiconductor circuit, the manufacturing method comprising:

[0016] Provide a substrate, manufacture the substrate, and process the side surface of the substrate to form multiple evenly spaced protrusions on the side surface, wherein the protrusions are cylindrical surfaces that are curved along the side length direction.

[0017] A circuit wiring layer is formed on the surface of the substrate;

[0018] Fabricate pins, wherein one end of multiple pins is connected to each other by connecting ribs;

[0019] Configure electronic components and pins in the circuit wiring layer;

[0020] Bonding wires are used to connect electronic components and circuit wiring layers to form a semi-finished circuit.

[0021] The circuit semi-finished product is injection molded using a packaging mold to form a sealing layer, wherein the sealing layer covers at least one side of the substrate;

[0022] The connecting ribs between the pins are cut off to form the semiconductor circuit under test. The semiconductor circuit under test is tested by the test equipment. If the test is qualified, the pins of the qualified semiconductor circuit under test are bent and shaped according to the preset pin shape to obtain a qualified semiconductor circuit.

[0023] The semiconductor circuit of the present invention includes a substrate, multiple electronic components, multiple pins, and a sealing layer. The substrate includes a mounting surface and a heat dissipation surface. A wiring layer is disposed on the mounting surface, containing multiple component mounting positions and multiple pads. Multiple arc-shaped protrusions, each cylindrical and curved along its side surface, are provided on the side of the substrate. Multiple electronic components are disposed on the component mounting positions of the wiring layer. Multiple pins are disposed on at least one side of the substrate, with one end of each pin connected to the wiring layer. The sealing layer covers the side of the substrate on which the electronic components are mounted and also covers the multiple electronic components. The other side of the substrate and the other ends of the multiple pins are exposed from the sealing layer. Unlike existing substrates with convex sharp edges, the substrate of the present invention has multiple convex arc surfaces on its side surface. This allows the sealing layer material to flow smoothly along the side surface and reach the bottom of the substrate, resulting in a tight bond between the two. This significantly reduces gaps between them, prevents external moisture from intruding into the semiconductor, and improves its operational reliability. Moreover, the presence of multiple protrusions on the side increases the surface area of ​​the side significantly compared to the flat surface in the prior art, thereby increasing the contact area with the sealing layer, further enhancing the bonding force between the two, and thus further increasing the operational reliability of the semiconductor circuit. Attached image description:

[0024] Figure 1 This is a cross-sectional view of a substrate in the prior art along the thickness direction.

[0025] Figure 2 This is a planar schematic diagram of the substrate of the semiconductor circuit according to an embodiment of the present invention;

[0026] Figure 3 for Figure 2 Enlarged view of section A;

[0027] Figure 4 This is a schematic diagram of a semiconductor circuit according to an embodiment of the present invention;

[0028] Figure 5 for Figure 4 A sectional view along the X1-X1' direction;

[0029] Figure 6 This is a flowchart of a semiconductor circuit manufacturing method according to an embodiment of the present invention.

[0030] Figure label:

[0031] Substrate 10, protrusion 11, arc surface 111, mounting surface 12, heat dissipation surface 13, pin 20, bonding wire 30, electronic component 40, IGBT transistor 41, fast recovery diode 42, driver chip 43, resistor and capacitor components 44, sealing layer 60, insulating layer 70, circuit wiring layer 80. Detailed Implementation

[0032] It should be noted that, provided there is no structural or functional conflict, the embodiments and features described in these embodiments can be combined with each other. The present invention will now be described in detail with reference to examples.

[0033] The semiconductor circuit mentioned in this invention is a circuit module that integrates power switching devices and high-voltage drive circuits, and is sealed in an external package. It has wide applications in the field of power electronics, such as frequency converters for driving motors, various inverter voltages, variable frequency speed control, metallurgical machinery, electric traction, and variable frequency home appliances. This semiconductor circuit also has several other names, such as Modular Intelligent Power System (MIPS), Intelligent Power Module (IPM), or hybrid integrated circuit, power semiconductor module, power module, etc.

[0034] The semiconductor circuit proposed in this invention enhances the bonding strength between the substrate 10 and the sealing layer 60, such as... Figures 2 to 5 As shown, the substrate includes a substrate 10, multiple electronic components 40, multiple pins 20, and a sealing layer 60. The substrate 10 includes a mounting surface 12 and a heat dissipation surface 13. The mounting surface 12 is provided with a circuit wiring layer 80, which includes multiple component mounting positions and multiple pads. Multiple arc-shaped protrusions 11 are provided on the side of the substrate 10, and the protrusions 11 are cylindrical and curved along the side length direction. Multiple electronic components 40 are disposed at the component mounting positions of the circuit wiring layer 80. Multiple pins 20 are disposed on at least one side of the substrate 10, and one end of the multiple pins 20 is connected to the circuit wiring layer 80. The sealing layer 60 covers the side of the substrate 10 where the electronic components 40 are mounted and covers multiple electronic components 40. The other side of the substrate 10 is exposed from the sealing layer 60, and the other ends of the multiple pins 20 are exposed from the sealing layer 60.

[0035] The existing semiconductor circuit substrate 200 has the following external structure: Figure 1 As shown, the substrate 200 is formed from a substrate by cutting. During cutting, a convex edge 201 is formed on the side of the substrate 200. This convexity prevents the molten sealing material, such as thermoplastic resin, from flowing downwards to the lower edge 201 during the subsequent formation of the sealing layer. This makes it easy for gaps to form between the resin and the lower edge 201, resulting in a loose bond between the resin and the substrate. Consequently, external moisture can easily enter the semiconductor circuit through these gaps, causing malfunctions in the components on the circuit board inside the semiconductor circuit. The basic principle of the semiconductor circuit of this invention is as follows... Figures 2 to 5As shown, after the substrate is cut and then polished, multiple cylindrical protrusions 11 curved along the length of the side are formed. This makes the side of the substrate 10 planar in the thickness direction, allowing the molten sealing material, such as resin, to flow smoothly along the side and reach the bottom of the substrate 10 when the sealing layer 60 is formed. This ensures a tight bond between the two, greatly reducing gaps and preventing external moisture from penetrating the semiconductor, thus improving its operational reliability. Furthermore, the multiple protrusions 11 on the side significantly increase the surface area compared to the planar surface in existing technologies, increasing the contact area with the sealing layer 60 and further enhancing the bonding strength, thereby further increasing the operational reliability of the semiconductor circuit.

[0036] In some embodiments of the present invention, such as Figures 2 to 5 As shown, protrusions 11 are continuously spaced on the side surface of substrate 10. Preferably, the protrusions 11 are evenly spaced on the side surface of substrate 10, and the protrusions 11 are connected by a long strip-shaped plane extending along the thickness direction. Through experimental testing, if the protrusions 11 are continuously arranged, that is, the arc surfaces 111 of the protrusions 11 are connected to each other, the V-shaped joint surface formed at the joint of the arc surfaces 111 will hinder the flow of molten sealing material, and a hollow area is easily formed at the bottom of the V-shaped joint surface, where the sealing material cannot cover. By spaced arrangement, the area between the two arc surfaces 111 is a horizontal plane, allowing the sealing material to flow smoothly on the horizontal plane, effectively promoting the sealing material to fully cover the side surface of substrate 10, thereby increasing the bonding force between the two.

[0037] Furthermore, such as Figures 2 to 5 As shown, in order to ensure that the arc surface 111 facilitates the flow of the sealing material, the arc angle Ω of the arc formed by the protrusion 11 in the thickness direction of the substrate 10 is greater than 90 degrees and less than 270 degrees. That is, the length of the arc is less than the length of the semicircle, so that the angle formed by one end of the arc and the corresponding straight line of the connecting surface in the cross section is an obtuse angle greater than 90 degrees, thus not hindering the flow of the sealing material at this point and enhancing its flow capacity.

[0038] Furthermore, such as Figures 2 to 5 As shown, in the cross-section of the substrate 10 in the thickness direction, the length of one side is 5 to 20 times the radius of the arc. In this way, a corresponding number of protrusions 11 are provided on the side surface of the substrate 10, thereby effectively increasing the contact area between the basic side surface and the sealing layer 60.

[0039] Preferably, through experimental testing, the distance between the center of the arc and the straight line formed on the cross section connecting the two protrusions 11 is half the radius R of the arc, i.e. Figure 3 In the case where R1=R2, and the distance between the arcs F=(2- The protrusion 11 manufactured in this way can facilitate the flow of sealing material to the maximum extent, thereby obtaining the optimal bonding force between the sealing material and the side of the substrate 10.

[0040] In the semiconductor circuit of the present invention, during the processing of the substrate 10, a plurality of uniformly spaced protrusions 11 are provided on the side surface of the substrate 10, and the protrusions 11 are cylindrical surfaces curved along the side length direction. This facilitates the flow of molding compound such as resin along the side surface of the substrate 10 during the potting process of forming the sealing layer 60, making the molding compound and the side surface of the substrate 10 tightly bonded. Moreover, by providing a plurality of protrusions 11, the area of ​​the side surface is greatly increased, thereby increasing the contact area with the sealing layer 60. This effectively increases the bonding force between the substrate 10 and the sealing layer 60, reduces the possibility of external moisture intrusion due to gaps between the side surface of the substrate 10 and the sealing layer 60, and thus increases the operational reliability of the semiconductor circuit.

[0041] In some embodiments of the present invention, the heat dissipation substrate 10 is made of a metallic material, specifically a rectangular plate made of aluminum of materials such as 1100 or 52. The insulating layer 70 is made of a resin material such as epoxy resin, and fillers such as alumina and aluminum carbide are filled inside the resin material to improve thermal conductivity. To improve thermal conductivity, these fillers can be angular in shape. To avoid the risk of the fillers damaging the contact surfaces of the electronic components 40 disposed on its surface, the fillers can be spherical, angular, or a mixture of angular and spherical shapes. The circuit wiring layer 80 can be formed by etching copper foil or by printing a paste-like conductive medium. The conductive medium can be a conductive material such as graphene, solder paste, or silver paste. The surface of the circuit wiring layer 80 is provided with multiple component mounting positions for mounting multiple electronic components 40. The electronic components 40 include power devices and driver chips 43. The power devices include switching transistors such as IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductors), specifically IGBTs 41 in this embodiment. They also include fast recovery diodes 42, which consume a lot of power and generate a lot of heat, thus the temperature of the entire semiconductor circuit is relatively high compared to room temperature during operation. The electronic components 40 also include passive components such as resistors and capacitors 44. For power devices that generate a lot of heat, auxiliary heat sinks (not shown in the figure) are used to fix them in the component mounting positions. The circuit wiring layer 80 and the multiple electronic components 40 mounted on it constitute the entire semiconductor circuit. Multiple pads are also provided around the periphery of the surface of the circuit wiring layer 80 to fix the pins 20, thereby transmitting signals to the internal circuitry of the semiconductor circuit. Pin 20 is generally made of metals such as copper. A nickel-tin alloy layer is formed on the copper surface through chemical plating and electroplating. The thickness of the alloy layer is generally 5μm. The plating layer can protect the copper from corrosion and oxidation and improve solderability. The material of pin 20 can be C194 (-1 / 2H) sheet (chemical composition: Cu (≧97.0), Fe: 2.4, P: 0.03, Zn: 0.12) or KFC (-1 / 2H) sheet (chemical composition: Cu (≧99.6), Fe: 0.1 (0.05~0.15), P: 0.03 (0.025~0.04)). The 0.5mm C194 or KFC sheet is processed by stamping or etching process, and then the surface is first plated with nickel with a thickness of 0.1-0.5um, and then tin with a thickness of 2-5um. The excess connecting ribs of pin 20 are removed and shaped into the required shape using specific equipment.

[0042] Furthermore, a thin layer of green solder mask (not shown in the figure) is provided on the surface of the circuit wiring layer 80 where no component mounting positions and pads are provided. This layer serves to prevent short circuits between traces of the circuit wiring layer 80 and to prevent oxidation and contamination of the surface of the circuit wiring layer 80, thereby providing protection.

[0043] In some embodiments of the present invention, such as Figure 5 As shown, the semiconductor circuit also includes multiple bonding wires 30, which connect multiple electronic components 40, the circuit wiring layer 80, and multiple pins 20. For example, the bonding wires 30 can connect electronic components 40 to each other, electronic components 40 to the circuit wiring layer 80, electronic components 40 to pins 20, and circuit wiring layer 80 to pins 20. The electronic components 40 are power devices mentioned in the above embodiments, such as IGBTs, freewheeling diodes, and driver chips 43, as well as others such as resistors and capacitors. The bonding wires 30 are typically gold wires, copper wires, gold-copper hybrid wires, fine bonding wires 38 μm or less, or thick bonding wires 100 μm or more.

[0044] The present invention also proposes a method for manufacturing a semiconductor circuit that enhances the bonding force between the substrate 10 and the sealing layer 60 as mentioned in the above embodiments, such as... Figure 6 As shown, the manufacturing method includes:

[0045] Step S100: Fabricate a substrate and process the side surface of the substrate to form multiple evenly spaced protrusions on the side surface, wherein the protrusions are cylindrical surfaces that are bent along the side length direction.

[0046] Step S200: Form a circuit wiring layer on the surface of the substrate;

[0047] Step S300: Prepare pins, wherein one end of multiple pins is connected to each other by connecting ribs;

[0048] Step S400: Configure electronic components and pins in the circuit wiring layer;

[0049] Step S500: Connect bonding wires between electronic components and circuit wiring layers to form a circuit semi-finished product;

[0050] Step S600: The semi-finished circuit is injection molded through a packaging mold to form a sealing layer, wherein the sealing layer covers the side of the substrate on which the electronic components are mounted.

[0051] Step S700: Cut off the connecting ribs between the pins to form the semiconductor circuit under test. Perform parameter testing on the semiconductor circuit under test using a testing device. If the test is qualified, bend each pin of the qualified semiconductor circuit under test according to the preset pin shape to obtain a qualified semiconductor circuit.

[0052] In step S100, the substrate 10 can be made from an aluminum substrate profile. The profile is cut according to a preset size to form a substrate 10 with the required dimensions. At this time, due to the cutting of the tool, a convex edge will be formed on the side of the substrate 10, and some parts will also form burr peaks. Then, the burrs are ground down by the equipment, and multiple evenly spaced protrusions 11 are further ground on the side. The surface of the protrusion 11 is a cylindrical surface that is curved along the side length direction, such as... Figure 2 and Figure 3 As shown, in the cross-section of the substrate 10 along the thickness direction, the protrusions 11 form uniformly spaced arcs, with an equal distance F between the arcs. The arc angle is preferably greater than 90 degrees and less than 2 degrees. This ensures that the angle formed by one end of the arc and the corresponding straight line of the connecting surface in the cross-section is an obtuse angle greater than 90 degrees, thus not hindering the flow of the sealing material and enhancing its flow capacity. Furthermore, the distance between the center of the arc and the straight line connecting two protrusions 11 in the cross-section is half the radius R of the arc. Figure 3 In the case where R1=R2, and the distance between the arcs F=(2- The protrusion 11 manufactured in this way can facilitate the flow of sealing material to the maximum extent, thereby obtaining the optimal bonding force between the sealing material and the side of the substrate 10.

[0053] In step S200, after the substrate 10 is fabricated, an insulating layer 70 can be prepared on the surface of the substrate 10 to achieve electrical insulation between the mounting surface 12 of the metal substrate 10 and the metal wiring layer 80, preventing short circuits in the wiring layer 80. The insulating layer 70 can be made of resin materials such as epoxy resin, and fillers such as alumina and aluminum carbide can be filled inside the resin material to improve thermal conductivity. Next, a metal substrate such as copper foil is laminated onto the surface of the insulating layer 70, and then the surface of the metal substrate is processed, such as by etching the copper foil, partially removing the copper foil to form wiring layers 80. Multiple component mounting positions and multiple pads are provided on these wiring layers 80.

[0054] Step S300 involves preparing the pin 20. The pin 20 can be formed from a copper substrate, such as a strip with a length of 25 mm, a width of 1.5 mm, and a thickness of 1 mm. A nickel layer is then formed on the surface of the pin 20 using chemical plating. This involves a mixture of nickel salt and sodium hypophosphite, with the addition of a suitable complexing agent, to form a nickel layer on the copper substrate of a specific shape. Metallic nickel has strong passivation capabilities, rapidly forming an extremely thin passivation film that resists corrosion from the atmosphere, alkalis, and certain acids. The nickel plating crystals are extremely fine, and the nickel layer thickness is typically 0.1 μm. Next, using an acidic sulfate process, the copper substrate with the formed shape and nickel layer is immersed in a plating solution containing positive tin ions at room temperature and an electric current is applied to form a nickel-tin alloy layer on the nickel layer surface. The nickel layer thickness is typically controlled at 5 μm. The formation of this nickel layer greatly improves protection and solderability. In order to limit the spacing between each pin 20, a connecting rib is pressed at the second end of the pin 20 using a specific mold to form a lead frame, thereby facilitating the rapid installation of multiple pins 20 on the substrate 10, thus completing the fabrication of the pins 20.

[0055] In step S400, solder paste is first applied to the component mounting positions and pads of the circuit wiring on the substrate 10 using a solder paste printer and a stencil. The stencil can be 0.13mm thick. These component mounting positions and pads are where solder paste will be applied, such as for subsequent soldering of electronic components 40. Alternatively, a silver paste dispensing machine can be used to apply specific patterns to the component mounting positions and pads with silver paste, which can also be used to solder electronic components 40 at these locations.

[0056] Next, electronic component 40 and pin 20 are installed. Electronic component 40 can be placed directly in the component mounting position. One end of pin 20 is placed on the pad, and the other end needs to be fixed by a carrier. The carrier is made of materials such as synthetic stone or stainless steel. Due to the connecting effect of the reinforcing ribs, it is easy to fix pin 20 in the position of the pad. Then, the substrate 10 placed on the carrier is cured by reflow soldering with solder paste or silver paste. Electronic component 40 and pin 20 are soldered and fixed to the component mounting position and the pad, respectively.

[0057] In step S500, this step involves connecting the bonding wires 30. One of the driver bonding pads of the driver chip 43 in the electronic component 40 can be directly connected to the gate bonding area of ​​a power device such as an IGBT via bonding wires 30, such as gold wires, copper wires, gold-copper hybrid wires, or fine aluminum wires of 38µm or less. Other driver bonding pads of the driver chip 43 can be directly connected to the pads of the circuit wiring layer 80 via bonding wires 30, such as gold wires, copper wires, gold-copper hybrid wires, or fine aluminum wires of 38µm or less. The emitter bonding area of ​​the IGBT can be directly connected to the pads of the circuit wiring layer 80 via thick aluminum wires of 100µm or more.

[0058] In step S600, this step is to form the sealing layer 60. First, the substrate 10, on which the electronic components 40, power devices, and pins 20 were installed in the above steps, is baked in an oxygen-free environment for no less than 2 hours, and the baking temperature can be selected as 5°C. The substrate 10 is then transferred to a packaging mold, which includes an upper mold and a lower mold. In addition, the pins 20 are fixedly disposed between the upper mold and the lower mold. The substrate 10 is positioned by contacting the fixing device located in the lower mold with the pins 20 which are soldered and fixed to the substrate 10.

[0059] Then, the packaging mold on which the substrate 10 is placed is closed, and sealing resin is injected through the gate. The sealing method can be either transfer molding using thermosetting resin or injection molding using thermosetting resin. Furthermore, the gas inside the mold cavity corresponding to the sealing resin injected from the gate is discharged to the outside through the vent.

[0060] Finally, demolding is performed by placing demolding pillars on the upper mold that abut against the surface of the sealing resin, causing the sealing resin to detach from the inner surface of the upper mold.

[0061] The sealing resin is then cured to form a sealing layer 60, with the bottom of the metal substrate exposed in the sealing layer 60 and the free end of the pin 20 exposed from the sealing layer 60.

[0062] In step S700, the connecting ribs (not shown in the figure) connecting the other ends of the multiple pins 20 are first removed to form the semiconductor circuit under test. These connecting ribs are residues generated during the pin 20 fabrication process. The connecting ribs can cause short circuits between the pins 20, therefore they need to be removed during semiconductor circuit fabrication. In one example, the connecting ribs connecting the second ends of the multiple pins 20 can be removed using a specific device, thus decoupling the other ends of each pin 20 and obtaining the semiconductor circuit under test for parameter testing in the next step.

[0063] The testing equipment can be used to perform parameter tests on the semiconductor circuit under test. For example, the testing equipment can send test signals to the semiconductor circuit under test and receive feedback signals from the semiconductor circuit under test. The testing equipment processes the feedback signals to obtain corresponding feedback data and compares the feedback data with a preset threshold range. When the feedback data meets the preset threshold range, the semiconductor circuit under test is determined to be qualified. Then, the pins 20 of the qualified semiconductor circuit under test can be bent and shaped according to the preset pin 20 shape to obtain a qualified semiconductor circuit.

[0064] Furthermore, before the testing equipment can be used to perform parameter testing on the semiconductor circuit under test, laser marking can be performed using laser equipment to mark the surface of the sealing layer 60 of the semiconductor circuit, thereby facilitating the identification and management of semiconductor circuit products.

[0065] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0066] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0067] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0068] In this invention, unless otherwise explicitly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components, unless otherwise explicitly limited. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0069] In this invention, unless otherwise explicitly specified and limited, "above" or "below" the second feature can mean that the first feature is in direct contact with the second feature, or that the first feature is in indirect contact with the second feature through an intermediate medium. Furthermore, "above," "over," and "on top" of the second feature can mean that the first feature is directly above or diagonally above the second feature, or simply that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature can mean that the first feature is directly below or diagonally below the second feature, or simply that the first feature is at a lower horizontal level than the second feature.

[0070] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A semiconductor circuit for improving the adhesion between a substrate and a sealing layer, characterized in that, include: The substrate includes a mounting surface and a heat dissipation surface. The mounting surface is provided with a circuit wiring layer, which includes multiple component mounting positions and multiple pads. The side of the substrate is provided with multiple arc-shaped protrusions, wherein the protrusions are cylindrical surfaces that are bent along the side length direction. Multiple electronic components are disposed at the component mounting positions of the circuit wiring layer; A plurality of pins are disposed on at least one side of the substrate, and one end of the plurality of pins is connected to the circuit wiring layer; A sealing layer covers one side of the substrate on which the electronic components are mounted, and covers a plurality of the electronic components. The other side of the substrate is exposed from the sealing layer, and the other ends of the plurality of pins are exposed from the sealing layer. The protrusions are continuously spaced on the side of the substrate, and the protrusions are connected by a long strip-shaped plane extending along the thickness direction. In the cross-section of the substrate in the thickness direction, the arc angle of the arc formed by the protrusion is greater than 90 degrees and less than 270 degrees. The length of one side of the cross section is 5 to 20 times the radius of the arc.

2. The semiconductor circuit according to claim 1, characterized by The distance between the centers of the arc and the straight lines connecting the two protrusions on the cross section is half the radius of the arc.

3. The semiconductor circuit according to claim 1, characterized by The plurality of said electronic components include power devices that generate heat, and an auxiliary heat sink is provided between the power devices and the circuit wiring layer.

4. The semiconductor circuit according to claim 1, characterized by The semiconductor circuit also includes bonding wires that connect the plurality of electronic components, the circuit wiring layer, and the plurality of pins.

5. The method of manufacturing a semiconductor circuit according to any one of claims 1 to 4, characterized by, The manufacturing method includes: A substrate is provided, the substrate is manufactured, and the side surface of the substrate is processed to form a plurality of evenly spaced protrusions on the side surface, wherein the protrusions are cylindrical surfaces curved along the side length direction. A circuit wiring layer is formed on the surface of the substrate; Fabricate pins, wherein one end of multiple pins is connected to each other by connecting ribs; Electronic components and pins are configured in the circuit wiring layer; Bonding wires are connected between the electronic components and the circuit wiring layer to form a circuit semi-finished product; The circuit semi-finished product is injection molded using a packaging mold to form a sealing layer, wherein the sealing layer covers at least one side of the substrate; The connecting ribs between the pins are cut off to form a semiconductor circuit under test. The semiconductor circuit under test is tested by a testing device. If the test is qualified, the pins of the qualified semiconductor circuit under test are bent and shaped according to a preset pin shape to obtain a qualified semiconductor circuit.

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