Semiconductor element with branched programmable structure and method for producing same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a first electrode, a first vertical pillar, and a first lower branch unit disposed at a first vertical level and having a first set of lower plates extending from the first vertical pillar and parallel to a first direction; two second electrodes each having a second vertical pillar and a second lower branch unit disposed at a second vertical level higher than the first vertical level and having a first set of lower plates extending from the second vertical pillar and parallel to the first direction; and a first isolation layer disposed between the first and second branch units. The first set of lower plates of the first and second lower branch units partially overlap. The first isolation layer and the first and second electrodes together configure a programmable structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 228,172, filed April 12, 2021, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor element and a method of manufacturing the semiconductor element. In particular, it relates to a semiconductor element having a branched programmable structure and a method of manufacturing the semiconductor element having the branched programmable structure. BACKGROUND

[0004] Semiconductor elements are used in different electronic applications, such as personal computers, mobile phones, digital cameras, or other electronic devices. The size of semiconductor elements is gradually reduced to meet the increasing demand for computing power. However, during the process of reducing the size, different problems are increased, and such problems continue to increase in number and complexity. Therefore, there are still ongoing challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of background art is provided merely for generally presenting the technical background of the present disclosure and does not acknowledge that any of the above description of background art discloses the subject matter of the present disclosure, does not constitute the prior art of the present disclosure, and should not be considered as any part of the present disclosure. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor element, comprising a first electrode comprising a first vertical pillar; and a first lower branch unit disposed at a first vertical level and comprising a first set of lower plates extending from opposite sides of the first vertical pillar and perpendicular to a first direction; two second electrodes disposed at two sides of the first electrode and each comprising a second vertical pillar; and a second lower branch unit disposed at a second vertical level higher than the first vertical level and comprising a first set of lower plates extending from opposite sides of the second vertical pillar and parallel to the first direction; and a first isolation layer disposed between the first lower branch unit and the second lower branch unit. In a top view, the first set of lower plates of the first lower branch unit and the first set of lower plates of the second lower branch unit partially overlap. The first electrode, the first isolation layer, and the second electrode together configure a programmable structure.

[0007] In some embodiments, the first vertical pillar comprises a plurality of first connection vias stacked vertically and a center plate of the first lower branch unit, and the first set of lower plates of the first lower branch unit extend from the center plate of the first lower branch unit.

[0008] In some embodiments, a shape of the center plate of the first lower branch unit in a top view is triangular, square, rectangular, polygonal, circular, or elliptical.

[0009] In some embodiments, the first isolation layer is an etch stop layer.

[0010] In some embodiments, the first set of lower plates comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide, a metal nitride, a transition metal aluminide, or a combination thereof.

[0011] In some embodiments, the first isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, or a combination thereof.

[0012] An embodiment of the present disclosure provides a semiconductor element, comprising two first electrodes configured orthogonally, two second electrodes configured orthogonally, and a first isolation layer. The two first electrodes respectively comprise a first vertical column and a first lower branch unit disposed at a first vertical level. The first lower branch unit comprises a first set of lower plates extending from opposite sides of the first vertical column and parallel to a first direction, and a second set of lower plates extending from other opposite sides of the first vertical column and parallel to a second direction perpendicular to the first direction. The two second electrodes comprise a second vertical column and a second lower branch unit disposed at a second level higher than the first vertical level. The second lower branch unit comprises a first set of lower plates extending from opposite sides of the second vertical column and parallel to the first direction, and a second set of lower plates extending from other opposite sides of the second vertical column and parallel to the second direction. The first isolation layer is disposed between the first lower branch unit and the second lower branch unit. In a top view, the first set of lower plates of the first lower branch unit and the second lower branch unit partially overlap, and in a top view, the second set of lower plates of the first lower branch unit and the second lower branch unit partially overlap. The first electrodes, the second electrodes, and the first isolation layer together configure a programmable structure.

[0013] In some embodiments, the two first electrodes respectively comprise a first upper branch unit disposed at a third vertical level higher than the second vertical level. The first upper branch unit comprises a first set of upper plates extending from other opposite sides of the first vertical column and parallel to a third direction oblique to the first direction and the second direction, and a second set of upper plates extending from other opposite sides of the first vertical column and parallel to a fourth direction perpendicular to the third direction.

[0014] In some embodiments, the semiconductor element further includes a third electrode and a second isolation layer. The third electrode includes a third vertical pillar and a first intermediate branch unit disposed at a fourth vertical level. The first intermediate branch unit includes a first set of intermediate plates extending from opposite sides of the third vertical pillar and parallel to the third direction, the fourth vertical level being higher than the third vertical level. In a top view, the first set of intermediate plates of the first intermediate branch unit partially overlaps the first set of upper plates of the first upper branch unit. The second isolation layer is disposed between the first upper branch unit and the first intermediate branch unit.

[0015] In some embodiments, the first intermediate branch unit includes a second set of intermediate plates extending from other opposite sides of the third vertical pillar and parallel to the fourth direction.

[0016] In some embodiments, the semiconductor element further includes a third isolation layer. The second electrode respectively includes a second upper branch unit disposed at a fifth vertical level. The second upper branch unit includes a first set of upper plates extending from other opposite sides of the second vertical pillar and parallel to the third direction, and a second set of upper plates extending from other opposite sides of the second vertical pillar and parallel to the fourth direction. The fifth vertical level is higher than the fourth vertical level. In a top view, the second set of upper plates of the second upper branch unit partially overlaps the second set of intermediate plates of the first intermediate branch unit. The third isolation layer is disposed between the second upper branch unit and the first intermediate branch unit.

[0017] In some embodiments, the semiconductor element further includes a fourth electrode including a fourth vertical pillar and a second intermediate branch unit disposed at the same level as the first intermediate branch unit. The second intermediate branch unit includes a first set of intermediate plates extending from opposite sides of the fourth vertical pillar and parallel to the third direction. In a top view, the first set of intermediate plates of the second intermediate branch unit partially overlaps the first set of upper plates of the second upper branch unit. The third isolation layer is disposed between the second upper branch unit and the second intermediate branch unit.

[0018] In some embodiments, the second intermediate branch unit includes a second set of intermediate plates extending from other opposite sides of the fourth vertical pillar and parallel to the fourth direction. In a top view, the second set of intermediate plates of the second intermediate branch unit partially overlaps the second set of upper plates of the first upper branch unit. The second isolation layer is disposed between the first upper branch unit and the second intermediate branch unit.

[0019] In some embodiments, a lower surface of the second vertical pillar contacts a substrate.

[0020] In some embodiments, a lower surface of the third vertical pillar is disposed at a vertical level higher than a vertical level of a lower surface of the first vertical pillar.

[0021] In some embodiments, a lower surface of the third vertical pillar contacts a substrate.

[0022] Another embodiment of the present disclosure provides a method of fabricating a semiconductor element, comprising forming a plurality of first lower branch units at a first vertical level; forming a first isolation layer to cover the plurality of first lower branch units; and forming a plurality of second lower branch units on the first isolation layer at a second vertical level higher than the first vertical level. The plurality of first lower branch units respectively comprises a first vertical pillar; and a first set of lower plates extending from two sides of the first vertical pillar and parallel to a first direction. The plurality of second lower branch units respectively comprises a second vertical pillar; a first set of lower plates extending from two sides of the second vertical pillar, parallel to the first direction, and partially overlapping with the first set of lower plates of the first lower branch units in a top view to configure a programmable structure.

[0023] In some embodiments, the plurality of first lower branch units respectively comprises a second set of lower plates extending from other two sides of the first vertical pillar and parallel to a second direction perpendicular to the first direction. The plurality of second lower branch units respectively comprises a second set of lower plates extending from other two sides of the second vertical pillar, parallel to the second direction, and partially overlapping with the second set of lower plates of the first lower branch units in a top view to configure another programmable structure.

[0024] In some embodiments, the method of fabricating a semiconductor element further comprises forming a plurality of first upper branch units on the plurality of first lower branch units at a third vertical level higher than the second vertical level and electrically coupled to the plurality of first lower branch units. The plurality of first upper branch units respectively comprises a first set of upper plates extending from other two sides of the first vertical pillar and parallel to a third direction oblique to the first direction.

[0025] In some embodiments, the method of fabricating a semiconductor element further comprises forming a second isolation layer to cover the plurality of first upper branch units; and forming a plurality of first intermediate branch units on the second isolation layer at a fourth vertical level higher than the third vertical level. The plurality of first intermediate branch units respectively comprises a first vertical pillar; and a first set of intermediate plates extending from two sides of the third vertical pillar, parallel to the third direction, and partially overlapping with the first set of upper plates of the first upper branch units in a top view to configure another programmable structure.

[0026] Due to the design of the semiconductor element of the present disclosure, each electrode can provide multiple programmable architectures in a limited wafer area through a branched programmable structure. Thus, the space of the semiconductor element can be saved.

[0027] The foregoing has outlined rather broadly the technical features of the technology of the present disclosure in order that the detailed description of the present disclosure that follows can be better understood. Additional technical features and advantages of the present disclosure will be described hereinafter that form the subject of the claims of the present disclosure. It should be appreciated by those skilled in the art that the conception and specific embodiments disclosed can be readily utilized as a basis for modifying or designing other structures or processes for carrying out the same purposes of the present disclosure. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the present disclosure as set forth in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0028] The disclosure of the present application can be more fully understood with the following detailed description in conjunction with the accompanying drawings, in which like reference numerals refer to like elements in which:

[0029] FIG. 1 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor element according to an embodiment of the present disclosure.

[0030] FIG. 2 is a sectional view schematic diagram illustrating a section along the section line A-A' of FIG. 1 .

[0031] FIG. 3 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor element according to an embodiment of the present disclosure.

[0032] FIG. 4 is a sectional view schematic diagram illustrating a section along the section line A-A' of FIG. 3 .

[0033] FIG. 5 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor element according to an embodiment of the present disclosure.

[0034] FIG. 6 is a sectional view schematic diagram illustrating a section along the section line A-A' of FIG. 5 .

[0035] FIG. 7 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor element according to an embodiment of the present disclosure.

[0036] FIG. 8 is a sectional view schematic diagram illustrating a section along the section line A-A' of FIG. 7 .

[0037] FIG. 9is a flowchart illustrating a method of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0038] FIG. 10 is a top view illustrating a part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0039] FIG. 11 is a top view illustrating a part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0040] FIG. 12 and FIG. 13 is a sectional view illustrating a section along the section lines A-A' and B-B' of FIG. 8 .

[0041] FIG. 14 is a top view illustrating a part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0042] FIG. 15 and FIG. 16 is a sectional view illustrating a section along the section lines A-A' and B-B' of FIG. 14 .

[0043] FIG. 17 is a top view illustrating a part of a flow of manufacturing a semiconductor device 1B according to another embodiment of the present disclosure.

[0044] FIG. 18 and FIG. 19 is a sectional view illustrating a section along the section lines A-A' and B-B' of FIG. 17 .

[0045] FIG. 20 is a top view illustrating a part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0046] FIG. 21 and FIG. 22 is a sectional view illustrating a section along the section lines A-A' and B-B' of FIG. 20 .

[0047] FIG. 23 is a top view illustrating a part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0048] FIG. 24 and FIG. 25 is a sectional view illustrating a section along the section lines A-A' and B-B' of FIG. 23 .

[0049] FIG. 26 is a top view illustrating a part of a flow of manufacturing a semiconductor device according to another embodiment of the present disclosure.

[0050] FIG. 27 and FIG. 28 This is a sectional view, illustrating along... FIG. 26 The cross-sections A-A' and B-B'.

[0051] FIG. 29 This is a top view schematic diagram illustrating part of the process for fabricating a semiconductor device according to another embodiment of this disclosure.

[0052] FIG. 30 and FIG. 31 This is a sectional view, illustrating along... FIG. 29 The cross-sections A-A' and B-B'.

[0053] FIG. 32 This is a top view schematic diagram illustrating part of the process for fabricating a semiconductor device according to another embodiment of this disclosure.

[0054] FIG. 33 and FIG. 34 This is a sectional view, illustrating along... FIG. 32 The cross-sections A-A' and B-B'.

[0055] FIG. 35 This is a top view schematic diagram illustrating part of the process for fabricating a semiconductor device according to another embodiment of this disclosure.

[0056] FIG. 36 and FIG. 37 This is a sectional view, illustrating along... FIG. 35 The cross-sections A-A' and B-B'.

[0057] Explanation of reference numerals in the attached figures:

[0058] 1A: Semiconductor components

[0059] 1B: Semiconductor components

[0060] 100: First electrode

[0061] 100vc: First vertical column

[0062] 101: First lower branch unit

[0063] 101a: First set of lower plates

[0064] 101b: Second group of lower plates

[0065] 101c: Center plate

[0066] 103: First upper branch unit

[0067] 103a: First set of upper boards

[0068] 103b: Second group, upper board

[0069] 103c: center plate

[0070] 105a: first connection via

[0071] 105b: first connection via

[0072] 105c: first connection via

[0073] 105d: first connection via

[0074] 105e: first connection via

[0075] 105f: first connection via

[0076] 105g: first connection via

[0077] 105h: first connection via

[0078] 200: second electrode

[0079] 200vc: second vertical column

[0080] 201: second lower branch unit

[0081] 201a: first set of lower plates

[0082] 201c: center plate

[0083] 203: second upper branch unit

[0084] 203a: first set of upper plates

[0085] 203b: second set of upper plates

[0086] 203c: center plate

[0087] 205a: second connection via

[0088] 205b: second connection via

[0089] 205c: second connection via

[0090] 205d: second connection via

[0091] 205e: second connection via

[0092] 205f: second connection via

[0093] 205g: second connection via

[0094] 205h: second connection via

[0095] 300: third electrode

[0096] 300vc: third vertical column

[0097] 301: first intermediate branch unit

[0098] 301a: first set of intermediate plates

[0099] 301b: second set of intermediate plates

[0100] 301c: center plate

[0101] 305a: third connection via

[0102] 305b: third connection via

[0103] 305c: third connection via

[0104] 305d: third connection via

[0105] 305e: third connection via

[0106] 400: fourth electrode

[0107] 400vc: fourth vertical column

[0108] 401: second intermediate branch unit

[0109] 401a: first set of intermediate plates

[0110] 401b: second set of intermediate plates

[0111] 401c: center plate

[0112] 405a: fourth connection via

[0113] 405b: fourth connection via

[0114] 405c: fourth connection via

[0115] 405d: fourth connection via

[0116] 405e: fourth connection via

[0117] 501: first isolation layer

[0118] 503: second isolation layer

[0119] 505: third isolation layer

[0120] 601: dielectric layer

[0121] 603: dielectric layer

[0122] 605: dielectric layer

[0123] 607: dielectric layer

[0124] 609: dielectric layer

[0125] 611: dielectric layer

[0126] 613: dielectric layer

[0127] 701: substrate

[0128] DR1: first direction

[0129] DR2: second direction

[0130] DR3: third direction

[0131] DR4: third direction

[0132] S11: step

[0133] S13: step

[0134] S15: step

[0135] S17: step

[0136] S19: step

[0137] X: direction

[0138] Y: direction

[0139] Z: direction DETAILED DESCRIPTION

[0140] The following description describes specific examples of components and configurations to simplify the present disclosure. These examples are merely intended to facilitate description of the aspects of the present disclosure and are in no way limiting. For example, although a first component is described as being formed on a second component, the example can include instances where the first component is formed directly on the second component, and also include instances where additional components are formed between the first and second components such that the first and second components are not in direct contact. Additionally, the embodiments of the present disclosure can repeatedly refer to reference numerals and / or letters in many examples. These repetitions are for the purpose of simplification and clarity, and do not inherently represent a particular relationship between the various embodiments and / or the configurations being discussed, unless specifically stated otherwise in the context.

[0141] Moreover, spatially relative terms, such as "beneath", "below", "lower", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientation depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0142] It will be understood that when a component is referred to as being "on" or "connected to" another component, it can be directly on or connected to the other component or intervening components can be present. In contrast, when a component is referred to as being "directly on" or "directly connected to" another component, there are no intervening components present.

[0143] It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and sections, these elements, components, regions, layers and sections should not be limited by these terms. Rather, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present disclosure.

[0144] It will be understood that, in the description of the present disclosure, an x-y-z coordinate system is assumed in which x and y represent dimensions in a plane parallel to a major surface of the structure, and z represents a dimension perpendicular to the plane.

[0145] It will be understood that, in the description of the present disclosure, above (or up) corresponds to the direction of the Z-direction arrow, and below (or down) corresponds to the opposite direction of the Z-direction arrow.

[0146] FIG. 9 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor device 1A according to an embodiment of the present disclosure. FIG. 1 is a cross-sectional view schematic diagram illustrating a cross-section along the cross-sectional line A-A' of FIG. 2 .

[0147] Reference is made to FIG. 1 and FIG. 2A substrate 701 can be provided. For example, the substrate 701 can include an elemental semiconductor or a compound semiconductor, where the elemental semiconductor is, for example, silicon or germanium, and the compound semiconductor is, for example, silicon germanium.

[0148] Referring to FIG. 1 and FIG. 2 A dielectric layer 601 can be formed on the substrate 701. For example, the dielectric layer 601 can include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorinated silicate glass, low-k dielectric material, the like, or a combination thereof.

[0149] In a cross-sectional view, a plurality of first connection vias 105a and a plurality of second connection vias 205a can be formed on the substrate 701 and in the dielectric layer 601. In a top view, the first connection vias 105a and the second connection vias 205a can be staggered along a direction X. The direction X can also be denoted as a first direction DR1. The first connection vias 105a can be disposed along a direction Y and can be spaced apart from each other. The second connection vias 205a can be disposed along the direction Y and can be spaced apart from each other. The direction Y can also be denoted as a second direction DR2. In some embodiments, the first connection vias 105a and the second connection vias 205a can be formed in a peripheral region of the substrate 701 or a redundant region of the substrate 701.

[0150] A plurality of device elements (not shown) can be formed on the substrate 701 and in the dielectric layer 603. The device elements can be transistors, such as complementary metal-oxide-semiconductor transistors, metal-oxide-semiconductor field-effect transistors, fin field-effect-transistors, the like, or combinations thereof. The device elements can be electrically coupled to form a plurality of functional units. In the description of the present disclosure, a functional unit generally represents a functionally associated logic circuit that has been separated into a distinct unit for a functional purpose. The functional units can be formed in a central region of the substrate 701. In some embodiments, the functional units can be electrically coupled to the first connection vias 105a and the second connection vias 205a. In some embodiments, the first connection vias 105a and the second connection vias 205a can be ground.

[0151] FIG. 3 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor element 1A according to an embodiment of the present disclosure. FIG. 4 is a cross-sectional view schematic diagram illustrating a cross-section along the cross-sectional line A-A’ of FIG. 3 .

[0152] Please refer to FIG. 3 and FIG. 4 , a dielectric layer 603 can be formed on the dielectric layer 601. A plurality of second connection vias 205b can be formed in the second connection vias 205a and in the dielectric layer 603, respectively.

[0153] A plurality of first lower branch units 101 can be formed on the first connection vias 105a, respectively. For the sake of brevity, clarity, and ease of description, only one first lower branch unit 101 is described. The first lower branch unit 101 can be formed at a first vertical level and can include a central plate 101c and a first set of lower plates 101a. The central plate 101c can be formed on the first connection via 105a. The first set of lower plates 101a can extend from both sides of the central plate 101c and be formed parallel to the first direction DR1. In some embodiments, the first set of lower plates 101a can extend from the central plate 101c and along two directions that intersect each other.

[0154] It should be understood that, in FIG. 3 and FIG. 4 , only one central plate 101c is shown in the first lower branch unit 101 for the sake of clarity.

[0155] FIG. 5 is a top view illustrating a partial process of fabricating a semiconductor device 1A according to an embodiment of the disclosure. FIG. 6 is a cross-sectional view illustrating a cross-section along the cross-sectional line A-A’ of FIG. 5 .

[0156] Referring to FIG. 5 and FIG. 6 , a first isolation layer 501 can be formed on the dielectric layer 603 to cover the first lower branch units 101 and the second connection via 205b. The first isolation layer 501 can have a thickness between about and about . In some embodiments, for example, the first isolation layer 501 can include silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, or a combination thereof. In some embodiments, for example, the first isolation layer 501 can include silicon nitride, carbon-doped oxide, carbon-incorporated silicon oxide, nitrogen-doped silicon carbide, or silicon oxycarbide. In some embodiments, the first isolation layer 501 can be an etch stop layer and can be easily integrated into a middle-end-of-line process or a back-end-of-line process.

[0157] Referring to FIG. 5 and FIG. 6 , a plurality of first connection vias 105b can be formed on the center plates 101c of the first lower branch units 101, respectively. A plurality of second connection vias 205c can be formed on the second connection via 205b, respectively. In some embodiments, in a top view, the second connection vias 205a, 205b, 205c can have shapes such as circular, elliptical, triangular, square, rectangular, diamond, parallelogram, polygon, or other suitable shapes. The second connection vias 205a, 205b, 205c can have mutually different shapes. In some embodiments, the second connection vias 205a, 205b, 205c can all have the same shape. In some embodiments, the second connection vias 205a, 205b, 205c can have different horizontal cross-sectional areas. In some embodiments, the second connection vias 205a, 205b, 205c can all have the same cross-sectional area. In the description of the disclosure, a horizontal cross-sectional area represents an area of a feature (or element) in a parallel x-y plane.

[0158] FIG. 7 is a top view illustrating a partial process of fabricating a semiconductor device 1A according to an embodiment of the disclosure. FIG. 8is a cross-sectional view illustrating a cross-section along the cross-sectional line A-A' of FIG. 7

[0159] Please refer to FIG. 7 and FIG. 8 A dielectric layer 605 can be formed on the first isolation layer 501 and cover the first connection vias 105b and the second connection vias 205c. A plurality of first connection vias 105c can be formed on the first connection vias 105b and in the dielectric layer 605, respectively. The first connection vias 105a, 105b, 105c and the center plate 101c of the first lower branch unit 101 together configure a first vertical column 100vc. The first vertical column 100vc and the first group of lower plates 101a of the first lower branch unit 101 together configure a first electrode 100.

[0160] In some embodiments, the first connection vias 105a, 105b, 105c can have different shapes from each other. In some embodiments, the first connection vias 105a, 105b, 105c can all have the same shape. In some embodiments, the first connection vias 105a, 105b, 105c can have different horizontal cross-sectional areas. In some embodiments, the first connection vias 105a, 105b, 105c can have the same horizontal cross-sectional area.

[0161] Please refer to FIG. 7 and FIG. 8 A plurality of second lower branch units 201 can be formed on the second connection vias 205c, respectively. For the sake of brevity, clarity and ease of description, only one second lower branch unit 201 is described. The second lower branch unit 201 can be formed at a second vertical level higher than a first vertical level. The second lower branch unit 201 can include a center plate 201c and a first group of lower plates 201a. The center plate 201c can be formed on the second connection via 205c. The center plate 201c and the second connection vias 205a, 205b, 205c together configure a second vertical column 200vc.

[0162] The first group of lower plates 201a can extend from both sides of the center plate 201c and be parallel to the direction of the first group of lower plates 101a of the first lower branch unit 101. In other words, the first group of lower plates 201a can extend along the first direction DR1. The second vertical column 200vc and the first group of lower plates 201a of the second lower branch unit 201 together configure a second electrode 200.

[0163] ​The fabrication of the first lower branch units 101 and the second lower branch units 201 can be easily integrated in a middle-of-line process or a back-end-of-line process. For example, the first lower branch units 101 and the second lower branch units 201 can be fabricated simultaneously with multiple layers of interlayer metal. That is, no additional process is needed to fabricate the first lower branch units 101 and the second lower branch units 201.

[0164] It should be appreciated that in FIG. 7 and FIG. 8 for clarity, only one center plate 201c is shown in the second lower branch unit 201.

[0165] For example, the first connection vias 105a, 105b, 105c, the second connection vias 205a, 205b, 205c, the first lower branch units 101, and the second lower branch units 201 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide (e.g., tantalum carbide, titanium carbide, tantalum manganese carbide), metal nitride (e.g., titanium nitride), transition metal aluminide, or a combination thereof.

[0166] Please refer to FIG. 8 and FIG. 9 In a top view, the first set of lower plates 201a of the second lower branch units 201 and the first set of lower plates 101a of the first lower branch units 101 can partially overlap. In a cross-sectional view, the first isolation layer 501 is disposed between the first set of lower plates 101a and the first set of lower plates 201a. The first isolation layer 501 and the overlapping first set of lower plates 101a of the first electrode 100 and the first set of lower plates 201a of the second electrode 200 together configure a programmable structure.

[0167] Please refer to FIG. 10In the schematic view of the first electrode 100, each side of the first set of lower plates 101a has two programmable states (On or Off). Thus, all four possible architectures can be used for the first electrode 100. For example, during a programming procedure, a programming voltage can be provided and applied to the second electrode 200 on the left side, and the first electrode 100 and the second electrode 200 on the right side can be grounded. The first isolation layer 501 (shown in dotted circle) sandwiched between the first set of lower plates 201a of the second electrode 200 on the left side and the first set of lower plates 101a of the first electrode 100 can be stressed under the programming voltage. Thus, the sandwiched portion of the first isolation layer 501 can break to form a continuous path connecting the first set of lower plates 201a of the second electrode 200 on the left side and the first set of lower plates 101a of the first electrode 100. In other words, the sandwiched portion of the first isolation layer 501 can be blown out (e.g., the programmable state is On). Conversely, the first isolation layer 501 sandwiched between the first set of lower plates 201a of the second electrode 200 on the right side and the first set of lower plates 101a of the first electrode 100 can still be inact (e.g., the programmable state is Off).

[0168] Due to the branched plates of the electrodes, each electrode can still provide multiple programmable architectures even within a limited wafer area. Thus, the actual space of the semiconductor device 1A can be saved.

[0169] FIG. 11 is a flowchart illustrating a method of fabricating a semiconductor device 1B according to another embodiment of the present disclosure. FIG. 12 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor device according to another embodiment of the present disclosure. FIG. 13 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor device 1B according to another embodiment of the present disclosure. FIG. 8 and FIG. 9 to FIG. 13 are cross-sectional schematic diagrams illustrating cross-sections along the cross-sectional lines A-A’ and B-B’ of FIG. 10 , respectively.

[0170] Referring to FIG. 1 , at step S11, a substrate 701 can be provided, and a plurality of first lower branched units 101 can be formed on the substrate 701.

[0171] Referring to FIG. 2 , a substrate 701 (not shown) and a dielectric layer 601 can have similar structures as FIG. 11 to FIG. 13 and FIG. 11 to FIG. 13The structures described, and the descriptions thereof, are not repeated herein. A plurality of first connection vias 105a and a plurality of second connection vias 205a can be formed on the substrate 701 and in the dielectric layer 601. In a top view, the first connection vias 105a can be orthogonally arranged and the second connection vias 205a can be orthogonally arranged. The first connection vias 105a and the second connection vias 205a can be alternately arranged along the first direction DR1 and the second direction DR2.

[0172] Referring to FIG. 14 A dielectric layer 603 can be formed on the dielectric layer 601 and cover the first connection vias 105a and the second connection vias 205a. A plurality of second connection vias 205b can be formed on the second connection vias 205a, respectively. A plurality of first lower branch units 101 can be formed on the first connection vias 105a and in the dielectric layer 603, respectively. For the sake of brevity, clarity, and ease of understanding, only one first lower branch unit 101 is described.

[0173] The first lower branch unit 101 can be formed at a first vertical level and can include a center plate 101c, a first set of lower plates 101a, and a second set of lower plates 101b. The center plate 101c can be formed on the first connection via 105a. The center plate 101c can have a shape, such as a circle, an ellipse, a triangle, a square, a rectangle, a diamond, a parallelogram, a polygon, or other suitable shape. In some embodiments, the center plate 101c can have a horizontal cross-sectional area that is different from a horizontal cross-sectional area of the first connection via 105a. In some embodiments, the center plate 101c and the first connection via 105a can have the same shape and can have the same horizontal cross-sectional area.

[0174] The first set of lower plates 101a can be formed extending from two sides of the center plate 101c and parallel to the first direction DR1. The second set of lower plates 101b can be formed extending from the other two sides of the center plate 101c and parallel to the second direction DR2. The first set of lower plates 101a and the second set of lower plates 101b can cross at the center plate 101c.

[0175] It should be understood that, in FIG. 15 for the sake of clarity, only one center plate 101c is shown in the first lower branch unit 101.

[0176] FIG. 16 is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor device 1B according to another embodiment of the present disclosure. FIG. 14 and FIG. 17 are cross-sectional view schematic diagrams illustrating cross-sections along the cross-sectional lines A-A’ and B-B’ of FIG. 18 . FIG. 19is a top view schematic diagram illustrating a partial flow of fabricating a semiconductor device 1B according to another embodiment of the present disclosure. FIG. 17 and FIG. 9 is a cross-sectional view schematic diagram illustrating a cross-section along the cross-sectional lines A-A’ and B-B’ of FIG. 14 to FIG. 19 .

[0177] Referring to FIG. 14 to FIG. 16 and FIG. 5 , at step S13, a first isolation layer 501 can be formed to cover the first lower branch units 101, and the second lower branch units 201 can be formed on the first isolation layer 501 and partially overlap the first lower branch units 101.

[0178] Referring to FIG. 6 , a first isolation layer 501 can be formed on the dielectric layer 603 to cover the first lower branch units 101 and the second connection vias 205b. The first isolation layer 501 can have a structure similar to that described in FIG. 14 to FIG. 16 and FIG. 17 to FIG. 19 , and the description thereof will not be repeated herein. In some embodiments, the first isolation layer 501 can be an etch stop layer and can be easily integrated into a middle-of-line process or a back-end-of-line process.

[0179] Referring to FIG. 17 to FIG. 19 , a plurality of first connection vias 105b can be respectively formed on the center plates 101c of the first lower branch units 101. The first connection vias 105b can be respectively electrically coupled to the first lower branch units 101. A plurality of second connection vias 205c can be respectively formed on the second connection vias 205b.

[0180] Referring to FIG. 17 to FIG. 19 , a dielectric layer 605 can be formed on the dielectric layer 603 to cover the first connection vias 105b and the second connection vias 205b. A plurality of first connection vias 105c can be respectively formed on the first connection vias 105b and in the dielectric layer 605. A plurality of second lower branch units 201 can be respectively formed on the second connection vias 205c and in the dielectric layer 605. For the sake of brevity, clarity, and ease of understanding, only one second lower branch unit 201 is described.

[0181] The second lower branch units 201 can be formed at a second vertical level higher than the first vertical level. The second lower branch units 201 can include a center plate 201c and a first set of lower plates 201a. The center plate 201c can be formed on the second connection vias 205c. The center plate 201c has a structure similar to that of the center plate 101c, and the description thereof will not be repeated herein.

[0182] The first set of lower plates 201a extends from both sides of the center plate 201c and is parallel to the direction of the first set of lower plates 101a of the first lower branch unit 101. In other words, the first set of lower plates 201a extends along the first direction DR1. The second set of lower plates 201b extends along the other two sides of the center plate 201c and is parallel to the direction of the second set of lower plates 101b of the first lower branch unit 101. In other words, the second set of lower plates 201b extends along the second direction DR2. The first set of lower plates 201a and the second set of lower plates 201b may intersect the center plate 201c.

[0183] Please refer to FIG. 20 In the top view, the first set of lower plates 201a of the second lower branch unit 201 and the first set of lower plates 101a of the first lower branch unit 101 may partially overlap. In the cross-sectional view, a first isolation layer 501 is disposed between the first set of lower plates 101a and the first set of lower plates 201a. The first isolation layer 501 and the overlapping portion of the first set of lower plates 101a of the first lower branch unit 101 and the first set of lower plates 201a of the second lower branch unit 201 are configured together into a programmable structure.

[0184] Please refer to FIG. 21 In the top view, the second set of lower plates 201b of the second lower branch unit 201 and the second set of lower plates 101b of the first lower branch unit 101 may partially overlap. In the cross-sectional view, a first isolation layer 501 is disposed between the second set of lower plates 101b and the second set of lower plates 201b. The first isolation layer 501 and the second set of lower plates 101b of the first branch unit 101 are configured together with the second set of lower plates 201b of the second lower branch unit 201 to form another programmable structure.

[0185] FIG. 22 This is a top view schematic diagram illustrating part of the process for fabricating semiconductor element 1B according to another embodiment of this disclosure. FIG. 20 and FIG. 23 This is a sectional view, illustrating along... FIG. 24 The cross-sections A-A' and B-B'. FIG. 25 This is a top view schematic diagram illustrating part of the process for fabricating semiconductor element 1B according to another embodiment of this disclosure. FIG. 23 and FIG. 9 This is a sectional view, illustrating along... FIG. 20 to FIG. 25 The cross-sections A-A' and B-B'.

[0186] Please refer to FIG. 20 to FIG. 22 and FIG. 20 to FIG. 22 In step S15, a plurality of first upper branch units 103 may be formed on a plurality of first lower branch units 101 and may be electrically coupled to the plurality of first lower branch units 101.

[0187] Please refer toFIG. 23 to FIG. 25 A dielectric layer 607 can be formed on the dielectric layer 605 and cover the first connection vias 105c and the second lower branch units 201. A plurality of first connection vias 105d can be formed corresponding to the first connection vias 105c and in the dielectric layer 607, respectively. A plurality of second connection vias 205d can be formed corresponding to the center plates 201c and in the dielectric layer 607, respectively.

[0188] Please refer to FIG. 23 to FIG. 25 A plurality of third connection vias 305a and a plurality of fourth connection vias 405a can be formed in the dielectric layer 607. In a top view, the third connection vias 305a can be orthogonally arranged. The third connection vias 305a can also be orthogonally arranged with the first connection vias 105d and the second connection vias 205d, respectively. The fourth connection vias 405a can be orthogonally arranged. The fourth connection vias 405a can also be orthogonally arranged with the first connection vias 105d and the second connection vias 205d, respectively. The third connection vias 305a and the fourth connection vias 405d can extend along the first direction DR1 and the second direction DR2 alternately. In some embodiments, a horizontal cross-sectional area of the third connection vias 305a or the fourth connection vias 405a can be smaller than a horizontal cross-sectional area of the first connection vias 105d or the second connection vias 205d.

[0189] In some embodiments, the third connection vias 305a and the fourth connection vias 405a can be formed along with the first connection vias 105a, 105b, 105c, 105d and the second connection vias 205a, 205b, 205c, 205d. In this case, a lower surface of each of the third connection vias 305a and the fourth connection vias 405a can contact the substrate 701. The third connection vias 305a, the fourth connection vias 405a, the first connection vias 105a, 105b, 105c, 105d and the second connection vias 205a, 205b, 205c, 205d formed simultaneously can reduce the number of masks for manufacturing the semiconductor element 1B. Therefore, the cost for manufacturing the semiconductor element 1B can be reduced.

[0190] Please refer to FIG. 26A dielectric layer 609 may be formed on the dielectric layer 607 and cover the first connection vias 105d, the second connection vias 205d, the third connection vias 305a, and the fourth connection vias 405a. A plurality of second connection vias 205e may be formed on the second connection vias 205d (not shown) and in the dielectric layer 609, respectively. A plurality of third connection vias 305b may be formed on the third connection vias 305a and in the dielectric layer 609, respectively. A plurality of fourth connection vias 405b may be formed on the fourth connection vias 405a and in the dielectric layer 609, respectively.

[0191] Please refer to FIG. 27 Multiple first upper branch units 103 may be respectively formed on the first connection vias 105d and in the dielectric layer 609. In some embodiments, no additional dielectric layer (e.g., dielectric layer 607) exists between the first upper branch units 103 and the second lower branch units 201. For the sake of brevity, clarity and ease of description, only one first upper branch unit 103 will be described.

[0192] The first upper branch unit 103 may be formed at a third vertical plane higher than the second vertical plane. The first upper branch unit 103 may include a center plate 103c, a first set of upper plates 103a, and a second set of upper plates 103b. The center plate 103c may be formed on the first connecting through hole 105d. The center plate 103c may have a structure similar to that of the center plate 101c, and its description will not be repeated herein.

[0193] The first set of upper plates 103a extends from both sides of the center plate 103c and is parallel to a third direction DR3. The third direction DR3 is inclined relative to the first direction DR1 and the second direction DR2. The second set of upper plates 103b extends along the other two sides of the center plate 103c and is parallel to a fourth direction DR4. The fourth direction DR4 is perpendicular to the third direction DR3. The first set of upper plates 103a and the second set of upper plates 103b may intersect the center plate 103c.

[0194] FIG. 28 This is a top view schematic diagram illustrating part of the process for fabricating semiconductor element 1B according to another embodiment of this disclosure. FIG. 26 and FIG. 29 This is a sectional view, illustrating along... FIG. 30 The cross-sections A-A' and B-B'. FIG. 31 This is a top view schematic diagram illustrating part of the process for fabricating semiconductor element 1B according to another embodiment of this disclosure. FIG. 29 and FIG. 9 This is a sectional view, illustrating along... FIG. 26 to FIG. 31 The cross-sections A-A' and B-B'.

[0195] Referring to FIG. 26 to FIG. 28 and FIG. 26 to FIG. 28 In step S17, a second isolation layer 503 can be formed to cover the first upper branch units 103. The first intermediate branch units 301 can be formed on the second isolation layer 503 and partially overlap the first upper branch units 103. The second intermediate branch units 401 can be formed on the second isolation layer 503 and partially overlap the first upper branch units 103.

[0196] Referring to FIG. 29 to FIG. 4 A second isolation layer 503 can be formed on the dielectric layer 609 to cover the first upper branch units 103, the second connection vias 205e, the third connection vias 305b and the fourth connection vias 405b. The second isolation layer 503 can have a similar structure to the first isolation layer 501, and the description thereof will not be repeated herein. In some embodiments, the second isolation layer 503 can be an etch stop layer and can be easily integrated into a middle-of-line process or a back-end-of-line process.

[0197] Referring to FIG. 29 to FIG. 31 The first connection vias 105e can be formed on the center plates 103c of the first lower branch units 101, respectively. The second connection vias 205f can be formed on the second connection vias 205e, respectively. The third connection vias 305c can be formed on the third connection vias 305b, respectively. The fourth connection vias 405c can be formed on the fourth connection vias 405b, respectively.

[0198] Referring to FIG. 29 to FIG. 31 31. A dielectric layer 611 can be formed on the dielectric layer 609 to cover the first connection vias 105e, the second connection vias 205f, the third connection vias 305c and the fourth connection vias 405c. The first connection vias 105f can be formed on the first connection vias 105e and in the dielectric layer 611, respectively. The second connection vias 205g can be formed on the second connection vias 205f and in the dielectric layer 611, respectively. The first intermediate branch units 301 can be formed on the third connection vias 305c and in the dielectric layer 611, respectively. For the sake of brevity, clarity and ease of description, only one first intermediate branch unit 301 is described. The second intermediate branch units 401 can be formed on the fourth connection vias 405c and in the dielectric layer 611, respectively. For the sake of brevity, clarity and ease of description, only one second intermediate branch unit 401 is described.

[0199] The first intermediate branch unit 301 can be formed at a fourth vertical level higher than the third vertical level. The first intermediate branch unit 301 can include a center plate 301c, a first set of intermediate plates 301a, and a second set of intermediate plates 301b. The center plate 301c can be formed on the third connection via 305c. The center plate 301c can have a structure similar to the center plate 101c, and the description thereof will not be repeated herein.

[0200] The first set of intermediate plates 301a can extend from both sides of the center plate 301c and be formed parallel to the direction of the first set of upper plates 103a of the first upper branch unit 103. In other words, the first set of intermediate plates 301a can extend along the third direction DR3. The second set of intermediate plates 301b can extend from the other two sides of the center plate 301c and be formed parallel to the fourth direction DR4. The first set of intermediate plates 301a and the second set of intermediate plates 301b can cross at the center plate 301c.

[0201] Referring to FIG. 32 In a top view, the first set of intermediate plates 301a of the first intermediate branch unit 301 and the first set of upper plates 103a of the first upper branch unit 103 can partially overlap. In a cross-sectional view, the second isolation layer 503 is disposed between the first set of upper plates 103a and the first set of intermediate plates 301a. The second isolation layer 503 and the overlapping first set of upper plates 103a of the first upper branch unit 103 and the first set of intermediate plates 301a of the first intermediate branch unit 301 together configure another programmable structure.

[0202] Referring to FIG. 33 The second intermediate branch unit 401 can be formed at the same level (e.g., the fourth vertical level) as the first intermediate branch unit 301. The second intermediate branch unit 401 can include a center plate 401c, a first set of intermediate plates 401a, and a second set of intermediate plates 401b. The center plate 401c can be formed on the fourth connection via 405c. The center plate 401c can have a structure similar to the center plate 101c, and the description thereof will not be repeated herein.

[0203] The first set of intermediate plates 401a can extend from both sides of the center plate 401c and be formed parallel to the third direction DR3. The second set of intermediate plates 401b can extend from the other two sides of the center plate 401c and be formed parallel to the direction of the second set of upper plates 103b of the first upper branch unit 103. In other words, the second set of intermediate plates 401b can extend along the fourth direction DR4. The first set of intermediate plates 401a and the second set of intermediate plates 401b can cross at the center plate 401c.

[0204] In the top view, the second set of middle plates 401b of the second intermediate branch units 401 and the second set of upper plates 103b of the first upper branch units 103 can partially overlap. In the cross-sectional view, the second isolation layer 503 is disposed between the second set of upper plates 103b and the second set of middle plates 401b. The second isolation layer 503 and the overlapping second set of upper plates 103b of the first upper branch units 103 and the second set of middle plates 401b of the second intermediate branch units 401 together configure another programmable structure.

[0205] FIG. 34 is a top view illustrating a partial flow of fabricating a semiconductor device 1B according to another embodiment of the disclosure. FIG. 32 and FIG. 35 is a cross-sectional view illustrating a cross-section along the cross-sectional lines A-A’ and B-B’ of FIG. 36 . FIG. 37 is a top view illustrating a partial flow of fabricating a semiconductor device 1B according to another embodiment of the disclosure. FIG. 35 and FIG. 9 is a cross-sectional view illustrating a cross-section along the cross-sectional lines A-A’ and B-B’ of FIG. 32 to FIG. 37 .

[0206] Please refer to FIG. 32 to FIG. 34 and FIG. 32 to FIG. 34 , at step S19, a third isolation layer 505 can be formed to cover the first and second intermediate branch units 301, 401, and the second upper branch units 203 can be formed on the third isolation layer 505, electrically coupled to the second lower branch units 201, and partially overlap the first and second intermediate branch units 301, 401.

[0207] Please refer to FIG. 35 to FIG. 37 , a third isolation layer 505 can be formed on the dielectric layer 611 to cover the first connection vias 105f, the second connection vias 205g, the first and second intermediate branch units 301, 401. The third isolation layer 505 can have a similar structure to the first isolation layer 501, and its description will not be repeated herein. In some embodiments, the third isolation layer 505 can be an etch stop layer and can be easily integrated into the middle-of-line process or the back-end-of-line process.

[0208] Please refer to FIG. 35 to FIG. 37The first connection via holes 105g can be formed on the first connection via holes 105f, respectively. The second connection via holes 205h can be formed on the second connection via holes 205g, respectively. The third connection via holes 305d can be formed on the center plates 301c of the first intermediate branch units 301, respectively. The fourth connection via holes 405d can be formed on the center plates 401c of the second intermediate branch units 401, respectively.

[0209] Please refer to FIG. 35 to FIG. 37 A dielectric layer 613 can be formed on the dielectric layer 611 to cover the first connection via holes 105g, the second connection via holes 205g, the third connection via holes 305d, and the fourth connection via holes 405d. First connection via holes 105h can be formed on the first connection via holes 105g and in the dielectric layer 613, respectively. Third connection via holes 305e can be formed on the third connection via holes 305d and in the dielectric layer 613, respectively. Fourth connection via holes 405e can be formed on the fourth connection via holes 405d and in the dielectric layer 613, respectively.

[0210] The first connection via holes 105a, 105b, 105c, 105d, 105e, 105f, 105g, 105h, the intermediate plate 101c, and the intermediate plate 103c together configure a first vertical column 100vc. The first vertical column 100vc, the first group of lower plates 101a, the second group of lower plates 101b, the first group of upper plates 103a, and the second group of upper plates 103b together configure a first electrode 100. The third connection via holes 305a, 305b, 305c, 305d, 305e, and the center plates 301c together configure a third vertical column 300vc. The third vertical column 300vc, the first group of intermediate plates 301a, and the second group of intermediate plates 301b together configure a third electrode 300. The fourth connection via holes 405a, 405b, 405c, 405d, 405e, and the center plates 401c together configure a fourth vertical column 400vc. The fourth vertical column 400vc, the first group of intermediate plates 401a, and the second group of intermediate plates 401b together configure a fourth electrode 400.

[0211] Please refer to FIG. 18 Second upper branch units 203 can be formed on the second connection via holes 205h and in the dielectric layer 613, respectively. For the sake of brevity, clarity, and ease of description, only one second upper branch unit 203 is described.

[0212] A second upper branch unit 203 can be formed at a fifth horizontal level higher than the fourth horizontal level. The second upper branch unit 203 can have a center plate 203c, a first set of upper plates 203a, and a second set of upper plates 203b. The center plate 203c can be formed on the second connection via 205h. The center plate 203c can have a structure similar to the center plate 101c, and the description thereof will not be repeated herein.

[0213] The first set of upper plates 203a can extend from both sides of the center plate 203c and be formed parallel to the direction of the first set of middle plates 401a of the second middle branch unit 401. In other words, the first set of upper plates 203a can extend along the third direction DR3. The second set of upper plates 203b can extend from the other two sides of the center plate 203c and be formed parallel to the direction of the second set of middle plates 301b of the first middle branch unit 301. In other words, the second set of upper plates 203b can extend along the fourth direction DR4. The first set of upper plates 203a and the second set of upper plates 203b intersect at the center plate 203c.

[0214] Please refer to FIG. 19 In a top view, the first set of upper plates 203a of the second upper branch unit 203 and the first set of middle plates 401a of the second middle branch unit 401 can partially overlap. In a cross-sectional view, the third isolation layer 505 can be disposed between the first set of upper plates 203a and the first set of middle plates 401a. The third isolation layer 505 and the overlapping first set of upper plates 203a of the second upper branch unit 203 and the first set of middle plates 401a of the second middle branch unit 401 together configure another programmable structure.

[0215] In a top view, the second set of upper plates 203b of the second upper branch unit 203 and the second set of middle plates 301b of the first middle branch unit 301 can partially overlap. In a cross-sectional view, the third isolation layer 505 can be disposed between the second set of upper plates 203b and the second set of middle plates 301b. The third isolation layer 505 and the overlapping second set of upper plates 203b of the second upper branch unit 203 and the second set of middle plates 301b of the first middle branch unit 301 together configure another programmable structure.

[0216] The second connection vias 205a, 205b, 205c, 205d, 205e, 205f, 205g, 205h, the center plate 201c, and the center plate 203c together configure a second vertical column 200vc. The second vertical column 200vc, the first set of lower plates 201a, the second set of lower plates 201b, the first set of upper plates 203a, and the second set of upper plates 203b together configure a second electrode 200.

[0217] Please refer to FIG. 36 , FIG. 37 , FIG. 8and ​ In the schematic view of the first electrode 100, each side of the first set of lower plates 101a, the second set of lower plates 101b, the first set of upper plates 103a, and the second set of upper plates 103b has two programmed states (On or Off). Thus, a total of 256 (e.g., 2 8 ) possible architectures can be utilized for the first electrode 100. For example, when programming a selected side of a selected electrode 100, a programming voltage can be applied to the selected electrode, and all other electrodes can be grounded. The programming procedure can be similar to the procedure as described in ​ , and the description thereof is not repeated herein.

[0218] From the disclosure of the embodiments of the semiconductor element 1A and the semiconductor element 1B, it should be understood that, depending on design requirements, some of the lower branch cells, the middle branch cells, and the upper branch cells, or some of the lower plates, the middle plates, or the upper plates can be optionally omitted. For example, the first upper branch cell 103 can be omitted. The remaining second set of upper plates 203b and the first middle branch cell 301 or the second middle branch cell 401 can be treated as capacitors.

[0219] Further, each set of plates of a branch cell (e.g., the first set of lower plates 101a and the second set of lower plates 101b of the first lower branch cell 101) can be formed at different vertical levels with an isolation layer (e.g., the first isolation layer 501) formed between each set of plates. In some embodiments, each set of plates can extend in different directions.

[0220] Due to the design of the semiconductor elements of the present disclosure, each electrode can provide multiple programming architectures in a limited wafer area. Thus, the space of the semiconductor element 1A / 1B can be saved.

[0221] While the present disclosure and its advantages have been disclosed in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. For example, many of the

[0222] Further, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein can be utilized according to the present disclosure. Accordingly, the appended claims are intended to cover all such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims

1. A semiconductor element, comprising: a first electrode, comprising: a first vertical pillar; and a first lower branch unit disposed at a first vertical level and comprising a first set of lower plates extending from opposite sides of the first vertical pillar and perpendicular to a first direction; two second electrodes disposed at two sides of the first electrode and each comprising: a second vertical pillar; and a second lower branch unit disposed at a second vertical level higher than the first vertical level and comprising a first set of lower plates extending from opposite sides of the second vertical pillar and parallel to the first direction; and a first isolation layer disposed between the first lower branch unit and the second lower branch unit; wherein in a top view, the first set of lower plates of the first lower branch unit partially overlap the first set of lower plates of the second lower branch unit; wherein the first electrode, the first isolation layer, and the second electrode together configure a programmable structure.

2. The semiconductor element of claim 1, wherein the first vertical pillar comprises a plurality of first connection vias stacked vertically and a center plate of the first lower branch unit, and the first set of lower plates of the first lower branch unit extend from the center plate of the first lower branch unit.

3. The semiconductor element of claim 2, wherein a shape of the center plate of the first lower branch unit in a top view is triangular, square, rectangular, polygonal, circular, or elliptical.

4. The semiconductor element of claim 3, wherein the first isolation layer is an etch stop layer.

5. The semiconductor element of claim 3, wherein the first set of lower plates comprises tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide, a metal nitride, a transition metal aluminide, or a combination thereof.

6. The semiconductor element of claim 5, wherein the first isolation layer comprises silicon oxide, silicon nitride, silicon oxynitride, nitrided silicon oxide, or a combination thereof.

7. A semiconductor element, comprising: two first electrodes orthogonally configured and each comprising a first vertical pillar and a first lower branch unit disposed at a first vertical level and comprising a first set of lower plates extending from opposite sides of the first vertical pillar and parallel to a first direction and a second set of lower plates extending from other opposite sides of the first vertical pillar and parallel to a second direction perpendicular to the first direction; two second electrodes orthogonally disposed and comprising a second vertical pillar and a second lower branch unit disposed at a second level higher than the first vertical level and comprising a first set of lower plates extending from opposite sides of the second vertical pillar and parallel to the first direction and a second set of lower plates extending from other opposite sides of the second vertical pillar and parallel to the second direction, wherein in a top view, each first set of lower plates of the first lower branch unit and the second lower branch unit partially overlap, and in a top view, each second set of lower plates of the first lower branch unit and the second lower branch unit partially overlap; and a first isolation layer disposed between the first lower branch unit and the second lower branch unit. wherein the first electrode, the second electrode, and the first isolation layer together configure a programmable structure.

8. The semiconductor element of claim 7, wherein the two first electrodes each comprise a first upper branch unit disposed at a third vertical level higher than the second vertical level and comprising: a first set of upper plates extending from the other two opposite sides of the first vertical pillar and parallel to a third direction, the third direction being oblique to the first direction and the second direction; and a second set of upper plates extending from the other two opposite sides of the first vertical pillar and parallel to a fourth direction, the fourth direction being perpendicular to the third direction.

9. The semiconductor element of claim 8, further comprising a third electrode and a second isolation layer, wherein the third electrode comprises a third vertical pillar and a first intermediate branch unit disposed at a fourth vertical level and comprising: a first set of intermediate plates extending from the opposite sides of the third vertical pillar and parallel to the third direction; wherein the fourth vertical level is higher than the third vertical level; wherein in a top view, the first set of intermediate plates of the first intermediate branch unit partially overlap the first set of upper plates of the first upper branch unit; wherein the second isolation layer is disposed between the first upper branch unit and the first intermediate branch unit.

10. The semiconductor element of claim 9, wherein the first intermediate branch unit comprises a second set of intermediate plates extending from the other two opposite sides of the third vertical pillar and parallel to the fourth direction.

11. The semiconductor element of claim 10, further comprising a third isolation layer, wherein the two second electrodes each comprise a second upper branch unit disposed at a fifth vertical level and comprising: a first set of upper plates extending from the other two opposite sides of the second vertical pillar and parallel to the third direction; and a second set of upper plates extending from the other two opposite sides of the second vertical pillar and parallel to the fourth direction; wherein the fifth vertical level is higher than the fourth vertical level; wherein in a top view, the second set of upper plates of the second upper branch unit partially overlap the second set of intermediate plates of the first intermediate branch unit; wherein the third isolation layer is disposed between the second upper branch unit and the first intermediate branch unit.

12. The semiconductor element of claim 11, further comprising a fourth electrode comprising a fourth vertical pillar and a second intermediate branch unit disposed at the same vertical level as the first intermediate branch unit and comprising: a first set of intermediate plates extending from the opposite sides of the fourth vertical pillar and parallel to the third direction; wherein in a top view, the first set of intermediate plates of the second intermediate branch unit partially overlap the first set of upper plates of the second upper branch unit; wherein the third isolation layer is disposed between the second upper branch unit and the second intermediate branch unit. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 13. The semiconductor element of claim 12, wherein the second intermediate branch unit comprises a second set of intermediate plates extending from the other two opposite sides of the fourth vertical pillar and parallel to the fourth direction, wherein the second set of intermediate plates of the second intermediate branch unit partially overlaps the second set of upper plates of the first upper branch unit in a top view, wherein the second isolation layer is disposed between the first upper branch unit and the second intermediate branch unit.

14. The semiconductor element of claim 7, wherein a lower surface of the second vertical pillar contacts a substrate.

15. The semiconductor element of claim 9, wherein a lower surface of the third vertical pillar is disposed at a vertical level that is higher than a vertical level of a lower surface of the first vertical pillar.

16. The semiconductor element of claim 9, wherein a lower surface of the third vertical pillar contacts a substrate.

17. A method of fabricating a semiconductor element, comprising: forming a plurality of first lower branch units at a first vertical level and each comprising: a first vertical pillar; and a first set of lower plates extending from two sides of the first vertical pillar and parallel to a first direction; forming a first isolation layer to cover the plurality of first lower branch units; and forming a plurality of second lower branch units on the first isolation layer at a second vertical level higher than the first vertical level and each comprising: a second vertical pillar; a first set of lower plates extending from two sides of the second vertical pillar, parallel to the first direction, and partially overlapping the first set of lower plates of the first lower branch unit in a top view to configure into a programmable structure.

18. The method of fabricating a semiconductor element of claim 17, wherein the plurality of first lower branch units each comprises: a second set of lower plates extending from the other two sides of the first vertical pillar and parallel to a second direction that is perpendicular to the first direction; and wherein the plurality of second lower branch units each comprises: a second set of lower plates extending from the other two sides of the second vertical pillar, parallel to the second direction, and partially overlapping the second set of lower plates of the first lower branch unit in a top view to configure into another programmable structure.

19. The method of fabricating a semiconductor element of claim 17, further comprising: forming a plurality of first upper branch units on the plurality of first lower branch units at a third vertical level higher than the second vertical level, electrically coupled to the plurality of first lower branch units, and each comprising: a first set of upper plates extending from the other two sides of the first vertical pillar and parallel to a third direction that is inclined with respect to the first direction.

20. The method of fabricating a semiconductor element of claim 19, further comprising: forming a second isolation layer to cover the plurality of first upper branch units; and forming a plurality of first intermediate branch units on the second isolation layer at a fourth vertical level higher than the third vertical level and each comprising: a first vertical pillar; and a first set of intermediate plates extending from two sides of the third vertical pillar, parallel to the third direction, and partially overlapping the first set of upper plates of the first upper branch unit in a top view to configure into another programmable structure. ​ ​ ​

Images