Semiconductor element with test pad and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor element and a method of manufacturing the same. The semiconductor element has a substrate, a circuit layer disposed on the substrate and having a functional block disposed on the substrate and a test pad disposed on the substrate and away from the functional block, a redistribution structure disposed on the circuit layer and having a first conductive portion disposed on and electrically coupled to the functional block and a second conductive portion disposed on and electrically coupled to the test pad, and a semiconductor via physically and electrically coupled to the test pad.

Description

[0001] CROSS-REFERENCE

[0002] This application claims priority to and the benefit of U.S. Nonprovisional Application No. 17 / 228,131, filed April 12, 2021, the contents of which are incorporated herein by reference in their entirety. TECHNICAL FIELD

[0003] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device. In particular, a semiconductor device having a test pad and a method of manufacturing the semiconductor device having the test pad. BACKGROUND

[0004] Semiconductor devices are used in different electronic applications, such as personal computers, cell phones, digital cameras, or other electronic devices. The size of semiconductor devices is gradually reduced to meet the increasing demand for computing power. However, during the process of reducing the size, different problems are increased, and such problems continue to increase in number and complexity. Therefore, there are still challenges in achieving improved quality, yield, performance, and reliability, as well as reducing complexity.

[0005] The above description of background art is provided merely for better understanding of the present disclosure and should not be taken as an acknowledgement that the above description of background art presents relevant prior art that is widely known by those skilled in the art in this country or elsewhere. Any acknowledgement that the above description of background art presents relevant prior art that is widely known by those skilled in the art in this country or elsewhere is expressly disclaimed. SUMMARY

[0006] One embodiment of the present disclosure provides a semiconductor device, comprising a substrate; a circuit layer disposed on the substrate and comprising a functional block and a test pad, the functional block disposed on the substrate, the test pad disposed on the substrate and away from the functional block; a redistribution structure disposed on the circuit layer and comprising a first conductive portion and a second conductive portion, the first conductive portion disposed on the functional block and electrically coupled to the functional block, the second conductive portion disposed on the test pad and electrically coupled to the test pad; and a semiconductor via physically and electrically coupled to the test pad.

[0007] In some embodiments, the functional block and the first conductive portion of the redistribution structure are electrically coupled via a multilayer interconnect structure of the circuit layer.

[0008] In some embodiments, the first conductive portion of the redistribution structure and the second conductive portion of the redistribution structure are electrically coupled.

[0009] In some embodiments, the semiconductor element further comprises a first passivation layer disposed between the circuit layer and the redistribution structure. The first passivation layer comprises polybenzoxazole, polyimide, benzocyclobutene, ajinomoto buildup film, solder resist film, silicon oxynitride, silicon nitride oxide, phosphosilicate glass, borosilicate glass, or boron-doped phosphosilicate glass.

[0010] In some embodiments, the semiconductor via comprises a fill layer disposed along the first passivation layer and extending to the circuit layer; and two isolation layers disposed on two side edges of the fill layer, wherein the two isolation layers comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, parylene, epoxy, or poly(p-xylene).

[0011] In some embodiments, the semiconductor via comprises a seed layer disposed between the two isolation layers and the fill layer and between the fill layer and the test pad, and electrically coupled to the fill layer and the test pad.

[0012] In some embodiments, the semiconductor via comprises an adhesion layer disposed between the seed layer and the two isolation layers and between the seed layer and the test pad, and electrically coupled to the seed layer and the test pad, wherein the adhesion layer comprises titanium, tantalum, titanium tungsten, or manganese nitride.

[0013] In some embodiments, the semiconductor via comprises a barrier layer disposed between the adhesion layer and the two isolation layers and between the adhesion layer and the test pad, and electrically coupled to the adhesion layer and the test pad, wherein the barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum nitride / tantalum bilayer.

[0014] In some embodiments, each sidewall of the semiconductor via is tapered.

[0015] In some embodiments, the functional block comprises a complementary metal-oxide-semiconductor transistor, a metal-oxide-semiconductor field-effect transistor, or a fin field-effect-transistor, or the like.

[0016] In some embodiments, the redistribution structure comprises a first isolation layer disposed on the first passivation layer, and the first conductive portion and the second conductive portion are disposed in the first isolation layer, wherein the first isolation layer comprises polybenzoxazole, polyimide, benzocyclobutene, solder resist, silicon oxynitride, silicon nitride oxide, phosphosilicate glass, borosilicate glass, or boron-doped phosphosilicate glass.

[0017] In some embodiments, the second conductive portion of the redistribution structure comprises a conductor layer disposed in the first isolation layer and electrically coupled to the semiconductor via; and a barrier layer disposed between the first isolation layer and the conductor layer, between the circuit layer and the conductor layer, and between the semiconductor via and the conductor layer.

[0018] In some embodiments, the second conductive portion of the redistribution structure comprises a seed layer disposed between the conductor layer and the barrier layer.

[0019] In some embodiments, the semiconductor element further comprises a heat dissipation layer disposed under the substrate, wherein the heat dissipation layer comprises vertically oriented graphite and a plurality of carbon nanotubes.

[0020] In some embodiments, the semiconductor element further comprises an attachment layer disposed between the heat dissipation layer and the substrate. The attachment layer comprises a die attach film, a silver paste, or the like.

[0021] In some embodiments, the semiconductor element further comprises a plurality of first connectors disposed on the redistribution structure and respectively electrically coupled to the first conductive portion of the redistribution structure and the second conductive portion of the redistribution structure. The plurality of first connectors comprises a plurality of solder joints, a plurality of bumps, a plurality of pillar bumps, or the like.

[0022] In some embodiments, the semiconductor element further includes a plurality of under bump metallurgy layers respectively arranged between the plurality of first connectors and the redistribution structure.

[0023] In some embodiments, the semiconductor via includes two assistance layers respectively arranged between the two isolation layers and the filling layer, wherein each lowest point of the two assistance layers is arranged at a vertical level lower than a vertical level of a lower surface of the first passivation layer.

[0024] Another embodiment of the present disclosure provides a method of manufacturing a semiconductor element, including providing a substrate; forming a circuit layer on the substrate and including a functional block on the substrate; and a test pad on the substrate and away from the functional block; forming a semiconductor via to physically and electrically connect to the test pad; and forming a redistribution structure on the circuit layer and including a first conductive portion on the functional block and electrically coupled to the functional block; and a second conductive portion on the test pad and electrically coupled to the test pad via the semiconductor via.

[0025] In some embodiments, the method of manufacturing further includes forming a plurality of first connectors on the redistribution structure and respectively corresponding to the first conductive portion of the redistribution structure and the second conductive portion of the redistribution structure, wherein the plurality of first connectors include a plurality of solders, a plurality of bumps, a plurality of stud bumps, or the like.

[0026] Due to the design of the semiconductor element of the present disclosure, the semiconductor element can be combined with a test method that integrates intermediate and / or final verification of existing good dies. Therefore, the yield of manufacturing the semiconductor element can be improved, and the cost of manufacturing the semiconductor element can be reduced.

[0027] The foregoing has outlined rather broadly the technical features of the present disclosure in order that the detailed description of the present disclosure that follows can be understood. Other technical features and advantages of the present disclosure will be described in the detailed description of the present disclosure that follows. The technical features of the present disclosure should be construed as being merely illustrative of preferred embodiments of the present disclosure. Those skilled in the art should appreciate that the concept and scope of the present disclosure can be implemented in a variety of ways without departing from the spirit and scope of the present disclosure. Therefore, the technical features of the present disclosure should not be construed as being limited to the preferred embodiments described herein. BRIEF DESCRIPTION OF DRAWINGS

[0028] The disclosure of the present application can be more fully understood with the following detailed description when considered in connection with the following drawings, in which like characters refer to like elements.

[0029] FIG. 1is a flowchart illustrating a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0030] FIG. 2 and FIG. 3 is a cross-sectional view illustrating a part of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0031] FIG. 4 is an enlarged cross-sectional view illustrating a semiconductor via of a semiconductor element according to an embodiment of the present disclosure.

[0032] FIG. 5 is a cross-sectional view illustrating a part of a method of manufacturing a semiconductor element according to an embodiment of the present disclosure.

[0033] FIG. 6 is an enlarged cross-sectional view illustrating a second conductive portion of a semiconductor element according to an embodiment of the present disclosure.

[0034] FIG. 7 to FIG. 10 is a cross-sectional view illustrating a semiconductor element according to some embodiments of the present disclosure.

[0035] FIG. 11 to FIG. 13 is an enlarged cross-sectional view illustrating a flow of manufacturing a semiconductor via of a semiconductor element according to an embodiment of the present disclosure.

[0036] FIG. 14 and FIG. 15 is an enlarged cross-sectional view illustrating semiconductor vias of semiconductor elements according to some embodiments of the present disclosure.

[0037] BRIEF DESCRIPTION OF DRAWINGS

[0038] 10: method of manufacturing

[0039] 101: substrate

[0040] 103: circuit layer

[0041] 105: functional block

[0042] 107: test pad

[0043] 109: multilayer interconnection structure

[0044] 109-1: conductive plug

[0045] 109-3: conductive line

[0046] 109-5: conductive via

[0047] 109-7: conductive pad

[0048] 111: first passivation layer

[0049] 113: upper conductive via

[0050] 201: semiconductor via

[0051] 201SW: sidewall

[0052] 301: redistribution structure

[0053] 303: first isolation layer

[0054] 305: second isolation layer

[0055] 307: first conductive part

[0056] 309: second conductive part

[0057] 309-1: barrier layer

[0058] 309-3: seed layer

[0059] 309-5: conductor layer

[0060] 311: connection via

[0061] 313: first upper conductive layer

[0062] 315: second upper conductive layer

[0063] 317: third upper conductive layer

[0064] 401: heat dissipation layer

[0065] 403: attachment layer

[0066] 405: first connection

[0067] 407: second passivation layer

[0068] 409: under bump metallization layer

[0069] 415: auxiliary layer

[0070] 415BP: lowest point

[0071] AL: adhesion layer

[0072] BL: barrier layer

[0073] FL: filling layer

[0074] IL: isolation layer

[0075] OP1: first opening

[0076] OP2: second opening

[0077] OP3: third opening

[0078] S11: step

[0079] S13: step

[0080] S15: step

[0081] SD1A: semiconductor element

[0082] SD1B: semiconductor element

[0083] SD1C: semiconductor element

[0084] SD1D: semiconductor element

[0085] SD1E: semiconductor element

[0086] SL: seed layer

[0087] Z: direction DETAILED DESCRIPTION

[0088] The specific examples below are illustrative of suitable components and configurations for practicing embodiments of the present disclosure. Of course, those of ordinary skill in the art will recognize that many modifications can be made to the specific examples without departing from the scope of the present disclosure. For example, although the examples describe various components as being formed on or connected to other components, one of ordinary skill in the art will recognize that the components can be coupled to one another in any suitable manner. In addition, embodiments of the present disclosure can refer to a number of references by reference numeral and / or letter. These repeated references are intended to simplify and clarify the present disclosure, and are not meant to suggest that the various embodiments and / or configurations discussed in connection with them are in any way related.

[0089] In addition, for ease of explanation, spatially relative terms such as "beneath", "below", "lower", "above", "upper" and the like can be used herein for describing the orientation of one element or feature relative to another element or feature as shown in the figures. The spatially relative terms are intended to encompass different orientations of the elements in use or operation in addition to the orientations depicted in the figures. The devices can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0090] It will be understood that, when a component is referred to as being formed "on", "connected to", and / or "coupled to" another component, it can include embodiments where the components are directly in contact with each other, and where additional components can be interposed between the components.

[0091] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and sections, these elements, components, regions, layers and sections should not be limited by these terms. Instead, these terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0092] Unless otherwise indicated herein, when a term is represented by, for example, "the same," "equal," "planar," or "coplanar," as used herein, such terms do not necessarily mean an exact, identical orientation, layout, location, shape, size, amount, or other measure, but rather mean within acceptable variation, including nearly exact identical orientation, layout, location, shape, size, amount, or other measure, which can occur, for example, due to manufacturing processes. The term "substantially" can be used herein to convey this meaning. For example, substantially the same, substantially equal, or substantially planar, can be exact, equal, or planar, or can be within acceptable variation, including nearly exact, equal, or planar, which can occur, for example, due to manufacturing processes.

[0093] In the present disclosure, a semiconductor element generally means an element that can operate by utilizing semiconductor characteristics, and an electro-optic device, a light-emitting display device, a semiconductor circuit, and an electronic device are included in the range of semiconductor elements.

[0094] It should be understood that in the description of the disclosure, above (or up) corresponds to the direction of the Z-direction arrow, while below (or down) corresponds to the opposite direction of the Z-direction arrow.

[0095] It should be understood that the terms "forming", "formed" and "form" can represent and include any method of creating, building, patterning, implanting or depositing an element, a dopant or a material. Examples of forming methods can include, but are not limited to, atomic layer deposition, chemical vapor deposition, physical vapor deposition, sputtering, spin coating, diffusing, depositing, growing, implantation, photolithography, dry etching and wet etching.

[0096] It should be understood that in the description of the disclosure, the functions or steps mentioned herein can occur in an order different from that in each figure. For example, two figures shown successively can actually be performed substantially simultaneously, or sometimes in reverse order, depending on the functions or steps involved.

[0097] FIG. 1 is a flowchart illustrating a method 10 of manufacturing a semiconductor device SD1A according to an embodiment of the present disclosure. FIG. 2 and FIG. 3 is a sectional view illustrating a part of the method of manufacturing the semiconductor device SD1A according to an embodiment of the present disclosure. FIG. 4 is an enlarged sectional view illustrating a semiconductor via of the semiconductor device SD1A according to an embodiment of the present disclosure.

[0098] Please refer to FIG. 1 In step S11, a substrate 101 can be provided, and a circuit layer 103 can be formed on the substrate 101.

[0099] Please refer to FIG. 2The substrate 101 can include a bulk semiconductor substrate composed of at least one semiconductor material. For example, the bulk semiconductor can include an elemental semiconductor such as silicon or germanium, a compound semiconductor such as silicon germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, or other III-V compound semiconductor or II- VI compound semiconductor

[0100] In some embodiments, the substrate 101 can include a semiconductor-on-insulator composed of, from bottom to top, a handle substrate, an insulator layer, and an uppermost semiconductor material layer. The handle substrate and the uppermost semiconductor material layer include the same materials as the aforementioned bulk semiconductor substrate. The insulator layer can be a crystalline or non-crystalline dielectric material such as an oxide and / or nitride. For example, the insulator layer can be a dielectric oxide such as silicon oxide. As another example, the insulator layer can be a dielectric nitride such as silicon nitride or boron nitride. As yet another example, the insulator layer can include a stack of a dielectric oxide and a dielectric nitride such as a stack of silicon oxide and silicon nitride or boron nitride in any order. The insulator layer can have a thickness between about 10 nm and about 200 nm. The insulator layer can eliminate leakage current and reduce the parasitic capacitance of the semiconductor device SD1A.

[0101] It should be understood that the term "about" modifying the quantity of an ingredient, component described herein, or a reactant of a composition of this disclosure, means that the values can occur greater or less than the value stated in order to occur in the manner as described (for example, by typical measurement and liquid handling procedures used to manufacture concentrates or solutions). Furthermore, variations can occur in the manufacturing process, in the reaction process, or in the measurement process, which can result in variations in the final product. In one aspect, the term "about" means within 10% of the reported value. In another aspect, the term "about" means within 5% of the reported value. In yet another aspect, the term "about" means within 10, 9, 8, 7, 6, 5, 4, 3, 2, or 1% of the reported value.

[0102] Referring to FIG. 2 , a circuit layer 103 can be formed on the substrate 101. The circuit layer 103 can include a plurality of interlayer dielectric layers and / or a plurality of interlayer metal dielectric layers, which include a plurality of functional blocks 105, a multi-level interconnect structure 109, and a plurality of test pads 107. The plurality of functional blocks 105 can be transistors, such as complementary metal-oxide-semiconductor (CMOS) transistors, metal-oxide-semiconductor field-effect transistors (MOSFETs), or fin field-effect-transistors (FinFETs), the like, or combinations thereof. The plurality of functional blocks 105 can work together to perform a plurality of different functions, such as logic, input / output, analog circuitry, and the like.

[0103] The multi-level interconnect structure 109 can include a plurality of conductive plugs 109-1, a plurality of conductive lines 109-3, a plurality of conductive vias 109-5, and a plurality of conductive pads 109-7, or other suitable conductive elements. The plurality of conductive plugs 109-1 can be physically and electrically coupled to the plurality of functional blocks 105. The plurality of conductive lines 109-3 can be disposed apart from each other and can be horizontally disposed in the interlayer dielectric layers and / or the interlayer metal dielectric layers along a direction Z. In the description of the disclosure, the uppermost conductive lines 109-3 can be designated as the plurality of conductive pads 109-7. Each upper surface of the plurality of conductive pads 109-7 can be substantially coplanar with an upper surface of the circuit layer 103. The plurality of conductive vias 109-5 can connect adjacent conductive lines 109-3 along the direction Z. In some embodiments, the plurality of conductive vias 109-5 can improve heat dissipation in the circuit layer 103 and can provide structural support in the circuit layer 103.

[0104] It should be appreciated that the number of the conductive plugs 109-1, the conductive lines 109-3, the conductive vias 109-5, and the conductive pads 109-7 in the description of the disclosure is for illustrative purposes only. The number of the aforementioned conductive features can be more or less than the number as shown in FIG. 2 .

[0105] For example, the ILD layers and / or the ILMD layers can include silicon oxide, borophosphosilicate glass, undoped silicate glass, fluorosilicate glass, low-k dielectric materials, the like, or combinations thereof. The low-k dielectric materials can have a dielectric constant less than 3.0 or even less than 2.5. In some embodiments, the low-k dielectric materials can have a dielectric constant less than 2.0. Fabrication techniques for the ILD layers and / or the ILMD layers can include deposition processes such as chemical vapor deposition, plasma-enhanced chemical vapor deposition, or the like. After the deposition processes, planarization processes can be performed to remove excess material and provide a substantially planar surface for subsequent processing steps. During formation of the ILD layers and / or the ILMD layers, functional blocks 105 and multilayer interconnect structure 109 can be formed.

[0106] It should be understood that in the description of the disclosure, a surface is "substantially flat" if there is a horizontal plane from which the surface deviates no more than three times the root mean square roughness of the surface.

[0107] For example, multilayer interconnect structure 109 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbides (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), metal nitrides (e.g., titanium nitride), transition metal aluminides, or combinations thereof.

[0108] Test pads 107 can be formed on substrate 101 and disposed away from functional blocks 105. In some embodiments, in a top view, functional blocks 105 can be disposed at a central region of substrate 101, and test pads 107 can be disposed at a peripheral region of substrate 101. Test pads 107 can allow for testing of semiconductor elements SDA, use of probes and / or probe cards, and the like. Verification testing can be performed on intermediate and final structures. Furthermore, the structures and methods described in the disclosure can be used in conjunction with testing methods that incorporate intermediate and / or final verification of existing good dies to improve yield and reduce cost.

[0109] Referring to FIG. 1 , FIG. 3 and FIG. 4 at step S13, a semiconductor via 201 can be formed to electrically couple to test pads 107.

[0110] Referring to FIG. 3A first passivation layer 111 can be formed on the circuit layer 103. The first passivation layer 111 can be a single layer structure or a multi-layer structure. In some embodiments, the first passivation layer 111 can include polybenzoxazole, polyimide, benzocyclobutene, solder resist film, or the like, or a combination thereof. In some other embodiments, the first passivation layer 111 can be a dielectric layer. The dielectric layer can include a nitride, such as silicon nitride, an oxide, such as silicon oxide, an oxynitride, such as silicon oxynitride, nitrided silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or the like, or a combination thereof. For example, the fabrication techniques of the first passivation layer 111 can include spin coating, lamination, deposition, or the like. The deposition can include chemical vapor deposition. In some embodiments, the first passivation layer 111 can be designated as a portion of the interlayer dielectric layers and / or the interlayer metal dielectric layers of the circuit layer 103.

[0111] It should be appreciated that, in the description of the present disclosure, silicon oxynitride refers to a substance that includes silicon, nitrogen, and oxygen, and a ratio of oxygen is greater than a ratio of nitrogen. Nitrided silicon oxide refers to a substance that includes silicon, oxygen, and nitrogen, and a ratio of nitrogen is greater than a ratio of oxygen.

[0112] An upper conductive via 113 can be formed along the first passivation layer 111 and physically and electrically coupled to a corresponding conductive pad 109-7 of the multilayer interconnect structure 109. In other words, the upper conductive via 113 can be electrically coupled to the plurality of functional blocks 105 via the multilayer interconnect structure 109. For example, the upper conductive via 113 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, metal carbide, such as tantalum carbide, titanium carbide, tantalum magnesium carbide, metal nitride, such as titanium nitride, transition metal aluminide, or a combination thereof.

[0113] Referring to FIG. 3 A semiconductor via 201 can be formed along the first passivation layer 111, extending to the circuit layer 103, and physically and electrically coupled to a corresponding test pad 107. In some embodiments, each sidewall 201SW of the semiconductor via 201 can be substantially vertical. In some embodiments, each sidewall 201SW of the semiconductor via 201 can be tapered. For example, an angle between each sidewall 201SW of the semiconductor via 201 and an upper surface of the first passivation layer 111 can be between about 85 degrees and about 88 degrees.

[0114] Referring to FIG. 4The semiconductor via 201 can include a first opening OP1 formed to at least partially expose the corresponding test pad 107, and continue to fill the first opening OP1. In some embodiments, the semiconductor via 201 can include a fill layer FL, a seed layer SL, an adhesion layer AL, a barrier layer BL, and two isolation layers IL.

[0115] Referring to FIG. 4 The isolation material can be conformally formed on both sides of the first opening OP1 and on a bottom surface. A punch etch process can be performed to remove the isolation material formed on the bottom surface of the first opening OP1. The isolation material remaining on both sides of the first opening OP1 can be considered as two isolation layers IL. In some embodiments, for example, the two isolation layers IL can include silicon oxide, silicon nitride, silicon oxynitride, or tetra-ethyl ortho-silicate. The two isolation layers IL can have a thickness between about 50 nm and about 200 nm. Alternatively, in some embodiments, for example, the two isolation layers IL can include parylene, epoxy, or poly(p-xylene). The two isolation layers IL can have a thickness between about 1 μm and about 5 μm. The two isolation layers IL can ensure that the fill layer FL is electrically isolated from the first passivation layer 111 in the circuit layer 1032.

[0116] Referring to FIG. 4 The barrier layer BL can be conformally formed on the two isolation layers IL and on the bottom surface of the first opening OP1. The barrier layer BL can have a U-shaped cross-sectional profile. The barrier layer BL can be electrically coupled to the corresponding test pad 107. For example, the barrier layer BL can include tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or a bilayer of tantalum nitride / tantalum. The barrier layer BL can inhibit the conductive material of the fill layer FL from diffusing into the two isolation layers IL, the circuit layer 103, or the first passivation layer 111. The fabrication technique of the barrier layer BL can include a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering.

[0117] Referring to FIG. 4 The adhesion layer AL can be conformally formed on the barrier layer BL and can have a U-shaped cross-sectional profile. The adhesion layer AL can be electrically coupled to the barrier layer BL. For example, the adhesion layer AL can include titanium, tantalum, titanium tungsten, or manganese nitride. The adhesion layer AL can improve adhesion between the seed layer SL and the barrier layer BL. The adhesion layer AL can have a thickness between about 5 nm and about 50 nm. The fabrication technique of the adhesion layer AL can include a deposition process, such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering.

[0118] Referring toFIG. 4 A seed layer SL can be conformally formed on the adhesion layer AL and can have a U-shaped cross-sectional profile. The seed layer SL can be electrically coupled to the adhesion layer AL. The seed layer SL can have a thickness between about 10 nm and about 40 nm. For example, the seed layer SL can include copper or ruthenium. Fabrication techniques for the seed layer SL can include deposition processes such as physical vapor deposition, atomic layer deposition, chemical vapor deposition, or sputtering. The seed layer SL can reduce the resistivity of the first opening OP1 during formation of the fill layer FL by an electroplating process.

[0119] Please refer to FIG. 4 A fill layer FL can be formed on the seed layer SL and completely fill the first opening OP1. For example, the fill layer FL can be copper. Fabrication techniques for the fill layer FL can include an electroplating process using a plating solution. The plating solution can include copper sulfate, copper methanesulfonate, copper gluconate, copper sulfamate, copper nitrate, copper phosphate, or copper chloride. The plating solution can have a pH between about 2 and about 6, or between about 3 and about 5. The process temperature for the electroplating process can be maintained between about 40 °C and about 75 °C, or between about 50 °C and about 70 °C.

[0120] In some embodiments, the electroplating solution can include accelerators, suppressors, and levelers. Accelerators can include a polar sulfur, oxygen, or nitrogen functionality to help increase deposition rates and can promote dense nucleation. Accelerators can be present at a low concentration level, for example, between about 0 and about 200 ppm. Suppressors are additives that reduce plating rates and are typically present in the electroplating bath at higher concentrations, for example, between about 5 ppm and about 1000 ppm. Suppressors can be polymeric surfactants with high molecular weights, such as polyethylene glycol.

[0121] The suppressor can slow down the deposition rate by adsorbing on the surface and forming a barrier layer of copper ions. Because of its large size and low diffusivity, the suppressor is less likely to reach the lower portion of the first opening OP1. Thus, most of the suppressing effect can occur at the upper portion of the first opening OP1 to help reduce the overburden of the fill material (e.g., copper) and avoid the first opening OP1 from closing.

[0122] The leveling agent can be used to improve the filling performance, reduce the surface roughness, and avoid copper deposition at the upper portion of the first opening OP1. The leveling agent can be present at a small concentration, for example, between about 1 ppm and about 100 ppm. For example, the leveling agent can be 3-mercapto-1-propanesulfonate, (3-sulfopropyl)disulfide, or 3,3-thiobis(1-propanesulfonate).

[0123] FIG. 5 FIG. 1A is a schematic cross-sectional view illustrating a partial flow of fabricating a semiconductor device SD1A according to an embodiment of the present disclosure. FIG. 6 FIG. 1B is a schematic enlarged cross-sectional view illustrating a second conductive portion 309 of the semiconductor device SD1A according to an embodiment of the present disclosure.

[0124] Referring to FIG. 1 , FIG. 5 and FIG. 6 , at step S15, a redistribution structure 301 can be formed on the circuit layer 103 and include a first conductive portion 307 and a second conductive portion 309. The first conductive portion 307 can be formed on and electrically coupled to the functional blocks 105, and the second conductive portion 309 can be formed on and electrically coupled to the test pads 107.

[0125] Referring to FIG. 5 , the redistribution structure 301 can include a first isolation layer 303, a second isolation layer 305, the first conductive portion 307, the second conductive portion 309, a plurality of connection vias 311, a first upper conductive layer 313, and a second upper conductive layer 315.

[0126] Generally, the formation of redistribution structure 301 can include forming one or more isolation layers (e.g., first isolation layer 303 and second isolation layer 305) and forming a plurality of conductive features (e.g., first conductive portion 307, second conductive portion 309, a plurality of connection vias 311, first upper conductive layer 313, and second upper conductive layer 315) in the isolation layers using any suitable method (e.g., a spin-coating technique, sputtering, or the like). The formation of the conductive features can include patterning the isolation layers (e.g., using a lithography process and / or an etching process) and forming the conductive features in the patterned isolation layers (e.g., by depositing a seed layer, using a mask layer to define the shape of the conductive features, and using an electroless / electrochemical plating process).

[0127] Referring to FIG. 5 First isolation layer 303 can be formed on first passivation layer 111. In some embodiments, first isolation layer 303 can include polybenzoxazole, polyimide, benzocyclobutene, solder resist film, or the like, or a combination thereof. In some other embodiments, first isolation layer 303 can be a dielectric layer. The dielectric layer can include a nitride, an oxide, a nitride-oxide, or a combination thereof, such as silicon nitride, silicon oxide, silicon oxynitride, nitrided silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or the like. For example, the fabrication technique of first isolation layer 303 can include spin-coating, lamination, deposition, or the like. The deposition process can include chemical vapor deposition.

[0128] Referring to FIG. 5In some embodiments, a second isolation layer 305 can be formed on the first isolation layer 303. In some embodiments, the second isolation layer 305 can include polybenzoxazole, polyimide, benzocyclobutene, solder resist film, or the like, or a combination thereof. In some other embodiments, the second isolation layer 305 can be a dielectric layer. The dielectric layer can include a nitride, an oxide, an oxynitride, or a combination thereof, such as silicon nitride, silicon oxide, silicon oxynitride, nitrided silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, or the like. For example, the fabrication techniques of the second isolation layer 305 can include spin coating, lamination, deposition, or the like. The deposition process can include chemical vapor deposition. The first isolation layer 303 and the second isolation layer 305 can include the same material, but are not limited thereto.

[0129] Referring to FIG. 5 A first conductive portion 307 can be formed along the first isolation layer 303 and on the plurality of functional blocks 105. The first conductive portion 307 can be physically and electrically coupled to the upper conductive via 113. The first conductive portion 307 and the plurality of functional blocks 105 can be electrically coupled via the upper conductive via 113 and the multilayer interconnection structure 109. A second conductive portion 309 can be formed along the first isolation layer 303 and on the plurality of test pads 107. The second conductive portion 309 can be physically and electrically coupled to the semiconductor via 201. The second conductive portion 309 and the plurality of test pads 107 can be electrically coupled via the semiconductor via 201.

[0130] Referring to FIG. 5 A plurality of connection vias 311 can be formed in the second isolation layer 305. The plurality of connection vias 311 can respectively correspond to the first conductive portion 307 and the second conductive portion 309. The plurality of connection vias 311 can respectively correspond to the first conductive portion 307 and the second conductive portion 309. A first upper conductive layer 313 can be formed in the second isolation layer 305 and on the first conductive portion 307. The first upper conductive layer 313 can be electrically coupled to the first conductive portion 307 via the corresponding connection via 311. A second upper conductive layer 315 can be formed in the second isolation layer 305 and on the second conductive portion 309. The second upper conductive layer 315 can be electrically coupled to the second conductive portion 309 via the corresponding connection via 311.

[0131] For example, the first conductive portion 307, the second conductive portion 309, the plurality of connection vias 311, the first upper conductive layer 313, and the second upper conductive layer 315 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof.

[0132] Referring to FIG. 6 In some embodiments, the second conductive portion 309 can include a seed layer 309-3 and a conductor layer 309-5 formed on the seed layer 309-3. The seed layer 309-3 can be conformally formed on two sidewalls of a second opening OP2 and a lower surface in the first isolation layer 303. The seed layer 309-3 can be a metal seed layer, such as a copper seed layer. In some embodiments, the second conductive portion 309 can include a barrier layer 309-1, such as a titanium layer. The seed layer 309-3 can be conformally formed on the barrier layer 309-1. The conductor layer 309-5 can include copper or other suitable metal. In some embodiments, the first conductive portion 307 can have a structure similar to the second conductive portion 309.

[0133] FIG. 7 to FIG. 10 is a cross-sectional schematic view illustrating a semiconductor device SD1B, SD1C, SD1D, SD1E in accordance with some embodiments of the present disclosure.

[0134] Referring to FIG. 7 , the semiconductor device SD1B can have a structure similar to that described as in FIG. 5 . In FIG. 7 , elements that are the same or similar to those in FIG. 5 have been designated with like element numbers, and repetitive descriptions thereof have been omitted. The semiconductor device SD1B can include a third upper conductive layer 317 instead of the first upper conductive layer 313 and the second upper conductive layer 315 (as shown in FIG. 5 ). The third upper conductive layer 317 can be disposed in the second isolation layer 305 and on the plurality of connection vias 311. The third upper conductive layer 317 can be electrically coupled to the first conductive portion 307 and the second conductive portion 309 simultaneously via the plurality of connection vias 311. For example, the third upper conductive layer 317 can include tungsten, cobalt, zirconium, tantalum, titanium, aluminum, ruthenium, copper, a metal carbide (e.g., tantalum carbide, titanium carbide, tantalum magnesium carbide), a metal nitride (e.g., titanium nitride), a transition metal aluminide, or a combination thereof.

[0135] Referring to FIG. 8 , the semiconductor device SD1C can have a structure similar to that described as in FIG. 5 . In FIG. 8 , elements that are the same or similar to those in FIG. 5Elements in FIG. 10A have been designated with like reference numerals in the other figures, and description thereof has been omitted for the sake of brevity. The semiconductor device SD1C can have a heat spreading layer 401 and an attachment layer 403.

[0136] Referring to FIG. 8 , the heat spreading layer 401 can be disposed below the substrate 101. The attachment layer 403 can be used to attach the heat spreading layer 401 to the substrate 101. In some embodiments, the attachment layer 403 can include a die attach film, a silver paste, or the like. In some embodiments, the heat spreading layer 401 can include a composite material selected from the group consisting of silicon carbide, aluminum carbide, graphite, and the like. The heat spreading layer 401 can have a good thermal conductivity, which can be greater than about 2 W / m.K. In some embodiments, the heat spreading layer 401 can have a high thermal conductivity, which can be greater than about 100 W / m.K, and can include a metal, a metal alloy, or the like. For example, the heat spreading layer 401 can include a metal and / or a metal alloy selected from the group consisting of aluminum, copper, nickel, cobalt, and the like.

[0137] In some embodiments, the heat spreading layer 401 can include a carbon material filled with a flexible material, such as a polymer matrix. For example, the heat spreading layer 401 can generally include vertically oriented graphite and a plurality of nanotubes filled with a fluoropolymer rubber matrix. The aspect ratio of the nanotubes can be between about 1 : 1 and about 1 : 100. By way of further example, the heat spreading layer 401 can include graphitic carbon. By way of still further example, the heat spreading layer 401 can include a pyrolytic graphite sheet. In some embodiments, the heat spreading layer 401 can have a thermal resistance of less than 0.2 °C cm / W at a thickness between about 250 μm and about 450 μm. The heat spreading layer 401 can provide additional heat spreading capability for the semiconductor device SD1C. 2 / Watt, which can be less than 0.2 °C cm / W at a thickness between about 250 μm and about 450 μm. The heat spreading layer 401 can provide additional heat spreading capability for the semiconductor device SD1C.

[0138] Referring to FIG. 9 , the semiconductor device SD1D can have a structure similar to that described in FIG. 5 . In FIG. 9 , the semiconductor device SD1D can have a structure similar to that described in FIG. 5The elements in FIG. 10 have been designated with like reference numerals as in FIG. 9, and repetitive description thereof has been omitted. The semiconductor element SD1D can include a plurality of first connecting members 405. The plurality of first connecting members 405 can be respectively disposed on the first upper conductive layer 131 and the second upper conductive layer 315. In some embodiments, the plurality of first connecting members 405 can comprise a conductive material having a low resistivity, such as tin, lead, silver, copper, nickel, bismuth, or alloys thereof, and the plurality of first connecting members 405 can be formed by a suitable process, such as evaporation, plating, ball drop, or screen printing. In some embodiments, the plurality of first connecting members 405 can be formed by a C4 process.

[0139] In some embodiments, the plurality of first connecting members 405 can be solder joints. The solder joints can comprise a material, such as tin or other suitable material, such as silver or copper. In an embodiment in which the solder joints are tin solder joints, the solder joints can be formed by initially forming a layer of tin to a thickness of between about 10 μm and about 100 μm by evaporation, electroplating, printing, solder transfer, or ball placement. Once the layer of tin has been formed on the redistribution structure 301, a reflow process can be performed to shape the solder joints into a desired shape.

[0140] In some embodiments, the first connections 405 can be pillar bumps including copper, for example. The pillar bumps can be formed directly on the first and second upper conductive layers 313, 315 without the need for contact pads, under bump metallurgy, or the like, thus also reducing the cost and process complexity of the semiconductor device SD1D, which can allow for increased density of the pillar bumps. In some embodiments, for example, a critical dimension (e.g., pitch) of a pillar bump can be less than about 5 pm, and the pillar bump can have a height of less than about 10 pm. Fabrication techniques for the pillar bumps can use any suitable method, such as depositing a seed layer, optionally forming an under bump metallurgy, using a mask to define a shape of the pillar bumps, electrochemically plating the pillar bumps in the mask, and continuing to remove any undesired portions of the mask and the seed layer. The pillar bumps can be used to electrically connect the semiconductor device SD1D to other packaging elements, such as a fan-out redistribution layer, a package substrate, an interposer, a printed circuit board, and the like.

[0141] Referring to FIG. 10 , the semiconductor device SD1E can have a structure similar to that described in FIG. 9 . Elements in FIG. 10 that are the same as or similar to those in FIG. 9 have been designated with like element numbers, and repetitive descriptions thereof have been omitted. The semiconductor device SD1E can include a second passivation layer 407 and a plurality of under bump metallurgy layers 409.

[0142] Referring to FIG. 10 , the second passivation layer 407 can be disposed on the second isolation layer 305. In some embodiments, the second passivation layer 407 can include polybenzoxazole, polyimide, benzocyclobutene, solder resist, the like, or a combination thereof. In some other embodiments, the second passivation layer 407 can be a dielectric layer. The dielectric layer can include a nitride, such as silicon nitride, an oxide, such as silicon oxide, an oxynitride, such as silicon oxynitride, nitrided silicon oxide, phosphosilicate glass, borosilicate glass, boron-doped phosphosilicate glass, the like, or a combination thereof. Fabrication techniques for the second passivation layer 407 can include spin coating, lamination, deposition, or the like. The deposition process can include chemical vapor deposition.

[0143] Referring to FIG. 10A plurality of third openings OP3 can be respectively provided to expose the upper surface of the first upper conductive layer 313 and the upper surface of the second upper conductive layer 315. A plurality of under bump metal layers 409 can be respectively and conformally provided in the third openings OP3. The plurality of under bump metal layers 409 can be respectively and electrically coupled to the first upper conductive layer 313 and the second upper conductive layer 315. A plurality of first connecting members 405 can be respectively provided on the plurality of under bump metal layers 409.

[0144] The under bump metal layer 409 can be a single layer structure or a multi-layer stack structure. For example, the under bump metal layer 409 can include a first conductive layer, a second conductive layer, and a third conductive layer stacked in sequence. The first conductive layer can serve as an adhesion layer to stably attach the first connecting member 405 to the first upper conductive layer 313 or the second upper conductive layer 315. For example, the first conductive layer can include at least one of titanium, titanium tungsten, chromium, and aluminum. The second conductive layer can serve as a barrier layer to prevent a conductive material included in the plurality of first connecting members 405 from diffusing into the second passivation layer 407. The second conductive layer can include at least one of copper, nickel, chromium copper, and nickel vanadium. The third conductive layer can serve as a seed layer to form the plurality of first connecting members 405 or as a wetting layer to improve the wetting properties of the plurality of first connecting members 405. The third conductive layer can include at least one of nickel, copper, and aluminum.

[0145] FIG. 11 to FIG. 13 is a magnified cross-sectional view illustrating a process of forming a semiconductor via of a semiconductor device according to an embodiment of the disclosure.

[0146] Referring to FIG. 11 The first openings OP1 can be formed along the first passivation layer 111 and extend to the circuit layer 103. The upper surface of the test pad 107 is exposed via the first openings OP1. The inner walls of the first openings OP1 can be slightly tapered, for example, between about 85 degrees and about 88 degrees, and smoothly conformal and void-free material filling, as will be described later. The tapered inner walls of the first openings OP1 can also improve the diffusion of metal ions within the first openings OP1 and can reduce the time to fill the first openings OP1. In addition, the smooth inner walls of the first openings OP1 can benefit in reducing the stress concentration. It should be understood that the term "sidewalls" and the term "inner walls" can be used interchangeably in the description of the disclosure.

[0147] In some embodiments, the first opening OP1 can have a width between about 1 μm and about 22 μm, or between about 5 μm and about 15 μm. In some embodiments, the first opening OP1 can have a depth between about 20 μm and about 160 μm, or between about 50 μm and about 130 μm. For example, the first opening OP1 can be formed by laser drilling, powder blast micromaching, deep reactive ion etching, or wet etching using a hydroxide such as potassium hydroxide, sodium hydroxide, rubidium hydroxide, ammonium hydroxide, or tetra methyl ammonium hydroxide.

[0148] Referring to FIG. 11 , the two isolation layers IL can be formed by a process similar to that described in FIG. 4 . The two auxiliary layers 415 can be conformally formed on the upper portions of the first openings OP1, respectively corresponding to the attachment on the two isolation layers IL, and on the upper surface of the first passivation layer 111. The lowest points 415BP of the two auxiliary layers 415 can be disposed at a vertical level lower than a vertical level of the lower surface of the first passivation layer 111.

[0149] Atomic layer deposition is a self-limiting, sequential monolayer-by- monolayer thin film growth technique based on surface reactions that can provide atomic layer control and deposit conformal thin films of materials provided by multiple precursors onto substrates of varying composition. In atomic layer deposition, the precursors are separated during the reaction. The first precursor passes over the substrate, which produces a monolayer on it. Any excess unreacted precursor is purged away. Then, a second precursor passes over the substrate and reacts with the first precursor to form a monolayer film on the substrate surface. This cycle is repeated to produce a film of desired thickness.

[0150] The two auxiliary layers 415 can be formed by a deposition process, such as an atomic layer deposition method, precisely controlling the amount of a first precursor of the atomic layer deposition method. For example, the two auxiliary layers 415 can include aluminum oxide, hafnium oxide, zirconium oxide, titanium oxide, titanium nitride, tungsten nitride, silicon nitride, or silicon oxide.

[0151] In some embodiments, when the second auxiliary layer 415 comprises aluminum oxide, the first precursor of the atomic layer deposition process can be trimethylaluminum and the second precursor of the atomic layer deposition process can be water or ozone.

[0152] In some embodiments, when the second auxiliary layer 415 comprises hafnium oxide, the first precursor of the atomic layer deposition process can be hafnium tetrachloride, hafnium tert-butoxide, hafnium dimethylamide, hafnium ethylmethylamide, hafnium diethylamide, or hafnium methoxy-t-butoxide and the second precursor of the atomic layer deposition process can be water or ozone.

[0153] In some embodiments, when the second auxiliary layer 415 comprises zirconium oxide, the first precursor of the atomic layer deposition process can be zirconium tetrachloride and the second precursor of the atomic layer deposition process can be water or ozone.

[0154] In some embodiments, when the second auxiliary layer 415 comprises titanium oxide, the first precursor of the atomic layer deposition process can be titanium tetrachloride, tetraethyl titanate, or titanium isopropoxide and the second precursor of the atomic layer deposition process can be water or ozone.

[0155] In some embodiments, when the second auxiliary layer 415 comprises titanium nitride, the first precursor of the atomic layer deposition process can be titanium tetrachloride and ammonia.

[0156] In some embodiments, when the second auxiliary layer 415 comprises tungsten nitride, the first precursor of the atomic layer deposition process can be tungsten hexafluoride and ammonia.

[0157] In some embodiments, when the second auxiliary layer 415 comprises silicon nitride, the first precursor of the atomic layer deposition process can be silylene, chlorine, ammonia, and dinitrogen tetrahydride.

[0158] In some embodiments, when the second auxiliary layer 415 comprises silicon oxide, then the first precursor of the atomic layer deposition process can be silicon tetraisocyanate or CH3OSi(NCO)3, and the second precursor of the atomic layer deposition process can be hydrogen or ozone.

[0159] Referring to FIG. 12 The fill layer FL can be deposited to completely fill the first opening OP1 and cover the second auxiliary layer 415. Due to the presence of the second auxiliary layer 415, the deposition rate of the fill material of the fill layer FL on the inner walls of the first opening OP1 can be reduced. Thus, the deposition rate of the fill material of the fill layer FL on the inner walls of the first opening OP1 and the deposition rate of the fill material of the fill layer FL on the lower surface of the first opening OP1 can become close to each other. As a result, the first opening OP1 can be filled without any voids adjacent to the lower surface of the first opening OP1.

[0160] Referring to FIG. 13 A planarization process, such as chemical mechanical polishing, can be performed until the upper surface of the first passivation layer 111 is exposed to remove excess material and provide a substantially planar surface for the next processing steps.

[0161] FIG. 14 and FIG. 15 are enlarged cross-sectional schematic views illustrating the semiconductor via of the semiconductor element of some embodiments of the present disclosure.

[0162] Referring to FIG. 14 , the semiconductor via 201 can have a structure similar to that described in FIG. 13 . The same or similar elements in FIG. 14 as in FIG. 13 have been designated with like element numbers and repetitive descriptions thereof have been omitted. The main difference in FIG. 14 is that the second isolation layer IL (as shown in FIG. 13 ) can be omitted. The second auxiliary layer 415 can be directly attached on the inner walls of the first opening OP1. The bottom points 415BP can replace the second isolation layer IL to ensure the electrical insulation of the semiconductor via 201. In some embodiments, the bottom points 415BP can not contact the upper surface of the test pad 107.

[0163] Referring to FIG. 15 , the semiconductor via 201 can have a structure similar to that described in FIG. 4 . The same or similar elements in FIG. 15 as in FIG. 4The elements in the figures can have the same reference numbers in different figures and can be described with the same or similar terminology throughout the specification. The two auxiliary layers 415 can correspond to the two isolation layers IL, respectively. That is, the two auxiliary layers 415 can be disposed between the barrier layer BL and the two isolation layers IL.

[0164] One embodiment of the present disclosure provides a semiconductor device, comprising a substrate; a circuit layer disposed on the substrate and comprising a functional block disposed on the substrate and a test pad disposed on the substrate and away from the functional block; a redistribution structure disposed on the circuit layer and comprising a first conductive portion disposed on the functional block and electrically coupled to the functional block and a second conductive portion disposed on the test pad and electrically coupled to the test pad; and a semiconductor via physically and electrically coupled to the test pad.

[0165] Another embodiment of the present disclosure provides a method of manufacturing a semiconductor device, comprising providing a substrate; forming a circuit layer on the substrate and comprising a functional block on the substrate and a test pad on the substrate and away from the functional block; forming a semiconductor via to be physically and electrically connected to the test pad; and forming a redistribution structure on the circuit layer and comprising a first conductive portion on the functional block and electrically coupled to the functional block and a second conductive portion on the test pad and electrically coupled to the test pad via the semiconductor via.

[0166] Due to the design of the semiconductor device of the present disclosure, the semiconductor device SD1A can be combined with the test method that integrates the intermediate and / or final verification of the existing good dies. Therefore, the yield of manufacturing the semiconductor device SD1A can be improved, and the cost of manufacturing the semiconductor device SD1A can be reduced.

[0167] While the present disclosure and the best mode thereof have been described in detail, it should be understood that various changes, substitutions and alterations can be made hereto without departing from the spirit and scope of the present disclosure as defined by the appended claims. For example, various processes described above can be implemented in different manners, and various processes described above can be replaced with other processes or combinations thereof.

[0168] Further, the scope of the present disclosure is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Accordingly, the disclosure of one or more embodiments of the present disclosure is intended to be illustrative, but not limiting, of the scope of the present disclosure. Thus, the scope of the present disclosure should be interpreted by reference to the claims.

Claims

1. A semiconductor device, comprising: a substrate; a circuit layer disposed on the substrate and comprising: a functional block disposed on the substrate; and a test pad disposed on the substrate and away from the functional block; a redistribution structure disposed on the circuit layer and comprising: a first conductive portion disposed on and electrically coupled to the functional block; and a second conductive portion disposed on and electrically coupled to the test pad; and a semiconductor via physically and electrically coupled to the test pad, wherein the functional block and the first conductive portion of the redistribution structure are electrically coupled via a multilayer interconnect structure of the circuit layer.

2. The semiconductor device of claim 1, wherein the first conductive portion of the redistribution structure and the second conductive portion of the redistribution structure are electrically coupled.

3. The semiconductor device of claim 1, further comprising a first passivation layer disposed between the circuit layer and the redistribution structure, wherein the first passivation layer comprises polybenzoxazole, polyimide, benzocyclobutene, Ajinomoto build-up film, solder resist, silicon oxynitride, silicon nitride oxide, phosphosilicate glass, borosilicate glass, or boron-doped phosphosilicate glass.

4. The semiconductor device of claim 3, wherein the semiconductor via comprises: a fill layer disposed along the first passivation layer and extending to the circuit layer; and two isolation layers disposed on two side edges of the fill layer, wherein the two isolation layers comprise silicon oxide, silicon nitride, silicon oxynitride, tetraethoxysilane, parylene, epoxy, or parylene.

5. The semiconductor device of claim 4, wherein the semiconductor via comprises a seed layer disposed between the two isolation layers and the fill layer and between the fill layer and the test pad, and electrically coupled to the fill layer and the test pad.

6. The semiconductor device of claim 5, wherein the semiconductor via comprises an adhesion layer disposed between the seed layer and the two isolation layers and between the seed layer and the test pad, and electrically coupled to the seed layer and the test pad, wherein the adhesion layer comprises titanium, tantalum, titanium tungsten, or manganese nitride.

7. The semiconductor device of claim 6, wherein the semiconductor via comprises a barrier layer disposed between the adhesion layer and the two isolation layers and between the adhesion layer and the test pad, and electrically coupled to the adhesion layer and the test pad, wherein the barrier layer comprises tantalum, tantalum nitride, titanium, titanium nitride, rhenium, nickel boride, or tantalum / tantalum nitride bilayer.

8. The semiconductor device of claim 3, wherein sidewalls of the semiconductor via are tapered.

9. The semiconductor device of claim 3, wherein the functional block comprises a complementary metal-oxide-semiconductor, a metal-oxide-semiconductor field-effect transistor, or a fin field-effect transistor, or the like. ​ 10. The semiconductor device of claim 3, wherein the redistribution structure comprises a first isolation layer disposed on the first passivation layer, and the first conductive portion and the second conductive portion are disposed in the first isolation layer, wherein the first isolation layer comprises polybenzoxazole, polyimide, benzocyclobutene, solder resist, silicon oxynitride, silicon nitride oxide, phosphosilicate glass, borosilicate glass, or boron-doped phosphosilicate glass.

11. The semiconductor device of claim 10, wherein the second conductive portion of the redistribution structure comprises: a conductor layer disposed in the first isolation layer and electrically coupled to the semiconductor via; and a barrier layer disposed between the first isolation layer and the conductor layer, between the circuit layer and the conductor layer, and between the semiconductor via and the conductor layer.

12. The semiconductor device of claim 11, wherein the second conductive portion of the redistribution structure comprises a seed layer disposed between the conductor layer and the barrier layer.

13. The semiconductor device of claim 3, further comprising a thermal dissipation layer disposed under the substrate, wherein the thermal dissipation layer comprises vertically oriented graphite and a plurality of carbon nanotubes.

14. The semiconductor device of claim 13, further comprising an attachment layer disposed between the thermal dissipation layer and the substrate, wherein the attachment layer comprises a grain attachment film, silver paste, or the like.

15. The semiconductor device of claim 3, further comprising a plurality of first connectors disposed on the redistribution structure and respectively electrically coupled to the first conductive portion of the redistribution structure and the second conductive portion of the redistribution structure, wherein the plurality of first connectors comprises a plurality of solder joints, a plurality of bumps, a plurality of stud bumps, or the like.

16. The semiconductor device of claim 15, further comprising a plurality of under-bump metal layers respectively disposed between the plurality of first connectors and the redistribution structure.

17. The semiconductor device of claim 4, wherein the semiconductor via comprises two auxiliary layers respectively disposed between the two isolation layers and the fill layer, wherein each nadir of the two auxiliary layers is disposed at a vertical level that is lower than a vertical level of a lower surface of the first passivation layer.

18. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a circuit layer on the substrate and comprising: a functional block on the substrate; and a test pad on the substrate and distal from the functional block; forming a semiconductor via to physically and electrically connect to the test pad; and forming a redistribution structure on the circuit layer and comprising: a first conductive portion on the functional block and electrically coupled to the functional block; and a second conductive portion on the test pad and electrically coupled to the test pad via the semiconductor via; and forming a plurality of first connectors on the redistribution structure and respectively electrically coupled to the first conductive portion of the redistribution structure and the second conductive portion of the redistribution structure, wherein the plurality of first connectors comprises a plurality of solder joints, a plurality of bumps, a plurality of stud bumps, or the like. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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