An automatic locking DLL applied to a high-speed LVDS interface

Abstract

The present invention relates to an automatic locking DLL applied to a high-speed LVDS interface, which includes a DLL delay-locked loop, a level conversion circuit, a phase detector, an adaptive sliding rheostat, and a DLL locking state identification circuit. The delay structure in the DLL delay-locked loop includes MOS transistor Ⅰ and MOS transistor Ⅱ, and MOS transistor Ⅰ and MOS transistor Ⅱ are connected to each other to form a structure with a positive feedback relationship. Among them, several DLL delay-locked loops are integrated inside the automatic locking DLL; the input end of the phase detector is correspondingly connected to the input signal end of the DLL delay-locked loop branch, and the phase detector is composed of two latch circuits, an OR gate, and a phase detection capacitor. After the two latch circuits and the OR gate form a parallel branch, they are then connected to the phase detection capacitor. The automatic locking DLL based on the high-speed LVDS interface in the present invention adds a phase detection circuit and an automatic locking feedback mechanism inside, improving the following ability and reaction speed of the internal data clock.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to an automatic locking type DLL applied to a high-speed LVDS interface. Background Art

[0002] Generally, the rate of a general LVDS interface is only about 200 Mbps. However, with the development of technology, the requirement for data transmission rate is getting higher and higher, and there is a waste of chip pin resources for the management of the LVDS interface and message transmission. At the same time, the management function of the LVDS interface cannot be flexibly expanded. Finally, in order to obtain a higher-speed LVDS interface and support a higher-rate data clock, there is an urgent need for a circuit structure that can improve the following ability and response speed of the internal data clock and ensure the fast matching of the clock and data. Summary of the Invention

[0003] To solve the above technical problems, an automatic locking type DLL applied to a high-speed LVDS interface of the present invention includes a DLL delay-locked loop, a level conversion circuit, a phase detector, an adaptive sliding rheostat, and a DLL locking state recognition circuit. The delay structure in the DLL delay-locked loop includes a MOS Ⅰ transistor and a MOS Ⅱ transistor, and the MOS Ⅰ transistor and the MOS Ⅱ transistor are connected to each other to form a positive feedback relationship structure. Among them, several DLL delay-locked loops are integrated inside the automatic locking type DLL; the level conversion circuit is arranged at the output end of the DLL delay-locked loop branch, and the phase detector is communicatively connected to the input signal end of the DLL delay-locked loop branch. The phase detector is composed of two latch circuits, an OR gate, and a phase detection capacitor. The output ends of the two latch circuits are respectively connected to the two input ends of the OR gate, and at the same time, the output end of the OR gate is connected to the phase detection capacitor;

[0004] The adaptive sliding rheostat has three ports, which are divided into a first port a, a second port b, and a third port c. The adaptive sliding rheostat is composed of n equal-value series resistors and an adaptive digital adjustment module. The series resistor string divides the power supply voltage into n equal parts. The first port a is directly connected to the bias circuit of the DLL in the DLL delay-locked loop, the second port b is connected to the output end of the DLL locking state recognition circuit, and the third port c is connected to the reverse input end of the DLL locking state recognition circuit; the DLL locking state recognition circuit is composed of a comparator.

[0005] In an embodiment of the present invention, after the MOS Ⅰ transistor and the MOS Ⅱ transistor in the DLL delay-locked loop form a positive feedback relationship with each other, its output voltage will follow the input voltage, but there is a certain delay relationship. The number of delay structures of the DLL delay-locked loop can be increased or decreased by a digital switch.

[0006] In one embodiment of the present invention, the two latch outputs in the phase detector output periodic pulses that reflect a fixed phase difference between its original clock and the clock delayed by the delay-locked loop. After passing through an OR gate, the periodic pulses are output to charge the phase-detection capacitor. After the capacitor is charged, the voltage becomes constant and is then provided as a reference for the adaptive sliding rheostat and the comparator. Then, it discharges and recharges to update the state.

[0007] In one embodiment of the present invention, the adaptive adjustment module continuously monitors the locking state of the DLL through the second port b. The first port a and the third port c are connected to the taps on the serial resistor controlled by the adaptive adjustment module. The voltage output from the first port a directly affects the bias circuit of the DLL, thereby controlling the delay of the DLL unit. The voltage output from the third port c represents the final tracking accuracy of the DLL. In the unlocked case, the adaptive adjustment module will continuously change the tap a on the sliding rheostat according to the digital algorithm, thereby changing the DLL delay through the DLL bias circuit and continuously reducing the voltage on the phase-detection capacitor until the DLL locking condition is met.

[0008] In one embodiment of the present invention, the input of the DLL locking state identification circuit is the comparison voltage output by the adaptive sliding rheostat and the voltage output by the phase-detection capacitor. When the voltage output by the phase-detection capacitor is less than the comparison voltage output by the adaptive sliding rheostat, it is determined that the DLL is locked.

[0009] In one embodiment of the present invention, the phase-detection capacitor is charged and discharged at regular intervals. The holding time after charging is required to meet the time required by the algorithm of the adaptive digital adjustment module, and then it discharges. No digital logic judgment is performed during the discharge period.

[0010] The above technical solution of the present invention has the following advantages compared with the prior art: The automatic locking type DLL based on the high-speed LVDS interface of the present invention adds an automatic locking type DLL delay-locked loop, which has a phase-detection circuit and a locking feedback mechanism inside, can improve the following ability and response speed of the internal data clock, and ensure the rapid matching of the clock and data. This technology has been applied to the LVDS data interface part of the high-speed DAC and has been verified by post-silicon testing. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to make the content of the present invention easier to be clearly understood, the present invention will be further described in detail below according to the specific embodiments of the present invention in conjunction with the drawings.

[0012] Figure 1 is a schematic diagram of the internal structure of an automatic locking type DLL applied to a high-speed LVDS interface of the present invention;

[0013] Figure 2It is a schematic diagram of the internal structure of the adaptive sliding rheostat proposed by the present invention;

[0014] Figure 3 It is a schematic diagram of the internal structure of the minimum unit of the DLL delay-locked loop proposed by the present invention;

[0015] Figure 4 It is a schematic diagram of the phase discrimination mechanism proposed by the present invention. Detailed implementation manners

[0016] As Figure 1 shown, this embodiment provides an automatic locking type DLL applied to a high-speed LVDS interface, including a DLL delay-locked loop, a level conversion circuit, a phase discriminator, an adaptive sliding rheostat, and a DLL locking state identification circuit. The delay structure in the DLL delay-locked loop includes MOS transistor 1 and MOS transistor 2, and MOS transistor 1 and MOS transistor 2 are connected to each other to form a positive feedback relationship structure. Among them, several DLL delay-locked loops are integrated inside the automatic locking type DLL; the level conversion circuit is arranged at the output end of the DLL delay-locked loop branch, and the input terminal interface of the phase discriminator is correspondingly connected to the input signal terminal of the DLL delay-locked loop branch. The phase discriminator is composed of two latch circuits, an OR gate, and a phase discrimination capacitor. The output terminals of the two latch circuits are respectively connected to the two input terminals of the OR gate, and at the same time, the output terminal of the OR gate is connected to the phase discrimination capacitor;

[0017] The adaptive sliding rheostat has three ports, which are divided into a first port a, a second port b, and a third port c. Among them, the first port a is directly connected to the bias circuit of the DLL in the DLL delay-locked loop, the second port b is connected to the output end of the DLL locking state identification circuit, and the third port c is connected to the reverse input end of the DLL locking state identification circuit; the DLL locking state identification circuit is composed of a comparator.

[0018] Furthermore, the provided automatic locking type DLL can automatically identify the locking state and adaptively adjust the DLL circuit delay, so as to quickly follow the input clock and achieve the purpose of data and clock synchronization and matching.

[0019] The delay structure of the DLL delay-locked loop is composed of Figure 3 a structure. MOS transistor 1 and MOS transistor 2 form a positive feedback relationship with each other. The output voltage will follow the input voltage, but there is a certain delay relationship. The number of delay structures of the DLL delay-locked loop can be increased or decreased through a digital switch;

[0020] The phase detector is composed of two latches, an OR gate, and a phase detection capacitor. There is a fixed phase difference between the original clock and the clock delayed by the delay-locked loop (DLL). This phase difference will output a periodic pulse reflecting the magnitude of the phase difference through the latch. After passing through the OR gate, the periodic pulse is used to charge the phase detection capacitor. After the capacitor is charged, the voltage remains constant and is then provided as a reference for the adaptive sliding rheostat and the comparator. Then it discharges and recharges to update the state, as Figure 4 shown;

[0021] The adaptive sliding rheostat is composed of n equal-valued series resistors and an adaptive digital adjustment module, as Figure 2 shown. The series resistor string divides the power supply voltage into n equal parts and has three ports. The adaptive adjustment module continuously monitors the locking state of the DLL through the second port b. The first port a and the third port c are connected to the taps on the series resistors controlled by the adaptive adjustment module. The voltage output from the first port a directly affects the bias circuit of the DLL, thereby controlling the delay of the DLL unit. The voltage output from the third port c represents the final tracking accuracy of the DLL. When not locked, the adaptive adjustment module will continuously change the tap on the sliding rheostat according to the digital algorithm, thereby changing the DLL delay through the DLL bias circuit and continuously reducing the voltage on the phase detection capacitor until the DLL locking condition is met;

[0022] The DLL locking state identification circuit is composed of a comparator. The inputs are the comparison voltage output by the adaptive sliding rheostat and the voltage output by the phase detection capacitor. When the voltage output by the phase detection capacitor is less than the comparison voltage output by the adaptive sliding rheostat, it is determined that the DLL is locked.

[0023] The phase detection capacitor is charged and discharged at regular intervals. The holding time after charging completion needs to meet the time required by the algorithm of the adaptive digital adjustment module, and then it discharges. No digital logic judgment is performed during the discharge period.

[0024] Obviously, the above embodiments are only examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. An automatic locking DLL applied to a high-speed LVDS interface, characterized in that, It includes a DLL delay phase-locked loop, a level conversion circuit, a phase detector, an adaptive sliding rheostat, and a DLL locking state identification circuit. The delay structure in the DLL delay phase-locked loop includes MOS transistor Ⅰ (1) and MOS transistor Ⅱ (2), and MOS transistor Ⅰ (1) and MOS transistor Ⅱ (2) are connected to form a structure with a positive feedback relationship with each other. Among them, several DLL delay phase-locked loops are integrated inside the automatic locking type DLL; the level conversion circuit is arranged at the output end of the DLL delay phase-locked loop branch. The input interface of the phase detector is correspondingly connected to the input signal end of the DLL delay phase-locked loop branch. The phase detector is composed of two latch circuits, an OR gate, and a phase detection capacitor. The output ends of the two latch circuits are respectively connected to the two input ends of the OR gate. At the same time, the output end of the OR gate is connected to the phase detection capacitor. The adaptive sliding rheostat has three ports, which are divided into the first port (a), the second port (b), and the third port (c). The adaptive sliding rheostat is composed of n equal-value series resistors and an adaptive digital adjustment module. The series resistor string divides the power supply voltage into n equal parts. Among them, the first port (a) is directly connected to the bias circuit of the DLL in the DLL delay phase-locked loop. The second port (b) is connected to the output end of the DLL locking state identification circuit, while the third port (c) is connected to the reverse input end of the DLL locking state identification circuit; the DLL locking state identification circuit is composed of a comparator.

2. The automatic locking type DLL according to claim 1, wherein: After MOS transistor Ⅰ (1) and MOS transistor Ⅱ (2) in the DLL delay phase-locked loop form a positive feedback relationship with each other, its output voltage will follow the input voltage, but there is a certain delay relationship. The number of delay structures of the DLL delay phase-locked loop can be increased or decreased through a digital switch.

3. The automatic locking type DLL according to claim 1, wherein: The two latch circuit outputs in the phase detector reflect the periodic pulses of a fixed phase difference between its original clock and the clock delayed by the delay phase-locked loop. After passing through the OR gate, the periodic pulses are output to charge the phase detection capacitor. After the capacitor is charged, the voltage is constant, and then it is provided as a reference for the adaptive sliding rheostat and the comparator. Then it discharges and recharges to update the state.

4. The automatic locking type DLL according to claim 1, wherein: The adaptive adjustment module always monitors the locking state of the DLL through the second port (b). The first port (a) and the third port (c) are connected to the taps on the serial resistor controlled by the adaptive adjustment module. The output voltage of the first port (a) directly affects the bias circuit of the DLL, thereby controlling the delay size of the DLL unit. The output voltage of the third port (c) represents the final following accuracy of the DLL.

5. The automatic locking type DLL according to claim 1, wherein: In the DLL locking state identification circuit, the input is the comparison voltage output by the adaptive sliding rheostat and the voltage output by the phase detection capacitor. When the voltage output by the phase detection capacitor is less than the comparison voltage output by the adaptive sliding rheostat, it is judged that the DLL is locked.

6. The automatic locking type DLL according to claim 3, wherein: The phase detection capacitor will be charged and discharged every once in a while. The holding time after charging is required to meet the time required by the algorithm of the adaptive digital adjustment module, and then it discharges. No digital logic judgment is performed during the discharge period.

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