A pixel unit circuit, image sensor and timing control method thereof

Abstract

The present invention discloses a pixel unit circuit, which includes: a photoelectric signal conversion unit for converting exposure information of a pixel point in an image frame into an initial voltage signal; a voltage amplification unit for amplifying and outputting the initial voltage signal; a first output unit for receiving and storing a first voltage signal of a pixel point in the image frame at the n-1th frame; a second output unit for receiving and outputting a second voltage signal of a pixel point in the image frame at the n-th frame; a comparison unit for receiving the first voltage signal from the first output unit and the second voltage signal from the second output unit, and comparing the first voltage signal and the second voltage signal to determine whether there is a change between the initial voltage signal of the pixel point in the image frame at the n-1th frame and the initial voltage signal of the pixel point in the image frame at the n-th frame. The pixel unit circuit provided by the present invention is used to save power consumption while ensuring CIS performance.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor image sensing technology, and in particular to a pixel unit circuit, an image sensor and a timing control method thereof. Background Art

[0002] Currently, complementary metal oxide semiconductor image sensors (CIS), as typical solid-state imaging sensors, are a key component of digital cameras and are widely used in industrial cameras, consumer electronics, digital products, security monitoring and other fields. With the continuous upgrading of smartphones and the drive of new technologies such as the Internet of Things, artificial intelligence, and advanced driver assistance systems, CIS has ushered in a rise in market demand, but also faces new challenges. On the one hand, CIS is becoming more and more integrated, and more new applications and technologies are being deployed compared to traditional shooting needs; on the other hand, mobile portable devices are generally powered by batteries and have strict application requirements for low power consumption and low heat dissipation. How to control and optimize the power consumption of CIS without reducing its performance has become a technical problem currently faced. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel unit circuit, an image sensor, and a timing control method thereof, which are used to trigger analog-to-digital conversion when a voltage signal of a pixel circuit changes significantly, thereby saving power consumption while ensuring CIS performance.

[0004] In a first aspect, the present invention provides a pixel unit circuit, the pixel unit circuit comprising:

[0005] A photoelectric signal conversion unit is used to convert exposure information of a pixel point in an image frame into an initial voltage signal; a voltage amplification unit is used to amplify and output the initial voltage signal; a first output unit is connected to the voltage amplification unit, and is used to receive and store a first voltage signal of a pixel point in the image frame at the n-1th frame; a second output unit is connected to the voltage amplification unit, and is used to receive and output a second voltage signal of the pixel point in the image frame at the nth frame; a comparison unit is connected to the output end of the first output unit and the output end of the second output unit, respectively, and the comparison unit is used to receive the first voltage signal from the first output unit and the second voltage signal from the second output unit, and compare the first voltage signal and the second voltage signal to determine whether there is a change between the initial voltage signal of the pixel point in the image frame at the n-1th frame and the initial voltage signal of the pixel point in the image frame at the nth frame.

[0006] The pixel unit circuit provided by the present invention has the following beneficial effects: the pixel unit circuit includes two output units, wherein the second output unit stores the pixel signal of the nth frame, and the first output unit stores the pixel signal of the n-1th frame, and the voltage signals of the two output units are simultaneously output to a comparison unit. This pixel structure is suitable for row-parallel processing of sampling information, including subsequent voltage signal comparison and analog-to-digital conversion. Because pixels in the same row operate in parallel, the operation speed can be greatly improved, and the system operation bandwidth can be increased. In addition, the comparison unit can determine whether the initial voltage signal of the pixel point has changed, which helps to determine whether to trigger analog-to-digital conversion.

[0007] Optionally, the photoelectric signal conversion unit includes a photodiode; the voltage amplification unit includes a first MOS tube, a second MOS tube and a third MOS tube; the source or drain of the first MOS tube and the gate of the second MOS tube are both connected to the cathode of the photodiode, the source or drain of the second MOS tube is connected to the source or drain of the third MOS tube, and the drain or source of the second MOS tube and the drain or source of the first MOS tube are both connected to the power supply voltage.

[0008] Optionally, the comparison unit includes a comparator; the first output unit includes a first switching transistor, a capacitor, a second switching transistor, and a fourth MOS transistor and a fifth MOS transistor;

[0009] The capacitor is used to store charge, one end of the capacitor is connected to the first switching transistor and the second switching transistor, and the other end of the capacitor is grounded; the gate of the fifth MOS transistor is connected to the second switching transistor, the source or drain of the fifth MOS transistor is connected to the source or drain of the fourth MOS transistor, and the drain or source of the fifth MOS transistor is connected to the first input terminal of the comparator; the drain or source of the fourth MOS transistor is grounded;

[0010] The first switching transistor and the second switching transistor are used to control the charging and discharging state of the capacitor; when the first switching transistor is closed and the second switching transistor is disconnected, the initial voltage signal of the pixel point of the image frame is stored in the capacitor; when the first switching transistor is disconnected and the second switching transistor is closed, the charge in the capacitor is transferred to the fifth MOS transistor through the second switching transistor.

[0011] Optionally, the second output unit includes a sixth MOS transistor and a seventh MOS transistor; the gate of the seventh MOS transistor is connected to the source or drain of the second MOS transistor, the source or drain of the seventh MOS transistor is connected to the source or drain of the sixth MOS transistor, the drain or source of the seventh MOS transistor is connected to the second input terminal of the comparator, and the drain or source of the sixth MOS transistor is grounded.

[0012] In a second aspect, the present invention further provides an image sensor, comprising, in addition to a pixel array and an analog-to-digital conversion unit formed by any possible pixel unit circuit according to the first aspect, the comparison unit is further configured to: when the absolute value of the difference between the first voltage signal and the second voltage signal is not within a set range, determine that there is a change between the initial voltage signal of the pixel point in the image frame at the n-1th frame and the initial voltage signal of the pixel point in the image frame at the nth frame, and send a trigger signal to the analog-to-digital conversion unit; the analog-to-digital conversion unit is connected to the output end of the second output unit, and the analog-to-digital conversion unit is configured to receive the second voltage signal of the pixel point in the image frame at the nth frame; and upon receiving the trigger signal, begin analog-to-digital conversion of the second voltage signal. In this embodiment, the comparison unit triggers the analog-to-digital conversion unit to perform analog-to-digital conversion only when a pixel signal changes significantly, and does not trigger analog-to-digital conversion when the pixel signal does not change significantly, thereby saving power consumption while ensuring CIS performance.

[0013] In a third aspect, the present invention provides a timing control method for a pixel unit circuit, which can be applied to the pixel circuit as described in the first aspect. The timing control method includes:

[0014] For the n-1th frame, in the first time period t1 starting from time T1, the driving circuit controls the reset signal input to the first MOS transistor to be high, turns on the first MOS transistor, and resets the photodiode;

[0015] In the second period t2 starting from time T2, the driving circuit controls the reset signal input to the first MOS transistor to switch from a high level to a low level, the first MOS transistor is disconnected, and the pixel unit circuit begins to be exposed;

[0016] The first switching transistor is controlled to be turned on. In a third period t3 starting at time T3, the driving circuit controls the row control signal to switch to a high potential, and the pixels of the corresponding row are selected. The sampling signals of the pixels in the row are stored on the capacitor. The pixel signal of the (n-1)th frame stored on the capacitor is output to the first input terminal of the comparison unit through the first transmission unit.

[0017] For the nth frame, in the fourth time period t4 starting from time T4, the driving circuit again controls the reset signal input to the first MOS transistor to be high level, turns on the first MOS transistor, and resets the photodiode;

[0018] In a fifth time period t5 starting from time T5, the driving circuit controls the reset signal input to the first MOS transistor to switch from a high level to a low level, the first MOS transistor is turned off, the pixel unit circuit begins to be exposed, and the second voltage signal of the nth frame is output to the second input terminal of the comparison unit through the second transmission unit;

[0019] When the difference between the second voltage signal and the first voltage signal is not within the set range, the comparison unit triggers the analog-to-digital conversion unit to perform analog-to-digital conversion at time T2; when the difference between the second voltage signal and the first voltage signal is within the set range, the comparison unit does not trigger the analog-to-digital conversion unit to perform analog-to-digital conversion.

[0020] Optionally, the method further comprises: after analog-to-digital conversion for a set period of time, writing the conversion result into the output result latch of the corresponding column.

[0021] Optionally, the method further includes: after the analog-to-digital conversion of the row of pixels is completed, clearing the conversion result and the comparison result stored in the latch.

[0022] Optionally, the method further includes: reading out the conversion results and comparison results stored in the latch in a serial manner.

[0023] The timing control method for a pixel unit circuit provided by the present invention has the beneficial effect of: when a row of pixels is selected, all pixels in the row input the voltage signal sampled in the current image frame and the voltage signal stored on the capacitor in the previous frame into a comparison unit for analog signal comparison. Only when a pixel signal is determined to have changed significantly does the analog-to-digital conversion unit trigger analog-to-digital conversion. If the pixel signal does not change significantly, analog-to-digital conversion is not triggered, thereby saving power consumption while ensuring CIS performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figure 1 A schematic diagram of a pixel unit circuit structure provided by an embodiment of the present invention

[0026] Figure 2 A schematic diagram of another specific pixel unit circuit structure provided by an embodiment of the present invention;

[0027] Figure 3 A schematic flow chart of a timing control method for a pixel unit circuit provided by an embodiment of the present invention;

[0028] Figure 4 A schematic structural diagram of an image sensor provided by an embodiment of the present invention;

[0029] Figure 5 A schematic diagram of timing waveforms of circuit operation of a unit pixel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0030] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also included in the scope of protection of the present invention.

[0031] It should be noted that in the following specific embodiments, when describing the embodiments of the present invention in detail, in order to clearly represent the structure of the present invention for the convenience of explanation, the structures in the accompanying drawings are not drawn according to general proportions, and are partially enlarged, deformed and simplified. Therefore, it should be avoided to understand this as a limitation of the present invention.

[0032] An embodiment of the present invention provides an image sensor, comprising a pixel array composed of pixel unit circuits. Figure 1 As shown, the pixel unit circuit includes a photoelectric signal conversion unit 01, a voltage amplification unit 02, a first output unit 03, a second output unit 04 and a comparison unit 05.

[0033] The photoelectric signal conversion unit 01 is used to convert the exposure information of the pixel points in the image frame into an initial voltage signal.

[0034] The voltage amplifying unit 02 is used to amplify and output the initial voltage signal.

[0035] The first output unit 03 and the second output unit 04 are both connected to the voltage amplification unit 02. The first output unit 03 is used to receive and store the first voltage signal of the pixel point of the image frame at the n-1 frame; the second output unit 04 is used to receive and output the second voltage signal of the pixel point of the image frame at the n frame.

[0036] A comparison unit 05, wherein the comparison unit 05 is connected to the output end of the first output unit 03 and the output end of the second output unit 04, respectively, and is used to receive the first voltage signal from the first output unit 03 and the second voltage signal from the second output unit 04, and compare the first voltage signal with the second voltage signal to determine whether there is a change between the initial voltage signal of the pixel point in the image frame at the n-1th frame and the initial voltage signal of the pixel point in the image frame at the nth frame.

[0037] Optionally, the image sensor including the above-mentioned pixel unit circuit further includes an analog-to-digital conversion unit 06, which is connected to the output end of the second output unit 04. The comparison unit 05 is further configured to: when the absolute value of the difference between the first voltage signal and the second voltage signal is not within a set range, determine that there is a change between the initial voltage signal of the pixel point in the image frame at the (n-1)th frame and the initial voltage signal of the pixel point in the image frame at the (n)th frame, and output a trigger signal for activating the analog-to-digital conversion unit 06 to perform analog-to-digital conversion.

[0038] As can be seen, the above-mentioned pixel unit circuit includes two output units, wherein the second output unit 04 stores and outputs the pixel signal of the nth frame, and the first output unit 03 stores the pixel signal of the n-1th frame. The voltage signals of the two output units are simultaneously output to the comparison unit 05. This pixel structure is suitable for row-parallel processing of sampling information, including the subsequent voltage signal comparison and analog-to-digital conversion process. Since pixels in the same row operate in parallel, the operation speed can be greatly improved, and the system operation bandwidth can be increased. In addition, the comparison unit 05 can determine whether the initial voltage signal of the pixel point has changed, which helps to determine whether to trigger analog-to-digital conversion. Only when a pixel signal changes significantly does the comparison unit 05 trigger the analog-to-digital conversion unit 06 to perform analog-to-digital conversion. When the pixel signal does not change significantly, the analog-to-digital conversion unit 06 is not triggered for analog-to-digital conversion, thereby saving power consumption while ensuring CIS performance.

[0039] In a specific embodiment, Figure 2 As shown, the above-mentioned photoelectric signal conversion unit 01 includes a photodiode (PD); the voltage amplification unit 02 includes a first MOS transistor M1, a second MOS transistor M2 and a third MOS transistor M3.

[0040] Specifically, the cathode of the photodiode PD is connected to the source or drain of the first MOS transistor M1, and the anode of the photodiode PD is grounded to VSS. The photodiode is configured to generate an electrical signal in response to a light signal. The gate of the first MOS transistor M1 is connected to a drive circuit, which inputs a reset signal (reset) to the first MOS transistor M1. The drain or source of the first MOS transistor M1 is connected to the power supply voltage VDD to reset the photodiode PD.

[0041] The gate of the second MOS transistor M2 is also connected to the cathode of the photodiode. The source or drain of the second MOS transistor M2 is connected to the power supply voltage VDD, and the drain or source is connected to one end of the third MOS transistor M3. The first and second MOS transistors M2 are used to amplify the initial voltage signal of the pixel point of the image frame to the first node A. The second MOS transistor M2 can be a source follower (SF) amplifier transistor, and the third MOS transistor M3 can be a site selection switch.

[0042] The first output unit 03 is used to output the first voltage signal of the first node A in the n-1th frame. Figure 2 For example, the first output unit O3 includes a first switching transistor S1, a capacitor C, a second switching transistor S2, and a fourth MOS transistor M4 and a fifth MOS transistor M5. One end of the capacitor C is connected to the first switching transistor S1 and the second switching transistor S2, and the other end is grounded to VSS. The capacitor C is used to store charge, and the first switching transistor S1 and the second switching transistor S2 are used to control the charge and discharge state of the capacitor. When the first switching transistor S1 is closed and the second switching transistor S2 is opened, the charge at the first node is stored in the capacitor C; when the first switching transistor S1 is opened and the second switching transistor S2 is closed, the charge in the capacitor C is transferred to the fifth MOS transistor M5 through the second switching transistor S2. Figure 2 As can be seen in FIG, the gate of the fifth MOS transistor M5 is connected to the second switch transistor, one end of the fifth MOS transistor M5 is connected to one end of the fourth MOS transistor M4, and the other end of the fifth MOS transistor M5 is connected to the first input end Input1 of the comparator comp. The other end of the fourth MOS transistor M4 is grounded to VSS.

[0043] The second output unit 04 is used to output the second voltage signal of the first node in the nth frame, where n is a positive integer. Figure 2 As shown, the second output unit includes a sixth MOS transistor M6 and a seventh MOS transistor M7. The gate of the seventh MOS transistor M7 is connected to the first node A, one end of the seventh MOS transistor M7 is connected to one end of the sixth MOS transistor M6, and the other end of the seventh MOS transistor M7 is connected to the second input terminal Input2 of the comparator comp. The other end of the sixth MOS transistor M6 is grounded to VSS.

[0044] In some optional embodiments, the pixel unit circuit is further connected to a driving circuit, and the driving circuit is connected to the gate of the first MOS transistor M1, the gate of the third MOS transistor M3, the gate of the fourth MOS transistor M4, the first switching transistor S1, the second switching transistor S2, and the gate of the sixth MOS transistor M6. The driving circuit is used to drive the first MOS transistor M1, the third MOS transistor M3, the fourth MOS transistor M4, the first switching transistor S1, the second switching transistor S2, and the sixth MOS transistor M6.

[0045] like Figure 2 As shown, the comparison unit includes a comparator comp, which is shared by the same column of pixel unit circuits and is used to output a trigger signal when the absolute value of the difference between the first voltage signal and the second voltage signal is not within a set range. The trigger signal is used to activate the analog-to-digital conversion unit to perform analog-to-digital conversion.

[0046] It is worth noting that each transistor mentioned above can be an NMOS transistor or a PMOS transistor. In this application, one end of any transistor is a source and the other end is a drain, or one end of any transistor is a drain and the other end is a source.

[0047] In this embodiment, optionally, the source or drain of the third MOS transistor M3 is connected to the source or drain of the eighth MOS transistor M8, the drain or source of the eighth MOS transistor M8 is grounded, the eighth MOS transistor M8 is shared by the pixel unit circuits in the same column, and the eighth MOS transistor M8 is used to provide a bias voltage.

[0048] Optionally, the source or drain of the fifth MOS transistor M5 is connected to the source or drain of a ninth MOS transistor M9, the drain or source of the ninth MOS transistor M9 is grounded, the ninth MOS transistor M9 is shared by pixel unit circuits in the same column, and the ninth MOS transistor M9 is used to provide a bias voltage;

[0049] The drain or source of the seventh MOS transistor M7 is connected to the source or drain of the tenth MOS transistor M10. The drain or source of the tenth MOS transistor M10 is grounded. The tenth MOS transistor M10 is shared by the pixel unit circuits in the same column and is used to provide a bias voltage. The eighth MOS transistor M8 receives a bias voltage. The gates of the ninth and tenth MOS transistors M9 and M10 receive a bias voltage. The drain or source of the ninth and tenth MOS transistors M9 and M10 are connected to the power supply voltage VDD.

[0050] It is worth noting that the fourth MOS transistor M4 and the comparator comp can be shared by the pixel units in the same column, and the ninth MOS transistor M9 and the tenth MOS transistor M10 can be shared by the pixel units in the same column.

[0051] In this embodiment, the pixel unit circuit includes two output units. The second output unit stores the pixel signal of the nth frame, while the first output unit stores the pixel signal of the n-1th frame. The voltage signals of the two output units are output simultaneously. This pixel structure is suitable for row-parallel processing of sampled information, including the subsequent voltage signal comparison and analog-to-digital conversion process. Because pixels in the same row operate in parallel, the operation speed can be greatly improved, increasing the system operation bandwidth. In addition, the analog-to-digital conversion is triggered only when a pixel signal changes significantly, which helps to save power.

[0052] Based on the above pixel unit circuit, the following is further combined Figure 3 Timing control method in Figure 4 The image sensor structure diagram in , and Figure 5 The timing flow chart in shows a schematic flow chart of a timing control method for a pixel unit circuit, which specifically includes the following steps.

[0053] S301 , for the n-1th frame, in the first period t1 starting from time T1 , the driving circuit controls the reset signal rst input to the first MOS transistor M1 of the pixel unit circuit 401 to be high, turns on the first MOS transistor M1 , and resets the photodiode PD.

[0054] S302 , in the second period t2 starting from time T2 , the driving circuit controls the reset signal rst input to the first MOS transistor M1 to switch from a high level to a low level, the first MOS transistor M1 is disconnected, and the pixel unit circuit starts to be exposed.

[0055] S303, controlling the first switch transistor S1 to be turned on, in the third period t3 starting at time T3, the driving circuit controls the row control signal row to switch to a high potential, the pixels of the corresponding row are selected, and the sampling signals of each pixel in the row are stored on the capacitor C.

[0056] In this step, when the image sensor's row address selection logic and signal driver component 403 controls the reset signal rst to switch from a high level to a low level, the pixel unit circuit 401 begins integrating and sampling exposure information. Subsequently, the driver circuit controls the first switch transistor S1 to turn on. When the row control signal row switches to a high potential at time T3, the pixels in the corresponding row are selected, and the sampled signals of all pixels in the row are stored on the capacitor C. In addition, the image sensor's column address encoder 402 is used to implement column address encoding, generating the X column address [M-1:0]. The row address encoder 404 is used to implement row address encoding, generating the Y column address [N-1:0], where M and N are positive integers.

[0057] S304 , in the nth frame, in the fourth time period t4 starting from time T4 , the driving circuit again controls the reset signal rst input to the first MOS transistor M1 to be high level, turns on the first MOS transistor M1 , and resets the photodiode PD.

[0058] S305, in the fifth time period t5 starting from time T5, the driving circuit controls the reset signal rst input to the first MOS transistor M1 to switch from a high level to a low level, the first MOS transistor M1 is disconnected, and the pixel unit circuit begins to be exposed. The second voltage signal of the nth frame is output to the second input terminal Input2 of the comparator comp through the second transmission unit, and the first voltage signal of the (n-1)th frame stored in the capacitor C is output to the first input terminal Input1 of the comparator comp through the first transmission unit.

[0059] In this step, after the pixel unit circuit is exposed, the photovoltaic effect under light will accumulate electrons on the surface of the photodiode PD due to the use of special semiconductor PN junction technology. The photovoltaic special effect refers to: after the PN junction intrinsic layer absorbs photons, photogenerated electrons and photogenerated holes will be generated. The two will be separated in the built-in electric field of the PN junction, thereby forming the phenomenon of photovoltaic voltage and photogenerated current.

[0060] In this embodiment, after a period of photoelectric conversion and integration in the pixel unit circuit, the voltage at the sampling point becomes proportional to the light intensity, reaching a specific value. During the sixth period t6, which begins at time T6, the first transmission unit outputs the (n-1)th frame signal stored in the first transmission unit to the first input terminal input1. When the row control signal switches to a high level, the pixels in the corresponding row are selected. At this time, the control signal input to the first switching transistor S1 is at a low level, and the first switching transistor S1 remains off. Therefore, the charge does not pass through the first transmission unit, but is instead directly output to the second input terminal Input2 of the comparator comp via the second transmission unit. Simultaneously, the second voltage signal of the nth frame is also output to the input port of the analog-to-digital conversion unit.

[0061] S306 , when the difference between the second voltage signal and the first voltage signal is not within the set range, the comparator comp triggers the analog-to-digital conversion unit to perform analog-to-digital conversion at time T7 .

[0062] Specifically, the comparator comp determines the difference between the second voltage signal and the first voltage signal collected by the same pixel in the two frames, and determines whether the absolute value of the difference is within the set range. If it exceeds the set range, it means that there is a significant change in the pixel signal. Therefore, the trigger signal (change) output by the comparator switches from a low level to a high level, activating the analog-to-digital conversion unit (ADC) to start the analog-to-digital conversion process, wherein the gradient waveform generator 409 is connected to the ADC. After a certain period of analog-to-digital conversion process, the conversion result is written into the output result latch FIFO of the corresponding column. Combined with Figure 4 For example, Figure 4 Event generator 405 corresponds to Figure 2 The comparator comp in the comparator comp, the comparator comp output is Figure 2 The trigger signal (change).

[0063] In this embodiment, when a row of pixels is selected, all pixels in the row input the voltage signal sampled in the current frame and the voltage signal stored on capacitor C in the previous frame into a comparator for analog signal comparison. When a pixel signal is determined to have changed significantly (the criterion is that the absolute value of the difference between the two exceeds a set range), the comparator result of the corresponding column of the pixel will output 1, the analog-to-digital conversion unit is enabled, and the pixel signal is converted into a digital signal by the column-shared column analog-to-digital conversion component 406 (A / D) and stored in the corresponding column analog-to-digital conversion structure latch 407. At the same time, the event status of the column is set to 1 (comparison result latch FIFO) and stored in the corresponding column event comparison result latch 408. If the pixel signal is determined to have not changed significantly (the criterion is that the absolute value of the difference between the two is within a set range), the comparator of the corresponding column of the pixel will output 0, the analog-to-digital conversion unit will not be activated, the pixel signal will not be A / D converted, and the status of the column will be set to 0.

[0064] Optionally, in S307 , after the analog-to-digital conversion of the row of pixels is completed, at time T8 , the conversion result and the comparison result stored in the latch are cleared.

[0065] That is, the system finally reads out and clears all conversion results stored in the column analog-to-digital conversion result latch 407 in a rapid serial manner. Correspondingly, all comparison results stored in the event result latch 408 are also read out and cleared in a synchronous and rapid serial manner.

[0066] It is worth noting that when the value stored in each cell of the latch FIFO is a first value (e.g., 0), the ADC value of the corresponding column is an invalid value. Only when the value stored in each cell of the latch FIFO is a second value (e.g., 1), the ADC value of the corresponding column is valid.

[0067] In this embodiment, the output of the image sensor can be output in either a synchronous or asynchronous manner. The so-called synchronous mode means that the output includes the numerical value of each pixel and the numerical value of the corresponding comparator result, that is, the correspondence between the pixel numerical value and the corresponding comparison result. When the numerical value of the comparator result is 0, the numerical value of the pixel is the previously collected pixel numerical value and has not changed. When the numerical value of the comparator result is 1, the numerical value of the pixel changes, and the numerical value output by the ADC replaces the numerical value of the pixel collected in the previous frame.

[0068] Asynchronous output refers to the output of the pixel's analog-to-digital value, along with the pixel's corresponding row and column address (pixel value, (column X address, row Y address)). Synchronous and asynchronous refers to whether the image sensor, as the information sender, and the computer, as the information receiver, require the synchronization signal FRARME_START (or LINE_START) at the beginning of each frame (or each line).

[0069] In summary, the advantage of the present invention is that when a row of pixels is selected, all pixels in that row input the voltage signal sampled in the current image frame and the voltage signal stored on the capacitor in the previous frame into the comparator for analog signal comparison. Only when a pixel signal is determined to have changed significantly does the analog-to-digital conversion unit trigger analog-to-digital conversion. If the pixel signal has not changed significantly, analog-to-digital conversion is not triggered, thereby saving power consumption while ensuring CIS performance.

[0070] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of patent protection of the present invention. Therefore, any equivalent structural variations made using the description and drawings of the present invention are also intended to be included within the scope of protection of the present invention. The above description of the disclosed embodiments is intended to enable those skilled in the art to implement or use the present invention.

[0071] Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention is not limited to the embodiments shown herein, but is to be construed in the widest manner consistent with the principles and novel features disclosed herein.

Claims

1. A pixel unit circuit, characterized in that: include: A photoelectric signal conversion unit, configured to convert exposure information of pixels in an image frame into an initial voltage signal; a voltage amplifying unit, configured to amplify and output the initial voltage signal; Wherein, the photoelectric signal conversion unit includes a photodiode; the voltage amplification unit includes a first MOS tube, a second MOS tube and a third MOS tube; The source or drain of the first MOS transistor and the gate of the second MOS transistor are both connected to the cathode of the photodiode, the source or drain of the second MOS transistor is connected to the source or drain of the third MOS transistor, and the drain or source of the second MOS transistor and the drain or source of the first MOS transistor are both connected to a power supply voltage; the first output unit is connected to the voltage amplifying unit, and is used to receive and store the first voltage signal of the pixel point in the image frame at the (n-1)th frame; The second output unit is connected to the voltage amplifying unit, and is used to receive and output a second voltage signal of the pixel point in the image frame at the nth frame; a comparing unit, the comparing unit being connected to the output end of the first output unit and the output end of the second output unit, respectively, and being configured to receive the first voltage signal from the first output unit and the second voltage signal from the second output unit, and compare the first voltage signal with the second voltage signal to determine whether there is a change between an initial voltage signal of the pixel point in the image frame at the (n-1)th frame and the initial voltage signal of the pixel point in the image frame at the (n)th frame; When the absolute value of the difference between the first voltage signal and the second voltage signal is not within a set range, determining that there is a change between the initial voltage signal of the pixel point in the image frame at the (n-1)th frame and the initial voltage signal of the pixel point in the image frame at the (n)th frame, and sending a trigger signal to the analog-to-digital conversion unit; In which, the analog-to-digital conversion unit is connected to the output end of the second output unit, and the analog-to-digital conversion unit is used to receive the second voltage signal of the pixel point in the image frame at the nth frame; when the analog-to-digital conversion unit receives the trigger signal, it starts to perform analog-to-digital conversion on the second voltage signal.

2. The pixel unit circuit according to claim 1, wherein: The comparison unit includes a comparator; The first output unit includes a first switching transistor, a capacitor, a second switching transistor, and a fourth MOS transistor and a fifth MOS transistor; The capacitor is used to store charge, one end of the capacitor is connected to the first switching transistor and the second switching transistor, and the other end of the capacitor is grounded; the gate of the fifth MOS transistor is connected to the second switching transistor, the source or drain of the fifth MOS transistor is connected to the source or drain of the fourth MOS transistor, and the drain or source of the fifth MOS transistor is connected to the first input terminal of the comparator; the drain or source of the fourth MOS transistor is grounded; The first switching transistor and the second switching transistor are used to control the charging and discharging state of the capacitor; when the first switching transistor is closed and the second switching transistor is disconnected, the initial voltage signal of the pixel point of the image frame is stored in the capacitor; when the first switching transistor is disconnected and the second switching transistor is closed, the charge in the capacitor is transferred to the fifth MOS transistor through the second switching transistor.

3. The pixel unit circuit according to claim 2, wherein: The second output unit includes a sixth MOS transistor and a seventh MOS transistor; the gate of the seventh MOS transistor is connected to the source or drain of the second MOS transistor, the source or drain of the seventh MOS transistor is connected to the source or drain of the sixth MOS transistor, the drain or source of the seventh MOS transistor is connected to the second input terminal of the comparator, and the drain or source of the sixth MOS transistor is grounded.

4. An image sensor, characterized in that: A pixel array comprising a pixel unit circuit according to any one of claims 1 to 3 and an analog-to-digital conversion unit, The comparing unit is further configured to: when the absolute value of the difference between the first voltage signal and the second voltage signal is not within a set range, determine that there is a change between the initial voltage signal of the pixel point in the image frame at the (n-1)th frame and the initial voltage signal of the pixel point in the image frame at the (n)th frame, and send a trigger signal to the analog-to-digital conversion unit; The analog-to-digital conversion unit is connected to the output end of the second output unit, and is used to receive the second voltage signal of the pixel point in the image frame at the nth frame; when receiving the trigger signal, the analog-to-digital conversion of the second voltage signal begins.

5. A timing control method for a pixel unit circuit, characterized in that: Applied to the pixel unit circuit according to any one of claims 2 to 3, the timing control method comprises: For the n-1th frame, in the first time period t1 starting from time T1, the driving circuit controls the reset signal input to the first MOS transistor to be high, turns on the first MOS transistor, and resets the photodiode; In the second period t2 starting from time T2, the driving circuit controls the reset signal input to the first MOS transistor to switch from a high level to a low level, the first MOS transistor is disconnected, and the pixel unit circuit begins to be exposed; The first switching transistor is controlled to be turned on. In a third period t3 starting at time T3, the driving circuit controls the row control signal to switch to a high potential. The pixels of the corresponding row are selected, and the sampling signals of the pixels of the corresponding row are stored on the capacitor. The pixel signal of the (n-1)th frame stored on the capacitor is output to the first input terminal of the comparison unit through the first transmission unit. For the nth frame, in the fourth time period t4 starting from time T4, the driving circuit again controls the reset signal input to the first MOS transistor to be high level, turns on the first MOS transistor, and resets the photodiode; In a fifth time period t5 starting from time T5, the driving circuit controls the reset signal input to the first MOS transistor to switch from a high level to a low level, the first MOS transistor is turned off, the pixel unit circuit begins to be exposed, and the second voltage signal of the nth frame is output to the second input terminal of the comparison unit through the second transmission unit; When the difference between the second voltage signal and the first voltage signal is not within the set range, the comparison unit triggers the analog-to-digital conversion unit to perform analog-to-digital conversion at time T2; when the difference between the second voltage signal and the first voltage signal is within the set range, the comparison unit does not trigger the analog-to-digital conversion unit to perform analog-to-digital conversion.

6. The timing control method according to claim 5, wherein: The method further comprises: After the analog-to-digital conversion for a set period of time, the conversion result is written into the output result latch of the corresponding column.

7. The timing control method according to claim 6, wherein: The method further comprises: When the analog-to-digital conversion of a row of pixels is completed, the conversion results and comparison results stored in the latch are cleared.

8. The timing control method according to claim 6, wherein: The method further comprises: The conversion results and comparison results stored in the latch are read out serially.

9. The timing control method according to claim 6, wherein: When the value stored in each unit of the latch is a first value, the value after analog-to-digital conversion of the corresponding column is an invalid value; when the value stored in each unit of the latch is a second value, the value after analog-to-digital conversion of the corresponding column is a valid value.

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