Circuit board for semiconductor testing

Abstract

The present invention relates to a circuit board for semiconductor testing, which includes a first sub-circuit board, a second sub-circuit board, and an interposer disposed therebetween. Each sub-circuit board includes a substrate and a plurality of circuits, and the circuits include upper and lower contacts. The interposer includes a plurality of vias and a plurality of connection conductors disposed therein and electrically connecting the upper and lower contacts of the two sub-circuit boards. The circuit board can define a central area and a peripheral area. The lower contacts of the first sub-circuit board located in the central area are electrically connected to a probe head, and the upper contacts of the second sub-circuit board located in the peripheral area are electrically connected to a test machine. The pitch of the upper contacts of the second sub-circuit board in the peripheral area is greater than the pitch of the lower contacts of the first sub-circuit board in the central area, and the number thereof is more than that of the lower contacts of the first sub-circuit board in the peripheral area. Thus, the power supply test consistency of the circuit board of the present invention is good.

Description

Technical Field

[0001] The present invention relates to a circuit board, and more particularly to a circuit board for semiconductor testing. Background Art

[0002] In the field of semiconductor testing, a probe card is used as an interface for connecting a tester and a device under test (e.g., a die on a wafer). The main structure of the probe card includes a circuit board (e.g., a printed circuit board, abbreviated as PCB) and a plurality of probes. Please refer to Figure 1 and Figure 2 , the circuit board 60 can be divided into a central region 63 (also referred to as the BGA region) located in the center of the circuit board 60 and a peripheral region 64 (also referred to as the pogo region) adjacent to the outer periphery of the circuit board 60 from its upper surface 61 or lower surface 62. The upper surface 61 of the circuit board 60 is the tester side, and the contacts (not shown in the figure) located in the peripheral region 64 on the upper surface 61 of the circuit board 60 are electrically connected to the tester (not shown in the figure). The lower surface 62 of the circuit board 60 is the device under test side, and the contacts (not shown in the figure) located in the central region 63 on the lower surface 62 of the circuit board 60 are electrically connected to the probes (not shown in the figure). During testing, the probe card electrically connects to the contacts of the device under test through the probes, so as to receive the signals generated by the tester through the circuit board 60 and then transmit them to the device under test, or receive the test results of the device under test and then transmit them to the tester.

[0003] Viewed from the longitudinal section of the circuit board 60, as shown in Figure 2 , the circuit board 60 can be divided into a power layer 65 (also referred to as the PI layer) and a signal layer 66 (also referred to as the SI layer) according to functions, and the circuit layout is carried out in a vertical layered manner. When establishing a test loop, the tester is electrically connected to the peripheral region 64 of the circuit board 60, and then the power signal is electrically connected from the peripheral region 64 to the central region 63 through the power layer 65 to provide the power required for testing the device under test. At the same time, the contacts for transmitting the test signal in the peripheral region 64 are electrically connected to the central region 63 through the signal layer 66 to transmit and / or receive the electrical signals of the device under test.

[0004] Furthermore, the current power layer 65 is mostly designed by stacking in the GPPG manner. G refers to the ground plane of the power layer 65, and P refers to the power plane of the power layer 65. Since the current circuit board manufacturing process forms circuits layer by layer (for example, in sequence, signal layer 66, ground plane G of the power layer 65, power plane P of the power layer 65, etc.), then performs lamination, and finally performs processes such as drilling and plated through hole (abbreviated as PTH) to electrically connect the circuits of each layer. Therefore, in the case where the circuits of the power layer 65 and the signal layer 66 are formed in a single circuit board in a mixed stacked arrangement, when performing the operation of drilling vertical vias, the signal vias 67 (for simplicity of the diagram, only the vias are shown as dotted lines in Figure 2 ) often penetrate the power plane P of the power layer 65. More specifically, in the peripheral area 64 of the circuit board 60, in order to ensure that the power vias 68 and the corresponding structure of the power plane P or GPPG of the power layer 65 can be electrically connected, the GPPG structure of the power layer 65 is partially located in the peripheral area 64, so the situation where the signal vias 67 penetrate the power plane P of the power layer 65 often occurs. This situation will cause the power integrity of the power layer 65 to be damaged, making the power test consistency of the power layer 65 worse. At this time, in order to ensure the power test consistency of the power layer 65, a physical capacitor (not shown in the figure) needs to be configured on the upper surface 61 of the circuit board 60 for compensation to ensure the power test consistency of the circuit board 60 for each DUT. SUMMARY OF THE INVENTION

[0005] However, in order to save the time spent on testing, for the requirement of using a probe card to point - measure DUTs, the more DUTs are point - measured in a single measurement, the better. For example, assume that the current probe card point - measures six DUTs at a time. To improve the test efficiency and reduce the testing time, it will develop in the direction of point - measuring eight or more DUTs at a time. That is to say, more probes and contacts and circuits electrically connected to the probes will be configured in the central area of the circuit board to provide more test channels between the DUTs and the tester.

[0006] Since the above - mentioned circuit board needs to configure a space (surface area) for placing physical capacitors on the upper surface of the circuit board to ensure the power test consistency of each DUT, when increasing the number of DUTs point - measured at a time, the probes and contacts and circuits electrically connected to the probes that need to be configured in the central area of the circuit board will occupy a larger circuit board surface area. At the same time, the number of physical capacitors also needs to increase accordingly. However, the size of the circuit board is limited by the tester and cannot be arbitrarily changed. This situation poses challenges to the designer for the configurable area of the circuit board again and again.

[0007] In addition, copper is provided on each power layer and signal layer of the circuit board as circuit traces. However, there are significant differences in the area and position of the copper provided on the power layer and signal layer. When they are pressed together, it may cause the problem of board warping. In other words, in the conventional circuit board, when the power layer and signal layer are arranged in a mixed manner, the problem of board warping needs to be considered in the circuit board manufacturing process. Therefore, the power layer needs to be arranged between two signal layers in the longitudinal position to ensure uniform stress during hot pressing, thereby avoiding the occurrence of board warping problems.

[0008] However, the above-mentioned method of arranging the power layer between two signal layers makes the vias between the power plane of the power layer and the DUT side of the circuit board in the central area of the circuit board have a relatively long length. That is to say, the inductance of this via is relatively large. When the test machine provides power to the DUT, resonance is more likely to occur, causing fluctuations in the power supply, resulting in unstable test results output by the DUT, and making the power supply test consistency of the conventional circuit board worse. Therefore, it is necessary to increase the number of physical capacitors configured on the upper surface of the circuit board to improve the power supply test consistency.

[0009] In view of the above problems, the object of the present invention is to provide a circuit board for semiconductor testing, which can ensure the power supply test consistency of the circuit board for each DUT even when reducing the number of physical capacitors configured while meeting the test requirements of multiple DUTs.

[0010] To achieve the above object, a circuit board for semiconductor testing provided by the present invention is characterized by comprising: a plurality of sub-circuit boards, and at least one interposer layer disposed between the plurality of sub-circuit boards. For example, the circuit board may comprise a first sub-circuit board, an interposer layer, and a second sub-circuit board stacked from bottom to top (i.e., the circuit board comprises two sub-circuit boards and one interposer layer), or, a third sub-circuit board and another interposer layer may be further stacked from bottom to top between the aforementioned interposer layer and the second sub-circuit board (i.e., the circuit board comprises three sub-circuit boards and two interposer layers). Each of the sub-circuit boards comprises a substrate formed of a dielectric material, and a plurality of circuits formed of a conductive material on the substrate for transmitting test signals and power supply signals provided by a testing machine to a probe head. The substrate has an upper surface and a lower surface. The plurality of circuits comprise a plurality of upper contacts located on the upper surface, and a plurality of lower contacts located on the lower surface and electrically connected to the plurality of upper contacts. The interposer layer comprises a plurality of vias, and a plurality of connection conductors disposed in the plurality of vias. Each of the connection conductors electrically connects an upper contact of one sub-circuit board to a lower contact of another sub-circuit board. The circuit board can define a central region and a peripheral region. The plurality of lower contacts of the first sub-circuit board are located in the central region and are used for electrically connecting to the probe head. The plurality of upper contacts of the second sub-circuit board are located in the peripheral region and are used for electrically connecting to the testing machine. The pitch between two adjacent upper contacts of the second sub-circuit board in the peripheral region is greater than the pitch between two adjacent lower contacts of the first sub-circuit board in the central region. The number of upper contacts of the second sub-circuit board located in the peripheral region is greater than the number of lower contacts of the first sub-circuit board located in the peripheral region.

[0011] In the technical solution of the present invention described above, the number of upper contacts of the second sub-circuit board located in the central region is less than the number of lower contacts of the first sub-circuit board located in the central region.

[0012] The number of lower contacts of the first sub-circuit board located in the central region is greater than the number of lower contacts of the first sub-circuit board located in the peripheral region.

[0013] The thickness of the substrate of the first sub-circuit board is greater than the thickness of the substrate of the second sub-circuit board.

[0014] The first sub-circuit board comprises a first ground layer, a first power layer, a second ground layer, a second power layer, and a third ground layer stacked in sequence from its upper surface to its lower surface.

[0015] The total number of upper contacts of the second sub-circuit board is less than the total number of lower contacts of the first sub-circuit board.

[0016] An electronic component is disposed in a through hole of the intermediate layer, and the electronic component is electrically connected to a circuit of a sub-circuit board.

[0017] The second sub-circuit board further includes an electronic component disposed on a contact point thereon.

[0018] The dielectric constant of the substrate of the first sub-circuit board is greater than the dielectric constant of the substrate of the second sub-circuit board.

[0019] Among the multiple sub-circuit boards, there is further a third sub-circuit board located above the first sub-circuit board and below the second sub-circuit board. The dielectric constant of the substrate of the third sub-circuit board is less than the dielectric constant of the substrate of the first sub-circuit board and greater than the dielectric constant of the substrate of the second sub-circuit board.

[0020] Among the multiple sub-circuit boards, there is further a third sub-circuit board located above the first sub-circuit board and below the second sub-circuit board. The thickness of the substrate of the third sub-circuit board is less than the thickness of the substrate of the first sub-circuit board and greater than the thickness of the substrate of the second sub-circuit board.

[0021] The number of upper contact points for transmitting test signals in the peripheral area of the second sub-circuit board is greater than the number of upper contact points for transmitting power signals in the peripheral area of the second sub-circuit board; the number of lower contact points for transmitting power signals in the peripheral area of the first sub-circuit board is greater than the number of lower contact points for transmitting test signals in the peripheral area of the first sub-circuit board.

[0022] The number of lower contact points for transmitting power signals in the peripheral area of the first sub-circuit board is greater than the number of lower contact points for transmitting test signals in the peripheral area of the first sub-circuit board; the number of upper contact points for transmitting test signals in the central area of the second sub-circuit board is greater than the number of upper contact points for transmitting power signals in the central area of the second sub-circuit board.

[0023] Adopting the above technical solution, according to the number of circuit board layers required for semiconductor testing, the present invention can connect two sub-circuit boards through an interposer, connect three sub-circuit boards through two interposers, or connect more than three sub-circuit boards through more than two interposers, thereby forming a multi-layer circuit board. In other words, the sub-circuit boards are first manufactured to have horizontal conductive lines and vertical vias (both belonging to the aforementioned lines), and then the sub-circuit boards are combined through the interposer, so that the lines of different sub-circuit boards are electrically connected to each other. In this way, the vertical vias of the circuit board are shorter, so the problems of difficult via setting and long residual segments can be avoided. Moreover, by using the interposer to bond the vertical vias of two sub-circuit boards and electrically connect the corresponding contacts between the two sub-circuit boards, the production qualification rate of the circuit board of the present invention can be ensured. In addition, the circuit board of the present invention can use the first sub-circuit board with the largest thickness as the substrate, and it is easier to maintain the flatness of the substrate. When stacking the sub-circuit boards through the interposer, the situation of poor flatness such as board bending or warping can be avoided, thereby improving the qualification rate of the circuit board. Furthermore, the dielectric constants of the substrates of different sub-circuit boards are different, which is beneficial to layout the lines for different purposes or requirements on different sub-circuit boards respectively. The pitch between adjacent upper contacts in the peripheral area of the second sub-circuit board is greater than the pitch between adjacent lower contacts in the central area of the first sub-circuit board. This configuration can make the signal output components of the testing machine more easily contact the upper contacts in the peripheral area of the second sub-circuit board respectively, thereby avoiding short circuits.

[0024] Furthermore, in the present invention, the first sub-board is circuit-layouted for power integrity, and the second sub-board is circuit-layouted for signal integrity, so as to avoid interference between test signals and power signals. Compared with the conventional method of mixing the power layer and the signal layer on a single circuit board, the circuit board architecture of the present invention is to separately fabricate two or more sub-boards and then connect them through an interposer layer. The first sub-board closest to the device under test is used as the PI sub-board mainly for power lines, and the second sub-board closest to the tester is used as the SI sub-board mainly for signal lines. Therefore, when performing the vertical vias operation of the vias, the PI sub-board and the SI sub-board are drilled separately. Therefore, compared with the conventional situation where the power layer and the signal layer are mixed on a single circuit board and drilled together, the present invention can greatly reduce the situation where the vias for transmitting test signals penetrate the power plane, and then a better power test consistency can be generated. The number of physical capacitors configured on the upper surface of the circuit board can be reduced. Without increasing the size of the circuit board, the power test consistency of the circuit board can also be ensured. Since the SI sub-board is close to the tester and the PI sub-board is close to the device under test, most of the vertical vias for transmitting test signals in the peripheral area of the SI sub-board do not need to be connected to the vertical vias in the peripheral area of the PI sub-board. Therefore, the number of upper and lower contacts in the peripheral area of the second sub-board is greater than the number of upper and lower contacts in the peripheral area of the first sub-board. This feature can avoid the problem that the vertical vias for transmitting test signals in the peripheral area of the PI sub-board penetrate the power plane, and then the power test consistency of the circuit board can be ensured.

[0025] In addition, since the circuit board of the present invention is divided into the PI sub-board and the SI sub-board as described above, the areas and positions of the copper layers in the PI sub-board are similar to each other, and the areas and positions of the copper layers in the SI sub-board are similar to each other. Therefore, the problem of board warping of a single sub-board can be avoided. The PI sub-board is configured at the position closest to the device under test, so that within the central area of the circuit board, the length of the vertical vias for transmitting power signals between the power plane of the PI sub-board and the device-under-test side of the circuit board can be shortened as much as possible. Therefore, compared with the above-mentioned conventional single circuit board, the inductance of the vertical vias for transmitting power signals in the PI sub-board of the present invention is smaller, and resonance is less likely to occur when the tester provides power to the device under test. Therefore, the test results output by the device under test are more stable, and the power test consistency is better. Therefore, the number of physical capacitors configured on the upper surface of the circuit board can be reduced. Description of the Drawings

[0026] Figure 1 and Figure 2 are respectively the plan view and the sectional view of the conventional circuit board for semiconductor testing;

[0027] Figure 3It is a cross-sectional schematic diagram of a circuit board for semiconductor testing provided by a first preferred embodiment of the present invention;

[0028] Figure 4 is Figure 3 an exploded view of;

[0029] Figure 5 It is a top view schematic diagram of the circuit board;

[0030] Figure 6 It is a cross-sectional schematic diagram of a first sub-circuit board of the circuit board;

[0031] Figure 7 It is a cross-sectional schematic diagram of a circuit board for semiconductor testing provided by a second preferred embodiment of the present invention. Detailed implementation manners

[0032] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present invention fall within the scope of protection of the present invention.

[0033] The applicant hereby explains that in the embodiments and drawings to be introduced below, the same reference numerals represent the same or similar elements or their structural features. It should be noted that the elements and structures in the drawings are for illustrative convenience and are not drawn according to actual proportions and quantities, and if possible in implementation, the features of different embodiments can be applied interactively.

[0034] Please first refer to Figure 3 and Figure 4 A circuit board 10 for semiconductor testing provided by a first preferred embodiment of the present invention includes a first sub-circuit board 20, an interposer 30, and a second sub-circuit board 40 stacked from bottom to top.

[0035] The first sub-circuit board 20 includes a substrate 21 formed of a dielectric material and a plurality of circuits formed of a conductive material on the substrate 21. The plurality of circuits include a plurality of horizontal conductive circuits 22 (the number is not limited, and only one of them is shown in the drawing), and a plurality of vertical vias 23. In detail, the first sub-circuit board 20 is a multi-layer circuit board formed by laminating multiple base materials. Horizontal conductive circuits 22 are provided on the surfaces where some of the base materials are joined. In other words, the substrate 21 is actually composed of multiple base materials. However, for the sake of simplifying the drawings, in the drawings of the present invention, except for Figure 6Except for this, the substrate 21 is drawn as a single entity. After the substrate 21 and the horizontal conductive lines 22 are manufactured, the vertical vias 23 are then provided. The vertical vias 23 are usually electroplated vias. The way of setting them is to first drill a through hole penetrating the upper surface 211 and the lower surface 212 of the substrate 21 by means of, for example, mechanical drilling or laser drilling, and then copper is plated on the inner wall of the through hole and the openings at both ends of the through hole. Thus, each vertical via 23 includes an upper contact 231 located on the upper surface 211, a lower contact 232 located on the lower surface 212, and a conductive inner wall 233 electrically connecting the upper contact 231 and the lower contact 232. In addition, each vertical via 23 may further include an insulator 234 filling its internal space. Both ends of each horizontal conductive line 22 are respectively connected to the conductive inner wall 233 of a vertical via 23, so that the upper and lower contacts 231, 232 not located on the same longitudinal axis can be electrically connected to each other through the horizontal conductive line 22.

[0036] The second sub-circuit board 40 is similar to the first sub-circuit board 20 and includes a substrate 41 formed of a dielectric material and a plurality of lines formed on the substrate 41 by a conductive material. The lines include a plurality of horizontal conductive lines 42 (the number is not limited, and only one of them is shown in the figure), and a plurality of vertical vias 43. In other words, the substrate 41 is actually composed of multiple layers of base materials. However, for the sake of simplifying the figure, the substrate 41 is drawn as a single entity in the present invention. Each vertical via 43 includes an upper contact 431 located on the upper surface 411 of the substrate 41, a lower contact 432 located on the lower surface 412 of the substrate 41, a conductive inner wall 433 electrically connecting the upper contact 431 and the lower contact 432, and an insulator 434 filling its internal space. Both ends of each horizontal conductive line 42 are respectively connected to the conductive inner wall 433 of a vertical via 43, so that the upper and lower contacts 431, 432 not located on the same longitudinal axis can be electrically connected to each other through the horizontal conductive line 42.

[0037] The interposer 30 includes an upper surface 31 connected to the second sub-circuit board 40, a lower surface 32 connected to the first sub-circuit board 20, a plurality of through holes 33 penetrating the upper surface 31 and the lower surface 32, and a plurality of connection conductors 34 provided in the through holes 33. The position of each through hole 33 corresponds to the vertical vias 23, 43 of the first and second sub-circuit boards 20, 40. Each connection conductor 34 electrically connects the upper contact 231 of the first sub-circuit board 20 and the lower contact 432 of the second sub-circuit board 40 located on the same longitudinal axis. In addition, some through holes 33 of the interposer 30 can accommodate an electronic component 35. The electronic component 35 does not necessarily need to be electrically connected to the upper contact 231 of the first sub-circuit board 20 and the lower contact 432 of the second sub-circuit board 40 at the same time. For example Figure 1The electronic component 35 therein is only electrically connected to the upper contact 231 of the first sub-board 20. Therefore, the upper contact 231 of the first sub-board 20 and the lower contact 432 of the second sub-board 40 may not correspond one-to-one. In addition, the upper contact 431 of the second sub-board 40 can also be electrically connected to an electronic component 44. The electronic components 35 and 44 can be capacitors, inductors, resistors, radio frequency components, connectors, relays, etc., and can be arranged according to requirements.

[0038] The circuit board 10 of the present invention is mainly used for semiconductor testing, that is, as the main circuit board of a probe card. Through the circuit layout of the first and second sub-boards 20 and 40 and the configuration of the connecting conductors 34 of the intermediate layer 30, the circuit board 10 can have a telecommunication transmission path that meets the testing requirements and a grounded line with impedance matching. The drawings of the present invention only schematically show a small number of lines to simplify the drawings and facilitate the description. Compared with the overall thickness of the circuit board 10, the thicknesses of the sub-boards 20 and 40 are much smaller. Therefore, their longitudinal vias 23 and 43 are short, which can avoid problems such as difficult via setting and long residual segments.

[0039] Please refer to Figure 3 and Figure 5 , the circuit board 10 can define a central region 12 and a peripheral region 14. Figure 5 Only schematically shows that the circuit board 10 may be circular, and the central region 12 and the peripheral region 14 are roughly distinguished by imaginary lines. Other components and features of the circuit board 10 are not shown in Figure 3 and Figure 4 The circuit board of the present invention can also be like Figure 1is shown as a square. Most of the lower contacts 232 of the first sub-board 20 are located in the central area 12 and are used to be electrically connected directly to a probe head (not shown in the figure) or to be electrically connected to the probe head through a space converter (not shown in the figure), thereby forming a probe card. Most of the upper contacts 431 of the second sub-board 40 are located in the peripheral area 14 and are used to be electrically connected to a testing machine (not shown in the figure), so that the power signal and the test signal provided by the testing machine are transmitted to a device under test (not shown in the figure) through the probes of the aforementioned probe head. In other words, the top side of the circuit board 10 (i.e., the upper surface 411 of the second sub-board 40) is the tester side facing the testing machine, and the bottom side of the circuit board 10 (i.e., the lower surface 212 of the first sub-board 20) is the wafer side facing the device under test (such as a wafer). The testing machine provides power and test signals to the upper contacts 431 in the peripheral area 14, and the power and test signals are then sequentially transmitted to the lower contacts 232 in the central area 12 through the circuit of the second sub-board 40, the connecting conductors 34 of the interposer 30, and the circuit of the first sub-board 20, and then transmitted to the device under test through the probe head. The pitch between two adjacent upper contacts 431 of the second sub-board 40 in the peripheral area 14 is greater than the pitch between two adjacent lower contacts 232 of the first sub-board 20 in the central area 12. This configuration can make the signal output components of the testing machine (such as the elastic contact components commonly known as pogo pins) more easily contact the upper contacts 431 of the second sub-board 40 in the peripheral area 14 respectively, thereby avoiding short circuits. Further, most of the lower contacts 232 of the first sub-board 20 are located in the central area 12 and are used to be electrically connected directly to a probe head, which means that the first sub-board 20 is the sub-board at the bottommost side of the circuit board 10. Most of the upper contacts 431 of the second sub-board 40 are located in the peripheral area 14 and are used to be electrically connected to a testing machine, which means that the second sub-board 40 is the sub-board at the topmost side of the circuit board 10.

[0040] To facilitate the aforementioned transmission of power and test signals, the number of upper contacts 431 of the second sub-board 40 located in the peripheral area 14 is greater than the number of lower contacts 232 of the first sub-board 20 located in the peripheral area 14, the number of upper contacts 431 of the second sub-board 40 located in the central area 12 is less than the number of lower contacts 232 of the first sub-board 20 located in the central area 12, the total number of upper contacts 431 of the second sub-board 40 is less than the total number of lower contacts 232 of the first sub-board 20, and the number of lower contacts 232 of the first sub-board 20 located in the central area 12 is greater than the number of lower contacts 232 of the first sub-board 20 located in the peripheral area 14.

[0041] In the present invention, the thickness T1 of the substrate 21 of the first sub-circuit board 20 may be greater than or equal to the thickness T2 of the substrate 41 of the second sub-circuit board 40. Preferably, the configuration is such that the thickness T1 is greater than the thickness T2 as provided in this embodiment. In addition, the dielectric constant of the material of the substrate 21 of the first sub-circuit board 20 may (but is not limited to) be greater than the dielectric constant of the material of the substrate 41 of the second sub-circuit board 40. Such a feature is conducive to separately arranging circuits for different purposes or requirements on different sub-circuit boards, and materials with different dielectric constants have different colors and can be distinguished by appearance.

[0042] Furthermore, in the present invention, the first sub-circuit board 20 is used for circuit layout for power integrity (PI for short), and the second sub-circuit board 40 is used for circuit layout for signal integrity (SI for short). Therefore, the first sub-circuit board 20 is also referred to as the PI sub-board, and the second sub-circuit board 40 is also referred to as the SI sub-board. That is, most of the horizontal conductive lines 42 of the second sub-circuit board 40 are used for test signal paths, and some can be used for secondary power paths, while most of the horizontal conductive lines 22 of the first sub-circuit board 20 are used for main power paths, so that most of the main power paths are close to the device under test, which is conducive to the detection of the application processor (AP for short) chip of the mobile phone.

[0043] In other words, most of the vertical vias 43 for transmitting test signals in the peripheral region 14 of the second sub-circuit board 40 are electrically connected to the vertical vias 43 in the central region 12 through the horizontal conductive lines 42. Most of the vertical vias 43 for transmitting power signals in the peripheral region 14 of the second sub-circuit board 40 are not connected to the horizontal conductive lines 42. That is, there may be a small part (or maybe none at all) of the horizontal conductive lines 42 and the vertical vias 43 in the central region 12 for transmitting power signals. Therefore, the number of upper and lower contacts 431, 432 for transmitting test signals in the central region 12 of the second sub-circuit board 40 is greater than the number of upper and lower contacts 431, 432 for transmitting power signals in the central region 12 of the second sub-circuit board 40 (this number may be zero). Relatively speaking, among the vertical vias 43 in the peripheral region 14 of the second sub-circuit board 40, those electrically connected to the vertical vias 43 in the peripheral region 14 of the first sub-circuit board 20 through the intermediate layer 30 are mostly for transmitting power signals, and the power signals are transmitted to the vertical vias 23 in the central region 12 through the horizontal conductive lines 22 of the first sub-circuit board 20. That is, there may be a small part (or maybe none at all) of the horizontal conductive lines 22 and the vertical vias 23 in the peripheral region 14 for transmitting test signals. Therefore, the number of upper and lower contacts 231, 232 for transmitting power signals in the peripheral region 14 of the first sub-circuit board 20 is greater than the number of upper and lower contacts 231, 232 for transmitting test signals in the peripheral region 14 of the first sub-circuit board 20 (this number may be zero). In addition, the number of upper and lower contacts 431, 432 for transmitting test signals in the peripheral region 14 of the second sub-circuit board 40 is greater than the number of upper and lower contacts 431, 432 for transmitting power signals in the peripheral region 14 of the second sub-circuit board 40. In practice, after the circuit board is manufactured, the upper contact 431 of the second sub-circuit board 40 and the lower contact 232 of the first sub-circuit board 20 can be measured using micro-resistance to determine whether each contact is used to transmit power signals or test signals. For example, contacts with an impedance less than 100 milliohms (mΩ) are contacts for transmitting power signals, and the others are contacts for transmitting test signals. According to the number of contacts measured and statistically analyzed in this way, the comparison of the number of upper and lower contacts for transmitting power signals and test signals in the central and peripheral regions of the first and second sub-circuit boards described above can be carried out.

[0044] Regarding the upper contact 431 for transmitting power signals or test signals in the peripheral region 14 of the second sub-circuit board 40, since the position for the test machine to transmit power signals or test signals is fixed, as long as there is a position diagram for transmitting power signals or test signals corresponding to the model of the test machine used or data that can explain the corresponding signals, the position of the upper contact 431 for transmitting power signals or test signals in the peripheral region 14 of the corresponding second sub-circuit board 40 can be determined.

[0045] Regarding the circuit design of the vertical vias 23 and 43, the stub of the via 43 can be removed by back drilling, or the thicknesses of the first and second daughter boards can be controlled so that the vertical vias 23 and 43 cannot form stubs, in order to avoid the deterioration of high-frequency loss during high-frequency and high-speed testing.

[0046] In terms of the horizontal conductive lines, the number of the horizontal conductive lines 22 on the first daughter board 20 for transmitting power signals is greater than the number of the horizontal conductive lines 22 on the first daughter board 20 for transmitting test signals (this number may be zero), and the number of the horizontal conductive lines 42 on the second daughter board 40 for transmitting test signals is greater than the number of the horizontal conductive lines 42 on the second daughter board 40 for transmitting power signals (this number may be zero).

[0047] Since the circuit layout for power integrity and the circuit layout for signal integrity are fabricated on two separate daughter boards, namely the PI daughter board 20 and the SI daughter board 40, it is possible to avoid the vertical via 43 of the SI daughter board 40 from penetrating the power layer of the PI daughter board 20. Therefore, compared with the conventional situation where the power layer and the signal layer are mixed and arranged on a single circuit board, the present invention can achieve better power test consistency, and thus the number of physical capacitors to be configured can be relatively small. Furthermore, since the SI daughter board 40 is close to the testing machine and the PI daughter board 20 is close to the device under test, most of the vertical vias 43 for transmitting test signals in the peripheral area 14 of the SI daughter board 40 do not need to be connected to the vertical vias 23 in the peripheral area 14 of the PI daughter board 20. Therefore, the number of upper and lower contacts 431 and 432 of the second daughter board 40 in the peripheral area 14 is greater than the number of upper and lower contacts 231 and 232 of the first daughter board 20 in the peripheral area 14. This feature can avoid the problem that the vertical vias for transmitting test signals in the peripheral area 14 of the PI daughter board 20 penetrate the power plane, and thus can ensure the power test consistency of the circuit board. Moreover, by using the intermediate layer 30 to bond the vertical vias of the two daughter boards and make electrical connections between the corresponding contacts of the two daughter boards, the production qualification rate of the circuit board of the present invention can be ensured. In addition, the areas and positions of the copper layers within the PI daughter board 20 are close to each other, and the areas and positions of the copper layers within the SI daughter board 40 are close to each other. Therefore, the problem of board warping of a single daughter board can be avoided. Since the PI daughter board 20 is arranged at the position closest to the device under test, within the central area of the circuit board, the length of the vertical via for transmitting power signals from the power plane of the PI daughter board 20 to the side of the device under test of the circuit board can be shortened as much as possible, making its inductance small and not likely to generate resonance when the testing machine supplies power to the device under test. Therefore, the test results output by the device under test are stable, resulting in good power test consistency, and thus the number of physical capacitors configured on the upper surface of the circuit board can be relatively small.

[0048] Moreover, the first sub-circuit board 20 has a relatively large thickness, and its lateral conductive lines 22 can adopt a design with two or more layers stacked to facilitate the electrical connection of the main power path. For example, as Figure 6 shown, the first sub-circuit board 20 may include a first ground layer G1, a first power layer P1, a second ground layer G2, a second power layer P2, and a third ground layer G3 that are sequentially stacked from its upper surface 211 to its lower surface 212. Hereinafter, this configuration will also be referred to as the GPGPG structure. As described above, the first sub-circuit board 20 is formed by laminating multiple substrates, and the foregoing ground layers G1 to G3 and power layers P1 to P2 are conductive layers provided on the mating surfaces of the substrates. To simplify the drawings and facilitate the description, Figure 6 only a straight line is used to represent each of the foregoing ground layers G1 to G3 and power layers P1 to P2 respectively in the figure, and other components and features of the first sub-circuit board 20 are not shown. In this GPGPG structure, an equivalent capacitance effect can be generated between the first ground layer G1 and the second ground layer G2, and between the second ground layer G2 and the third ground layer G3. Therefore, the equivalent capacitance effect of the PI sub-board 20 can be improved, which is also beneficial to the consistency of power supply testing, and thus the number of physical capacitors used can be reduced. In addition to the foregoing advantages, this GPGPG structure also makes the PI sub-board 20 have a relatively large thickness. Therefore, it can be recognized from the appearance of the PI sub-board 20 that it has the GPGPG structure. Moreover, the circuit board 10 of the present invention uses the first sub-circuit board 20 with a relatively large thickness as the base, and it is easier to maintain the flatness of the base. When stacking the second sub-circuit board 40 through the interposer 30, situations such as board bending or warping with poor flatness can be avoided, and thus the yield of the circuit board 10 can be improved.

[0049] In contrast, a conventional single circuit board with a GPPG stacking method and used for six DUTs is about 80 layers. If the foregoing GPGPG structure is to be applied to a single circuit board and the probe card is to be developed in the direction of single-point testing eight or more DUTs at a time, the number of stacked boards of the circuit board will be as high as more than 100 layers. According to the current circuit board stacking and lamination technology, the circuit board needs to be provided with vias penetrating its top and bottom surfaces, such as electroplated vias. Limited by drilling technology and aspect ratio, the more layers and the greater the thickness of the circuit board, the higher the drilling difficulty, and even drilling may be impossible under specific size requirements. Moreover, the deeper the via, the wider the via needs to be drilled, making it difficult to reduce the center spacing between adjacent vias, and thus it is difficult to meet the test requirements of fine pitch. It can be seen from this that the method of separately manufacturing the PI sub-board 20 and the SI sub-board 40 and then connecting them through the interposer 30 in the present invention is more suitable for adopting the GPGPG structure than the conventional circuit board.

[0050] In addition, the PI circuit layout and the SI circuit layout are separately disposed on different sub-boards, which can avoid the mutual interference between the test signal and the power signal, and the PI circuit layout disposed on the first sub-board 20 with a larger dielectric constant of the substrate material can reduce the required number of capacitors. Moreover, the circuit board 10 can use the first sub-board 20 with a larger thickness as the base, which can more easily maintain the flatness of the base, and can avoid the situation of poor flatness such as board bending or warping when stacking the second sub-board 40 through the interposer 30, thereby improving the qualification rate of the circuit board 10. The feature that the first sub-board 20 has a larger thickness is not limited to being achieved by the aforementioned GPGPG structure. For example, the thickness of the power layer of the first sub-board 20 can be increased, which can not only increase the thickness of the first sub-board 20, but also reduce the impedance value of the power line, and can also achieve the effect of improving the power consistency.

[0051] According to the number of circuit board layers required for semiconductor testing, the present invention can also connect two or more sub-boards through more than one interposer. For example Figure 7 the circuit board 10' provided by a second preferred embodiment of the present invention shown in the figure is similar to the aforementioned circuit board 10, except that a third sub-board 40' and another interposer 30' are further stacked between the interposer 30 and the second sub-board 40, that is, the circuit board 10' includes three sub-boards and two interposers. The structures of the interposer 30' and the third sub-board 40' are respectively similar to the structures of the aforementioned interposer 30 and the second sub-board 40, and the applicant will not repeat them here, and some structural features of the interposer 30' and the third sub-board 40' are not labeled in the drawings. The thickness T3 of the substrate 41' of the third sub-board 40' is less than the thickness T1 of the substrate 21 of the first sub-board 20 and greater than the thickness T2 of the substrate 41 of the second sub-board 40. The dielectric constant of the material of the substrate 41' of the third sub-board 40' is less than the dielectric constant of the material of the substrate 21 of the first sub-board 20 and greater than the dielectric constant of the material of the substrate 41 of the second sub-board 40. The interposer 30 is disposed between the first sub-board 20 and the third sub-board 40', and the connecting conductor 34 of the interposer 30 is electrically connected to the upper contact 231 of the first sub-board 20 and the lower contact 432' of the third sub-board 40' located on the same longitudinal axis. The interposer 30' is disposed between the second sub-board 40 and the third sub-board 40', and the connecting conductor 34' of the interposer 30' is electrically connected to the upper contact 431' of the third sub-board 40' and the lower contact 432 of the second sub-board 40 located on the same longitudinal axis.

[0052] In Figure 1 the circuit board 10 shown or Figure 5In the shown circuit board 10', the first sub-circuit board 20 can be a low-impedance power signal substrate. Its maximum thickness is beneficial to maintaining the flatness of the circuit board, and its highest dielectric constant is beneficial to controlling the capacitive reactance of the capacitor to provide a low power impedance, so that the power signal transmission will not attenuate. The second sub-circuit board 40 can be a high-speed signal substrate. Its lowest dielectric constant is beneficial to controlling the capacitive reactance of the capacitor to provide a high-impedance match, so that the test signal transmission will not attenuate. Thus, the circuit board of the present invention can meet the requirements of high-frequency and high-speed testing and the requirements of power transmission and supply to the device under test, and can reduce the power interference caused by the high-speed signal penetrating the power layer. And Figure 5 The third sub-circuit board 40' of the shown circuit board 10' can be a low-speed signal and power line substrate, which is mainly used to set the lines of medium and low-frequency signals with impedance requirements lower than those of high-speed signals, and the lines of secondary power signals with impedance requirements higher than those of the main power signal.

[0053] Finally, it must be stated again that the constituent elements disclosed in the foregoing embodiments of the present invention are only for illustrative purposes and are not used to limit the patent protection scope of this case. The substitution or change of other equivalent elements should also be covered by the patent protection scope of this case.

Claims

1. A circuit board for semiconductor testing, characterized in that Comprising: A plurality of sub - circuit boards, each of the sub - circuit boards comprising a substrate formed of a dielectric material, and a plurality of circuits formed of a conductive material on the substrate for transmitting test signals and power supply signals provided by a testing machine to a probe head. The substrate has an upper surface and a lower surface. The plurality of circuits include a plurality of upper contacts located on the upper surface, and a plurality of lower contacts located on the lower surface and electrically connected to the plurality of upper contacts; At least one intermediate layer disposed between the plurality of sub - circuit boards. The intermediate layer includes a plurality of vias and a plurality of connection conductors disposed in the plurality of vias. Each of the connection conductors electrically connects an upper contact of one sub - circuit board to a lower contact of another sub - circuit board; Wherein, the circuit board can define a central region and a peripheral region. The plurality of sub - circuit boards include a first sub - circuit board and a second sub - circuit board located above the first sub - circuit board. The plurality of lower contacts of the first sub - circuit board are located in the central region and are used for electrically connecting with the probe head. The plurality of upper contacts of the second sub - circuit board are located in the peripheral region and are used for electrically connecting with the testing machine. The pitch between two adjacent upper contacts of the second sub - circuit board in the peripheral region is greater than the pitch between two adjacent lower contacts of the first sub - circuit board in the central region. The number of upper contacts of the second sub - circuit board located in the peripheral region is greater than the number of lower contacts of the first sub - circuit board located in the peripheral region.

2. The circuit board for semiconductor testing according to claim 1, wherein: The number of upper contacts of the second sub - circuit board located in the central region is less than the number of lower contacts of the first sub - circuit board located in the central region.

3. The circuit board for semiconductor testing according to claim 1, characterized in that: The number of lower contacts of the first sub - circuit board located in the central region is greater than the number of lower contacts of the first sub - circuit board located in the peripheral region.

4. The circuit board for semiconductor testing according to claim 1, wherein: The thickness of the substrate of the first sub - circuit board is greater than the thickness of the substrate of the second sub - circuit board.

5. The circuit board for semiconductor testing according to claim 1, wherein: The first sub - circuit board includes a first ground layer, a first power layer, a second ground layer, a second power layer, and a third ground layer stacked in sequence from its upper surface to its lower surface.

6. The circuit board for semiconductor testing according to claim 1, wherein: The total number of upper contacts of the second sub - circuit board is less than the total number of lower contacts of the first sub - circuit board.

7. The circuit board for semiconductor testing according to claim 1, characterized in that: An electronic component is disposed in one of the vias of the intermediate layer, and the electronic component is electrically connected to the circuit of one of the sub - circuit boards.

8. The circuit board for semiconductor testing according to claim 1, wherein: The second sub - circuit board further includes an electronic component disposed on its upper contacts.

9. The circuit board for semiconductor testing according to claim 1, wherein: The dielectric constant of the material of the substrate of the first sub - circuit board is greater than the dielectric constant of the material of the substrate of the second sub - circuit board.

10. The circuit board for semiconductor testing according to claim 1, wherein: The plurality of sub - circuit boards further include a third sub - circuit board located above the first sub - circuit board and below the second sub - circuit board. The dielectric constant of the material of the substrate of the third sub - circuit board is less than the dielectric constant of the material of the substrate of the first sub - circuit board and greater than the dielectric constant of the material of the substrate of the second sub - circuit board.

11. The circuit board for semiconductor testing according to claim 1, wherein: Among the multiple sub-circuit boards, there is also a third sub-circuit board located above the first sub-circuit board and below the second sub-circuit board. The thickness of the substrate of the third sub-circuit board is less than the thickness of the substrate of the first sub-circuit board and greater than the thickness of the substrate of the second sub-circuit board.

12. The circuit board for semiconductor testing according to claim 1, characterized in that: The number of upper contact points for transmitting test signals in the peripheral area of the second sub-circuit board is greater than the number of upper contact points for transmitting power signals in the peripheral area of the second sub-circuit board; the number of lower contact points for transmitting power signals in the peripheral area of the first sub-circuit board is greater than the number of lower contact points for transmitting test signals in the peripheral area of the first sub-circuit board.

13. The circuit board for semiconductor testing according to claim 1, characterized in that: The number of lower contact points for transmitting power signals in the peripheral area of the first sub-circuit board is greater than the number of lower contact points for transmitting test signals in the peripheral area of the first sub-circuit board; the number of upper contact points for transmitting test signals in the central area of the second sub-circuit board is greater than the number of upper contact points for transmitting power signals in the central area of the second sub-circuit board.

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