Memory device and method of manufacturing the same

Abstract

The present invention provides a memory device and a manufacturing method thereof, wherein the memory device comprises: a substrate, a stacking structure, a channel layer and a charge storage structure. The stacking structure is located on the substrate, and comprises a plurality of insulating layers and a plurality of conductive layers stacked alternately, and the stacking structure has a hole. The channel layer is located in the hole, and comprises a first part and a second part. The number of grain boundaries of the second part is lower than the number of grain boundaries of the first part. The charge storage structure is located between the first part and the plurality of conductive layers, and the charge storage structure and the second part sandwich the first part therebetween.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and in particular to a storage device and a manufacturing method thereof. Background Art

[0002] Flash memory has become a widely used storage device in many electronic devices because it has the advantage that the stored data will not disappear after power failure. Although the three-dimensional NAND flash memory developed with the evolution of technology can improve the integration of storage devices, it also has many related challenges. Summary of the invention

[0003] The invention is directed to a memory device and a manufacturing method thereof, which can improve the quality of a channel layer and reduce the variation of a read current.

[0004] According to an embodiment of the present invention, a memory device is proposed, comprising: a substrate; a stacking structure located on the substrate, comprising an insulating layer and a plurality of conductive layers stacked alternately, wherein the stacking structure has a hole; a channel layer located in the hole, comprising a first portion; and a second portion, wherein the number of grain boundaries of the second portion is lower than the number of grain boundaries of the first portion; and a charge storage structure located between the first portion and the plurality of conductive layers, wherein the charge storage structure and the second portion sandwich the first portion.

[0005] According to an embodiment of the present invention, a method for manufacturing a memory device is proposed, comprising: forming a stacking structure on a substrate, the stacking structure comprising an insulating layer and a plurality of conductive layers stacked alternately; forming a hole in the stacking structure; forming a charge storage structure on a sidewall of the stacking structure in the hole; forming a channel layer in the hole, comprising forming a first portion on a sidewall of the charge storage structure in the hole; and forming a second portion on a sidewall of the first portion in the hole, the number of grain boundaries of the second portion being lower than the number of grain boundaries of the first portion.

[0006] According to an embodiment of the present invention, a method for manufacturing a memory device is proposed, comprising: forming a stacking structure on a substrate, the stacking structure comprising a first material layer and a plurality of second material layers alternately stacked; forming a hole in the stacking structure; forming a channel layer in the hole, comprising forming a first portion on a sidewall of the stacking structure in the hole; and forming a second portion on a sidewall of the first portion in the hole, the number of grain boundaries of the second portion being lower than the number of grain boundaries of the first portion; forming a filling layer in the hole to cover the sidewall of the second portion; replacing the plurality of second material layers with a plurality of conductor layers; and forming a charge storage structure between the plurality of conductor layers and the plurality of first material layers.

[0007] Based on the above, in various embodiments of the present invention, the channel layer includes a first portion and a second portion. The second portion has a low grain boundary density, which can reduce the variation of the read current. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figures 1A to 1D is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0009] FIG. 2A to FIG. 2I is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention;

[0010] FIG. 3A to FIG. 3D It is a cross-sectional schematic diagram showing an intermediate stage of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention. DETAILED DESCRIPTION

[0011] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0012] Figures 1A to 1D It is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0013] Please refer to Figure 1A , providing a substrate 10. The substrate 10 may be a semiconductor substrate, such as a silicon-containing substrate. A dielectric layer 12 having an opening 14 has been formed on the substrate 10. The dielectric layer 12 may be a single layer, a composite layer, or a stacked layer. The substrate 10 and the dielectric layer 12 may include other layers or devices. An amorphous silicon layer 16 is formed on the sidewall of the dielectric layer 12 in the opening 14. The amorphous silicon layer 16 may be deposited by chemical vapor deposition. The amorphous silicon layer 16 may have a dopant or may not have a dopant. The dopant may be a P-type such as boron, or an N-type such as phosphorus or arsenic.

[0014] Please refer to Figure 1B The amorphous silicon layer 16 is subjected to an annealing process 17 to form a polysilicon layer 16a. The polysilicon layer 16a has a plurality of grain boundaries 18. There are a plurality of intersections C between the grain boundaries 18. The thickness T1 of the polysilicon layer 16a is, for example, 10 nm to 20 nm.

[0015] Please refer to Figure 1B and Figure 1CIf the thickness T1 of the polysilicon layer 16a is thicker and there are more grain boundaries 18 and intersections C, it will be detrimental to the flow of current. The embodiment of the present invention can selectively perform an etching process, such as anisotropic etching, to thin the thickness T1 of the polysilicon layer 16a to form a polysilicon layer 16b with a thickness T2. The thickness T2 of the polysilicon layer 16b is, for example, 1nm to 5nm. The density of the grain boundaries 18 in the polysilicon layer 16b is reduced due to the thinning of the thickness. The intersections C between the grain boundaries 18 are also reduced or disappear.

[0016] Please refer to Figure 1D , an epitaxial process is performed to form an epitaxial silicon layer 20 on the sidewall of the polysilicon layer 16b in the opening 14. The epitaxial silicon layer 20 may not fill the opening 14, or may fill the remaining space of the opening 14 (not shown). The method for forming the epitaxial silicon layer 20 is, for example, hot wire chemical vapor deposition. In some embodiments, methane and argon are used to deposit at a temperature of 100 to 550 degrees Celsius and a pressure of 1x10-2 to 1 Torr. The epitaxial silicon layer 20 and the polysilicon layer 16b can be used together as a channel layer 22. The polysilicon layer 16b serves as the first part P1 of the channel layer 22; the epitaxial silicon layer 20 serves as the second part P2 of the channel layer 22. In some embodiments, the thickness T3 of the second part P2 of the channel layer 22 accounts for 75% to 95% of the total thickness (T2+T3) of the channel layer 22. Compared to the polysilicon layer 16b, the epitaxial silicon layer 20 has a lower grain boundary density, so the grain boundary density of the second portion P2 of the channel layer 22 is less than that of the first portion P1. When the channel layer 22 is applied to a memory device, the variation of the read current can be reduced. Although the channel layer 22 is described by taking the polysilicon layer 16b as the first portion P1 and the epitaxial silicon layer 20 as the second portion P2 as an example, the present invention is not limited thereto. In other embodiments, other suitable types of polycrystalline layers and epitaxial layers can also be used as the first portion P1 and the second portion P2 of the channel layer 22, respectively.

[0017] The process of forming the channel layer described above can be applied to the process of a memory device, which is described below with an example.

[0018] FIG. 2A to FIG. 2I It is a cross-sectional schematic diagram of an intermediate stage of a method for manufacturing a three-dimensional memory device according to an embodiment of the present invention.

[0019] Please refer to Figure 2A, providing a substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon-containing substrate. The substrate 100 may further include a device layer (not shown) located on the semiconductor substrate and a metal interconnect structure (not shown) located on the device layer. The device layer may include active devices or passive devices. Active devices are, for example, transistors, diodes, etc. Passive devices are, for example, capacitors, inductors, etc. The metal interconnect structure may include a dielectric layer (not shown), a plug 101, and a wire (not shown). The plug 101 may be electrically connected to a source line. The material of the plug 101 includes tungsten.

[0020] Please refer to Figure 2A , a stacking structure SK is formed above the substrate 100. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The stacking structure SK includes a plurality of first material layers 102 and a plurality of second material layers 104 that are alternately stacked. The first material layer 102 may be an insulating layer, such as silicon oxide. The second material layer 104 may be an insulating layer, such as silicon nitride. In the present embodiment, the bottom layer and the top layer of the stacking structure SK are both the first material layer 102, but the present invention is not limited thereto. In addition, in the present embodiment, 4 layers of the first material layer 102 and 3 layers of the second material layer 104 are used for illustration, however, the present invention is not limited thereto.

[0021] Next, please refer to Figure 2B , a patterning process is performed to remove part of the stacked structure SK in the memory matrix region to form one or more holes 106 passing through the stacked structure SK. In one embodiment, the hole 106 may have a substantially vertical sidewall. In another embodiment, the hole 106 may have a slightly inclined sidewall (not shown).

[0022] Please refer to Figure 2C , a channel layer 108 is formed on the sidewall of the hole 106. The channel layer 108 can be formed by the method of forming the channel layer 22 in the above embodiment. That is, the channel layer 108 can include a first portion 108a and a second portion 108b. The first portion 108a is connected to the plug 101, and the second portion 108b covers the first portion 108a. The first portion 108a is, for example, a polysilicon layer; the second portion 108b is, for example, an epitaxial silicon layer. The polysilicon layer and the epitaxial silicon layer can be formed by the method of forming the polysilicon layer 16b and the epitaxial silicon layer 20 described in the above embodiment, respectively. The channel layer 108 is, for example, a compliant layer that does not fill the hole 106.

[0023] Please refer to Figure 2D , a filling layer 110 is filled into the hole 106. The material of the filling layer 110 is, for example, silicon oxide.

[0024] FIG. 2E to FIG. 2IIt shows that the second material layer 104 is replaced by a conductive layer 124 a , and a charge storage structure 122 a is formed between the conductive layer 124 a and the first material layer 102 , which will be described in detail below.

[0025] Please refer to Figure 2E , photolithography and etching processes are performed to form trenches (slits) 112 in the stack structure SK. The trenches 112 expose the plurality of first material layers 102 and the plurality of second material layers 104 of the stack structure SK.

[0026] Please refer to Figure 2F , an etchant is injected / passed through the trench 112 to remove the multiple second material layers 104 of the stack structure SK, forming a plurality of horizontal openings 114 to expose the multiple first material layers 102 and the channel layer 108 of the stack structure SK.

[0027] Please refer to Figure 2F and Figure 2G A charge storage structure 122 is formed in the trench 112 and the horizontal opening 114. The charge storage structure 122 includes, for example, a silicon oxide layer 116, a silicon nitride layer 118, and a high-k dielectric layer 120. The high-k dielectric layer 120 refers to a dielectric layer having a dielectric constant greater than 4, such as Al 2 O 3 , HfO 2 、ZrO 2 、 2 O 5 、TiO 2 The silicon oxide layer 116 , the silicon nitride layer 118 and the high-k dielectric layer 120 are, for example, compliant layers, which can be formed by chemical vapor deposition or atomic layer deposition.

[0028] Please refer to Figure 2H , a conductive layer 124 is formed in the trench 112 and the horizontal opening 114 to cover the charge storage structure 122. The conductive layer 124 is, for example, tungsten, titanium or tantalum, and is formed by, for example, chemical vapor deposition.

[0029] Please refer to Fig.2I , the conductive layer 124 of the trench 112 and the high-k dielectric layer 120 of the charge storage structure 122 are removed, leaving the conductive layer 124a and the charge storage structure 122a in the horizontal opening 114. The charge storage structure 122a includes the silicon oxide layer 116, the silicon nitride layer 118 and the high-k dielectric layer 120a.

[0030] Thereafter, subsequent processes may be performed to complete the manufacture of the three-dimensional memory device.

[0031] FIG. 3A to FIG. 3DIt is a cross-sectional schematic diagram showing an intermediate stage of a method for manufacturing a three-dimensional memory device according to another embodiment of the present invention.

[0032] Please refer to Figure 3A , providing a substrate 200. The substrate 200 may be a semiconductor substrate, such as a silicon-containing substrate. In one embodiment, a doped region may be formed in the substrate 200 according to design requirements. A device layer (not shown) and a metal interconnect structure (not shown) may be formed on the substrate 200. The device layer may include active devices or passive devices. Active devices are, for example, transistors, diodes, etc. Passive devices are, for example, capacitors, inductors, etc. The metal interconnect structure may include a dielectric layer, a plug, and a wire, etc.

[0033] Please refer to Figure 3A , a stacking structure SK' is formed above the substrate 200. The stacking structure SK' includes a plurality of first material layers 202 and a plurality of second material layers 204 that are alternately stacked. The first material layer 202 may be an insulating layer, such as silicon oxide. The second material layer 204 may be a polysilicon layer. In the present embodiment, the bottom layer and the top layer of the stacking structure SK' are both the first material layer 202, but the present invention is not limited thereto. In addition, in the present embodiment, four layers of the first material layer 202 and three layers of the second material layer 204 are used for illustration, but the present invention is not limited thereto.

[0034] Next, please refer to Figure 3B , a patterning process is performed to remove a portion of the stacked structure SK' to form one or more holes 206 passing through the stacked structure SK'. In one embodiment, the hole 206 may have a substantially vertical sidewall. In another embodiment, the hole 206 may have a slightly inclined sidewall (not shown).

[0035] Please refer to Figure 3C , a charge storage structure 222 is formed on the sidewall of the hole 206. The charge storage structure 222 includes, for example, a silicon oxide layer 216, a silicon nitride layer 218, and a silicon oxide layer 220. The silicon oxide layers 216 and 220 and the silicon nitride layer 218 are, for example, compliant layers, which can be formed by thermal oxidation or chemical vapor deposition.

[0036] Please refer to Figure 3D , a channel layer 208 is formed on the sidewall of the charge storage structure 222 of the hole 206. The channel layer 208 can be formed by the method of forming the channel layer 22 in the above embodiment. That is, the channel layer 208 can include a first portion (for example, a polysilicon layer) 208a and a second portion (for example, an epitaxial silicon layer) 208b. The second portion 208b fills the hole 206, but is not limited thereto. The polysilicon layer and the epitaxial silicon layer can be formed by the method of forming the polysilicon layer 16b and the epitaxial silicon layer 20 described in the above embodiment, respectively, which will not be described in detail here.

[0037] Thereafter, subsequent processes may be performed to complete the manufacture of the three-dimensional memory device.

[0038] In multiple embodiments of the present invention, the channel layer includes a polysilicon layer and an epitaxial silicon layer. The low grain boundary density of the epitaxial silicon layer can reduce the variation of the read current. In addition, the polysilicon layer can be thinned to reduce the number of grain boundaries and grain boundary intersections, thereby further reducing the variation of the read current.

[0039] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A storage device, characterized in that ,include: substrate; A stacking structure, located on the substrate, comprising a plurality of insulating layers and a plurality of conductor layers stacked alternately, wherein the stacking structure has a hole; The channel layer is located in the hole and includes: Part I; and a second portion having a lower number of grain boundaries than the first portion; and A charge storage structure is located between the first portion and the plurality of conductor layers, and the charge storage structure and the second portion sandwich the first portion. The first portion includes a polysilicon layer, and the second portion includes an epitaxial silicon layer. 2 . The memory device according to claim 1 , wherein the charge storage structure is further located between the plurality of insulating layers and the plurality of conductive layers of the stacked structure. 3 . The memory device according to claim 2 , further comprising a filling layer filled in the hole and covering a sidewall of the second portion. The memory device according to claim 1 , wherein the second portion fills up the hole.

5. A method for manufacturing a memory device, characterized in that ,include: forming a stacked structure on a substrate, the stacked structure comprising a plurality of insulating layers and a plurality of conductive layers stacked alternately; forming a hole in the stacked structure; forming a charge storage structure on a sidewall of the stacked structure in the hole; as well as Forming a channel layer in the hole, comprising: forming a first portion of a sidewall of the charge storage structure in the hole; as well as A second portion is formed on the side wall of the first portion in the hole, the second portion having a lower grain boundary number than the first portion, The first portion includes a polysilicon layer, and the second portion includes an epitaxial silicon layer. 6 . The method for manufacturing a memory device according to claim 5 , further comprising removing a portion of the first portion to reduce a thickness of the first portion.

7. A method for manufacturing a memory device, characterized in that ,include: forming a stacking structure on a substrate, wherein the stacking structure comprises a plurality of first material layers and a plurality of second material layers stacked alternately; forming a hole in the stacked structure; forming a channel layer in the hole, comprising: A sidewall of the stacked structure in the hole forms a first portion; as well as forming a second portion on a sidewall of the first portion in the hole, the second portion having a lower grain boundary number than the first portion; forming a filling layer in the hole to cover a side wall of the second portion; replacing the plurality of second material layers with a plurality of conductor layers; as well as forming a charge storage structure between the plurality of conductor layers and the plurality of first material layers, The first portion includes a polysilicon layer, and the second portion includes an epitaxial silicon layer. 8 . The method for manufacturing a memory device according to claim 7 , further comprising removing a portion of the first portion to reduce a thickness of the first portion.

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