Chip structure and chip function control method

Abstract

The present invention discloses a chip structure and a chip function control method, wherein the chip structure includes a programmable register circuit, a latch circuit, a core circuit, and a multiplexer circuit. The programmable register circuit and the latch circuit are located in a first power domain. When the first power domain is activated, the latch circuit is driven to read a set value to generate a latch signal. The core circuit and the multiplexer circuit are located in a second power domain. The activation timing of the first power domain is earlier than the activation timing of the second power domain. When the second power domain is activated, the multiplexer circuit receives the latch signal and outputs a function signal to the core circuit from the output end. The present invention can improve the efficiency and convenience of chip development, enhance the flexibility of chip function design, reduce the power consumption of the battery power supply, and increase the service life of the chip.

Description

Technical Field

[0001] The present invention relates to a chip structure and a chip function control method, and more particularly to a chip structure and a chip function control method that drive a chip circuit with power domains having different startup timings and can start chip functions in advance. Background Art

[0002] Current chip designs use strapping pins to set chip functions. These pins are connected to pull-up or pull-down resistors to control the chip's switching between different functions, ultimately determining the chip's function. However, these designs require the use of chip pins, requiring pin specifications to be confirmed when setting chip functions, which places additional restrictions on chip pin usage.

[0003] If chip functions are not configured through pin connections, software control is often used to determine chip functions, placing the function configuration circuitry within the chip, thereby reducing the number of pins used. However, internal chip operations require the chip to be powered on before the relevant settings are executed. This can cause a delay in the startup of some functions, making them incapable of meeting the requirements of the relevant functions. Therefore, when it comes to chip function configuration, existing chip structures and function control methods still have significant shortcomings.

[0004] The inventors of the present invention have considered and designed a chip structure and a chip function control method in order to improve the problems of the prior art and thereby promote industrial implementation and utilization. Summary of the Invention

[0005] In view of the problems described in the prior art, an object of the present invention is to provide a chip structure and a chip function control method to avoid delays in chip function startup, thereby reducing chip operation efficiency.

[0006] Based on the above objectives, the present invention provides a chip structure comprising a programmable register circuit (One Time Programmer, OTP), a latch circuit, a core circuit, and a multiplexer circuit. The programmable register circuit is located in a first power domain and is used to store a set value for a set function. The latch circuit is coupled to the programmable register circuit and is located in the first power domain. When the first power domain is activated, the latch circuit reads the set value from the programmable register circuit and generates a latch signal. The core circuit is located in a second power domain, and the activation timing of the first power domain is earlier than the activation timing of the second power domain. The multiplexer circuit is coupled to the latch circuit and is located in the second power domain. When the second power domain is activated, the multiplexer circuit receives the latch signal and outputs a function signal of the set function to the core circuit from the output end of the multiplexer circuit.

[0007] Preferably, the chip structure may further include a power saving switching circuit coupled to the first voltage source and the second voltage source of the first power domain. The power supply of the first power domain is switched between the first voltage source and the second voltage source by the power saving switching circuit.

[0008] Preferably, the power saving switching circuit can be coupled to the trigger circuit and the second voltage source detection circuit. When the second voltage source detection circuit detects that the second voltage source is activated, the trigger circuit transmits a switching signal to the power saving switching circuit to control the power supply switching of the first power domain.

[0009] Preferably, the first power domain may include a battery power source, and the second power domain may include a system driving power source.

[0010] Preferably, the latch circuit can be coupled to a pulse circuit, which is coupled to the first power domain. The pulse circuit provides a pulse signal to control the latch circuit to access a set value.

[0011] Preferably, the multiplexer circuit may be coupled to a register circuit, the register circuit is coupled to the second power domain, and the register circuit provides a register signal to control the multiplexer circuit to output a functional signal.

[0012] The present invention provides a chip function control method, which is suitable for controlling the operating functions of a chip. The chip function control method includes: setting a first power domain, and setting a programmable register circuit and a latch circuit of the chip in the first power domain; setting a second power domain, and setting a multiplexer circuit and a core circuit of the chip in the second power domain, wherein the startup timing of the first power domain is earlier than the startup timing of the second power domain; when the first power domain is started, driving the latch circuit to read the set value of the programmable register circuit and generate a latch signal; when the second power domain is started, controlling the multiplexer circuit to receive the latch signal, and outputting a function signal to the core circuit from the output end of the multiplexer circuit.

[0013] Preferably, the chip function control method further includes providing a power saving switching circuit coupled to the first voltage source and the second voltage source. When the second voltage source is activated, the power saving switching circuit is used to switch the first voltage source of the first power domain to the second voltage source.

[0014] Preferably, the power-saving switching circuit can control the power supply switching of the first power domain via a switching signal transmitted by the trigger circuit.

[0015] Preferably, the first power domain may include a battery power source, and the second power domain may include a system driving power source.

[0016] As described above, the chip structure and chip function control method according to the present invention can have one or more of the following advantages:

[0017] (1) This chip structure and chip function control method can set the chip function through the internal circuit without connecting a pull-up resistor or a pull-down resistor, thereby reducing the number of chip pins used and improving the efficiency and convenience of chip development.

[0018] (2) This chip structure and chip function control method can enable the function setting circuit to operate earlier before the core unit of the chip is started through the design of different power domains, advance the timing of function setting, and improve the flexibility of chip function design.

[0019] (3) This chip structure and chip function control method can reduce the power consumption of the battery power supply and increase the service life of the chip by setting a power-saving switching circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] To make the technical features, contents, advantages and effects of the present invention more apparent, the present invention is described with reference to the following drawings:

[0021] Figure 1 Schematic diagram of a chip structure according to an embodiment of the present invention.

[0022] Figure 2 This is a timing diagram of chip function control according to an embodiment of the present invention.

[0023] Figure 3 FIG. 1 is a schematic diagram of a power-saving switching circuit according to an embodiment of the present invention.

[0024] Figure 4 Flowchart of a chip function control method according to an embodiment of the present invention.

[0025] Explanation of symbols:

[0026] 11: Programmable register circuit

[0027] 12: Latch circuit

[0028] 13: Core circuit

[0029] 14: Multiplexer circuit

[0030] 15: Pulse circuit

[0031] 16: Register circuit

[0032] 17: Select Circuit

[0033] 21: Power saving switching circuit

[0034] 22: First voltage source

[0035] 23: Second voltage source

[0036] 24: Trigger circuit

[0037] 25: Second voltage source detection circuit

[0038] 100: Chip structure

[0039] AT5: front-wheel drive power supply

[0040] FS: Functional signal

[0041] G: Control gate

[0042] I1: first input terminal

[0043] I2: second input terminal

[0044] LV: Latch signal

[0045] O: Output

[0046] P1: first power domain

[0047] P2: Second power domain

[0048] PS: Pulse signal

[0049] RST: switching signal

[0050] RV: Registered signal

[0051] SV: Set value

[0052] S1~S4: Steps

[0053] t1: first time point

[0054] t2: second time point

[0055] t3: third time point

[0056] VBAT: battery power

[0057] VSB: Standby mode voltage DETAILED DESCRIPTION

[0058] To facilitate understanding of the technical features, contents, advantages, and effects achievable by the present invention, the present invention is hereby described in detail below in the form of embodiments in conjunction with the accompanying drawings. The drawings used therein are intended only to illustrate and assist in the description, and may not reflect the actual proportions and precise configurations of the present invention after implementation. Therefore, the proportions and configurations of the attached drawings should not be interpreted to limit the scope of the claims of the present invention in actual implementation. This is hereby stated.

[0059] See also Figure 1 , Figure 1The schematic diagram of the chip structure of an embodiment of the present invention is shown. As shown, chip structure 100 includes a programmable register circuit 11, a latch circuit 12, a core circuit 13, a multiplexer circuit 14, a pulse circuit 15, a register circuit 16, and a selection circuit 17. The programmable register circuit 11 and the latch circuit 12 are located in the first power domain P1. The programmable register circuit 11 stores a set value SV for a function setting. Specifically, the set value SV of the chip function is stored in this register after programming. When this set value SV is read, the chip can perform the function corresponding to this set value SV. A latch circuit 12 is provided corresponding to the programmable register circuit 11. The latch circuit 12 is coupled to the programmable register circuit 11 and can lock the set value SV of the programmable register circuit 11 through the latch circuit 12. In this embodiment, the latch circuit 12 is coupled to the pulse circuit 15. When the first power domain P1 is activated, the pulse circuit 15 provides a pulse signal PS to the control gate G of the latch circuit 12. The pulse signal PS controls the latch circuit 12 to read the set value SV of the programmable register circuit 11.

[0060] In this embodiment, the core circuit 13 and the multiplexer circuit 14 are located in the second power domain P2. The output of the latch circuit 12 is coupled to the multiplexer circuit 14, and the output of the multiplexer circuit 14 is coupled to the core circuit 13. The multiplexer circuit 14 includes a first input terminal I1 and a second input terminal I2. The output of the latch circuit 12 is coupled to the first input terminal I1 of the multiplexer circuit 14. The set value SV of the programmable register circuit 11 is transmitted to the multiplexer circuit 14 via the latch circuit 12 via the latch signal LV. The second input terminal I2 of the multiplexer circuit 14 is coupled to the output of the register circuit 16. The register circuit 16 transmits a register signal RV to the multiplexer circuit 14. The signal values ​​of the latch signal LV and the register signal RV can correspond to different chip functions. When the second power domain P2 is activated, the multiplexer circuit 14 can select the high or low voltage signals provided by the selection circuit 17 to output the latch signal LV received at the first input terminal I1 or the register signal RV received at the second input terminal I2 from the output terminal O of the multiplexer circuit 14 to the core circuit 13. In other words, the corresponding chip function is enabled by outputting the function signal FS, and the core circuit 13 performs the set function operation.

[0061] The aforementioned programmable register circuit 11, latch circuit 12, core circuit 13, multiplexer circuit 14, pulse circuit 15, register circuit 16, etc., all require power to start up. If they are driven with the same power startup sequence, when the multiplexer circuit 14 starts up, it must wait for the power to drive the programmable register circuit 11 and latch circuit 12 before the multiplexer circuit 14 receives the latch signal LV and outputs the function signal FS to the core circuit 13 to enable the chip function, resulting in a delay in operation. If it is necessary to enable all chip operating functions simultaneously during startup, such as by setting a multi-function pin to one of multiple preset functions, this startup method will not achieve the expected startup time. To solve the above problem, the present invention divides the power supply into a first power domain P1 and a second power domain P2. The second power domain P2 provides voltage to start the core circuit 13 and the multiplexer circuit 14 of the chip structure 100. That is, the operation of the chip system is driven by the power supplied by the second power domain P2. The first power domain P1 is the power source that provides power before the second power domain P2 is started. The startup timing of the first power domain P1 is earlier than the startup timing of the second power domain P2.

[0062] As shown in the figure, the programmable register circuit 11 and latch circuit 12 in the chip structure 100 are located in the first power domain P1, while the core circuit 13 and multiplexer circuit 14 are located in the second power domain P2. Before the second power domain P2 is powered, the latch circuit 12, powered by the first power domain P1, reads the set value SV of the programmable register circuit 11. When the second power domain P2 supplies power to the multiplexer circuit 14, it immediately receives the latch signal LV from the latch circuit 12 and outputs the function signal FS to the core circuit 13 through the output terminal O, thereby immediately activating the set function. In this embodiment, the latch circuit 12 is coupled to a pulse circuit 15, which is also located in the first power domain P1. The first power domain P1 drives the pulse circuit 15 to provide a pulse signal PS to the control gate G of the latch circuit 12, thereby controlling the latch circuit 12 to read the set value SV of the programmable register circuit 11. On the other hand, the register circuit 16 coupled to the multiplexer circuit 14 is located in the second power domain P2. After the second power domain P2 is activated, the register circuit 16 can provide a register signal RV for different chip functions. After the multiplexer circuit 14 switches, the output function signal FS is changed, allowing the output terminal O to output the function signal FS to the core circuit 13, thereby executing different chip functions.

[0063] Please also see Figure 2 and Figure 3 , Figure 2 This is a timing diagram of chip function control according to an embodiment of the present invention. Figure 3 FIG. 1 is a schematic diagram of a power-saving switching circuit according to an embodiment of the present invention. Figure 2As shown, at a first time point t1, the chip's second power domain P2 is not activated, while the chip's first power domain P1 is powered by the battery power supply VBAT. The battery power supply VBAT can be a mercury battery, typically used as a real-time clock. At a second time point t2, the battery power supply VBAT's supply voltage is switched by the power-saving switching circuit 21, allowing the power originally supplied by the battery power supply VBAT to be converted to the pre-drive power supply AT5, which drives the programmable register circuit and latch circuit. The pre-drive power supply AT5 is the voltage source for the chip system. From the second time point t2 onward, the first power domain P1 is powered by the voltage provided by the pre-drive power supply AT5. The pulse circuit is driven to provide a pulse signal PS to control the latch circuit to read the programmable register circuit's settings. While the second power domain P2 is not yet activated, the latch circuit has already captured the settings corresponding to the chip's functions.

[0064] At the third time point t3, the chip system's power supply provides a standby mode voltage VSB, which serves as the power supply for the second power domain P2. This voltage begins powering the components within the chip, activating the core circuitry of the chip structure. The power supply is typically a large-capacity battery in an electronic device or a power supply for a landline phone. Both the pre-power supply AT5 and the standby mode voltage VSB are voltage sources provided by the chip system's power supply. The pre-power supply AT5 is activated earlier than the standby mode voltage VSB. In this embodiment, the multiplexer circuit is located in the second power domain P2. Because the latch circuit is activated by the first power domain P1 at a first time point t1, which precedes the third time point t3, the multiplexer circuit immediately receives the latch signal provided by the latch circuit when it is activated at the third time point t3. This allows the function signal for the output setting function to be outputted earlier, without waiting for the power supply timing delay. This allows the core units of the chip to execute the preset functions immediately upon system startup, resulting in more efficient chip system operation.

[0065] Meanwhile, at the third time point t3, the second power domain P2 also drives the register circuit to provide a register signal to the multiplexer circuit. This allows the multiplexer circuit to switch between different functional signal outputs via the selection circuit, thereby achieving the effect of switching chip functions. Compared to connecting pull-up and pull-down resistors to chip pins, which determine the chip function, this embodiment achieves function switching without occupying chip pins, thereby reducing the complexity of chip pin configuration.

[0066] In this embodiment, the first power domain P1 can be powered by the battery power VBAT to provide a power supply with an earlier startup sequence. However, the voltage and power that can be supplied by the mercury battery installed in the chip are limited and cannot be continuously used as the power source for the first power domain P1. In order to save the consumption of the battery power VBAT, the chip structure is configured with a power saving switching circuit 21 to switch the power source of the first power domain P1 through the switching signal RST. Figure 3 As shown, the power supply source of the first power domain P1 is coupled to the power-saving switching circuit 21. The power-saving switching circuit 21 can be a multiplexer circuit, and its first input end is coupled to the first voltage source 22. In this embodiment, the first voltage source 22 is the battery power VBAT provided by the mercury battery. The second input end of the multiplexer circuit is coupled to the second voltage source 23 of the system driving power supply. In this embodiment, the second voltage source 23 is the front-end power supply AT5 of the chip system.

[0067] Please also see Figure 2 At the second time point t2, the second voltage source detection circuit 25 detects that the precursor power supply AT5 of the system drive power supply is activated. At this time, the chip already has sufficient power supply sources, and there is no need to continuously consume the battery power supply VBAT. Therefore, the power saving switching circuit 21 switches the power supply source of the first power domain P1 from the first voltage source 22 to the second voltage source 23 through the switching signal RST transmitted by the trigger circuit 24. That is, the precursor power supply AT5 is used as the power supply source of the first power domain P1, reducing the power consumption of the battery power supply VBAT. In this embodiment, when the switching signal RST is at a low level, the battery power supply VBAT provides the power supply source for the first power domain P1. When the second voltage source 23 is detected, the switching signal RST turns to a high level, and the first power domain P1 switches the power supply source to the precursor power supply AT5 through the power saving switching circuit 21, saving the consumption of the battery power supply VBAT and achieving a power saving effect. However, the present invention is not limited to this. In other embodiments, the chip system may not be equipped with a front-drive power supply AT5. After the power-saving switching circuit 21 detects the standby mode voltage VSB of the system driving power supply, the power-saving switching circuit 21 can directly switch the power supply of the first power domain P1 from the battery power supply VBAT to the standby mode voltage VSB.

[0068] See also Figure 4 , Figure 4 Flowchart of the chip function control method according to an embodiment of the present invention. As shown in the figure, the chip function control method includes the following steps (S1-S4):

[0069] Step S1: Set up a first power domain, and set up the programmable register circuit and latch circuit of the chip in the first power domain. Figure 1The chip structure includes a programmable register circuit and a latch circuit, the latch circuit being coupled to the programmable register circuit. Both the programmable register circuit and the latch circuit are located in a first power domain and driven by the first power domain. In this embodiment, the first power domain can convert the battery power supply voltage to a predetermined drive voltage provided by the chip system via a power-saving switching circuit, with the front-end power supply serving as the power supply for the first power domain.

[0070] Step S2: Setting a second power domain, and placing the chip's multiplexer circuits and core circuits in the second power domain. The startup timing of the first power domain is earlier than the startup timing of the second power domain. Setting a second power domain different from the first power domain, and placing the multiplexer circuits and the chip's core circuits in the second power domain. The startup timing of the power supply from the first power domain is earlier than the startup timing of the power supply from the second power domain. The second power domain can be the power supply for the core circuits of the startup chip system, and only provides the power required by the chip's internal components when the chip system is turned on. Because the battery is installed in the device and continuously provides power, it can provide power even when the chip system is not turned on. Therefore, the startup timing of the first power domain can be earlier than the startup timing of the second power domain.

[0071] Step S3: When the first power domain is activated, the latch circuit is driven to read the setting value of the programmable register circuit and generate a latch signal. When the first power domain is activated, the latch circuit can read the setting value of the programmable register circuit and transmit the latch signal to execute the chip function corresponding to the setting value. However, as described in the previous embodiment, if the programmable register circuit and the latch circuit must wait until the second power domain powered by the chip system is activated, the difference in their operating timing will cause the chip function to take effect. In this embodiment, by activating the first power domain with an earlier timing to drive the pulse circuit to generate a pulse signal, the latch circuit is controlled to read the programmable register circuit. This can lock the setting value of the preset function before the chip system is activated, thereby improving operating efficiency.

[0072] Step S4: When the second power domain is activated, the multiplexer circuit is controlled to receive a latch signal, and the function signal is output from the output of the multiplexer circuit to the core circuit. Because the latch circuit has locked the set value of the chip function, when the second power domain activates the multiplexer circuit, it can immediately receive the latch signal and output the function signal from the output of the multiplexer circuit to the core circuit of the chip. In addition, the multiplexer circuit can be connected to a register circuit to receive a register signal. The selection circuit switches between the latch signal and the register signal, allowing the chip to switch between different set functions, achieving the effect of selecting or binding chip functions. This also reduces the need for external pull-up and pull-down resistors on chip pins to switch functions.

[0073] Following the above steps, when the second power domain is activated, the chip structure can save power consumption by configuring a power-saving switching circuit. The power-saving switching circuit is coupled to the first voltage source and the second voltage source of the first power domain. Because the first voltage source is a battery power source and has limited power, when the second voltage source detection circuit detects that the voltage of the second voltage source is activated, the power-saving switching circuit can transmit a switching signal via a trigger circuit to control the multiplexer to switch the power input terminal, replacing the first voltage source with the second voltage source as the power source for the first power domain, thereby reducing the power consumption of the battery power source and achieving a power saving effect.

[0074] The above description is for illustrative purposes only and is not intended to be limiting. Any equivalent modifications or variations that do not depart from the spirit and scope of the present invention should be included in the scope of the claims.

Claims

1. A chip structure, characterized in that: Include: A programmable register circuit, located in the first power domain, for storing a setting value of a setting function; a latch circuit coupled to the programmable register circuit and located in the first power domain, wherein when the first power domain is activated, the latch circuit reads the set value from the programmable register circuit and generates a latch signal; The core circuit is located in the second power domain, and the startup timing of the first power domain is earlier than the startup timing of the second power domain; as well as The multiplexer circuit is coupled to the latch circuit and is located in the second power domain. When the second power domain is activated, the multiplexer circuit receives the latch signal and the output end of the multiplexer circuit outputs the function signal of the set function to the core circuit.

2. The chip structure according to claim 1, wherein: The power saving switching circuit is coupled to a first voltage source and a second voltage source of the first power domain. The power supply of the first power domain is switched between the first voltage source and the second voltage source by the power saving switching circuit.

3. The chip structure according to claim 2, wherein: The power saving switching circuit is coupled to a trigger circuit and a second voltage source detection circuit. When the second voltage source detection circuit detects that the second voltage source is activated, the trigger circuit transmits a switching signal to the power saving switching circuit to control power supply switching of the first power domain.

4. The chip structure according to claim 2, wherein: The first power domain includes a battery power source, and the second power domain includes a system driving power source.

5. The chip structure according to claim 1, wherein: The latch circuit is coupled to a pulse circuit, which is coupled to the first power domain. The pulse circuit provides a pulse signal to control the latch circuit to access the setting value.

6. The chip structure according to claim 1, wherein: The multiplexer circuit is coupled to a register circuit. The register circuit is coupled to the second power domain. The register circuit provides a register signal to control the multiplexer circuit to output the functional signal.

7. A chip function control method, characterized in that: Applicable to controlling the operating functions of a chip, the chip function control method comprises the following steps: Setting a first power domain, and setting the programmable register circuit and latch circuit of the chip in the first power domain; Setting a second power domain, setting the multiplexer circuit and the core circuit of the chip in the second power domain, and starting the first power domain earlier than the second power domain; When the first power domain is activated, the latch circuit is driven to read the setting value of the programmable register circuit to generate a latch signal; as well as When the second power domain is activated, the multiplexer circuit is controlled to receive the latch signal, and a function signal is output to the core circuit through an output terminal of the multiplexer circuit.

8. The chip function control method according to claim 7, wherein: It also includes the following steps: A power-saving switching circuit is provided, coupled to the first voltage source and the second voltage source. When the second voltage source is activated, the power-saving switching circuit is used to switch the first voltage source of the first power domain to the second voltage source.

9. The chip function control method according to claim 8, wherein: The power-saving switching circuit controls the power supply switching of the first power domain via a switching signal transmitted by a trigger circuit.

10. The chip function control method according to claim 8, wherein: The first voltage source includes a battery power source, and the second voltage source includes a system driving power source.

Images