Method and device for synthesizing circuit description into DSP module in EDA

Abstract

The present invention discloses a method for synthesizing a circuit description into a DSP module in an EDA, comprising the following steps: collecting the $mul unit, $add unit, and $sub unit in the RTLIL-level units under the multiplication item, using the two inputs of the $mul unit as child nodes and the output as the parent node to construct a binary linked list; determining the DSP type based on the binary linked list and creating a temporary $dsp unit; mapping the $dsp unit into a DSP module and outputting a synthesized netlist file. The present invention also discloses a device using this method for synthesizing a circuit description into a DSP module in an EDA. By synthesizing multiplication, multiplication-addition, and accumulation operations using DSP modules, the present invention reduces the number of logic units and lowers chip utilization, making the synthesis module of the EDA tool more efficient and richer, and providing a better and more efficient design environment for FPGA chip design.

Description

Technical Field

[0001] The present invention relates to a method for synthesizing a circuit description into a DSP module in an EDA (Electronic Design Automation) tool. The method is mainly applied to a synthesis module in an EDA (Electronic Design Automation) tool to synthesize multiplication, multiply-add, and multiply-accumulate operations of a circuit description into a DSP (Digital Signal Processor) module, belonging to the technical field of EDA tool design. The method also relates to a device using the method for synthesizing a circuit description into a DSP module in an EDA tool. Background Art

[0002] In recent years, FPGAs (Field Programmable Gate Arrays) have seen increasing adoption in fields such as the internet, communications, image processing, automotive electronics, aerospace, and modern military equipment. The FPGA market is in huge demand, and EDA software is an essential tool for FPGA design. However, all well-known EDA tools in the industry must be imported. In extreme situations such as international tensions, trade wars, and sanctions, rights holders may prohibit the export and use of EDA tools. This would severely hinder circuit design and have a significant impact on the development of my country's FPGA and integrated circuit industries. Developing domestic EDA design software to replace imported software is a crucial and urgent long-term strategic necessity.

[0003] The DSP module is a key component of FPGA chips. It forms part of the FPGA chip to enable high-speed digital signal processing. It can perform basic operations such as multiply-add and multiply-accumulate. Simply put, the DSP module synthesizes the hardware description language (Verilog) into a module that adapts to the FPGA chip architecture. The synthesis module is a crucial component of EDA software; without it, subsequent processes cannot proceed.

[0004] Therefore, how to synthesize circuit description into DSP modules in EDA is an urgent problem that needs to be solved. Summary of the Invention

[0005] In view of the above-mentioned deficiencies in the prior art, the object of the present invention is to provide a method and apparatus for synthesizing circuit descriptions into DSP modules in EDA tools that has a small number of logic units, low chip utilization, and is richer and more efficient. This method and apparatus for synthesizing circuit descriptions into DSP modules in EDA tools can synthesize multiplication, multiply-add, and accumulate operations using DSP modules, providing a better and more efficient design environment for FPGA chip design.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions:

[0007] A method for synthesizing a circuit description into a DSP module in an EDA includes the following steps: collecting the $mul unit, $add unit, and $sub unit in the RTLIL-level units under the multiplication item, using the two inputs of the $mul unit as child nodes, and outputting the corresponding outputs as the parent node of the current-level binary linked list and the child node of the next-level binary linked list, thereby constructing a binary linked list; determining the DSP type based on the binary linked list and creating a temporary $dsp unit; mapping the $dsp unit to a set target DSP module, and outputting a synthesized netlist file. The method has the beneficial effect of reducing the number of logic units and chip utilization by synthesizing multiplication, multiplication-addition, and accumulation operations into DSP modules, making the synthesis module of the EDA tool more efficient and richer, and providing a better and more efficient design environment for FPGA chip design.

[0008] In the process of constructing the binary linked list, first select one of the $mul units as a node of the binary linked list, and traverse all the $add units, the $sub units and the $mul units to find all the RTLIL-level units related to the $mul unit, and return the root node of the binary linked list.

[0009] When there are N $mul units, select the first $mul unit, find its associated $add unit or $sub unit, and build a first-level binary linked list with the two inputs of the first $mul unit as child nodes and the output as the parent node; find the second $mul unit under the $add unit or $sub unit associated with the first $mul unit, with the two inputs of the second $mul unit as child nodes and the output as the parent node, and build a first-level binary linked list with the parent node of the first $mul unit and the parent node of the second $mul unit as child nodes , build a second-level binary linked list with the $add unit or the $sub unit as the parent node; search in sequence to the Nth $mul unit under the $sub unit item associated with the N-1th $mul unit, with the two inputs of the Nth $mul unit as child nodes and the output as the parent node, build an Nth-level binary linked list with the parent node of the N-1th $mul unit and the parent node of the Nth $mul unit as child nodes and the $sub unit as the parent node; the first-level binary linked list to the Nth-level binary linked list constitute a complete binary linked list, where N is a positive integer.

[0010] The method for obtaining the RTLIL-level unit is to parse the lexical structure and syntax in the Verilog file into AST and then convert the AST into the RTLIL-level unit.

[0011] The type of the $dsp unit is simple multiplication, 36-bit multiplication, multiply-accumulate, double multiply-accumulate, or quad multiply-accumulate.

[0012] In the simple multiplication type, the delay beat of the clock cycle of the DSP module is detected.

[0013] In the four-multiply-add type, the circuit includes four multiplication operations with asynchronous clear operations.

[0014] The DSP module is composed of two submodules, wherein one submodule is partially connected to the input signal, and its output signal is connected to the input port of the other submodule, and the output signal of the other submodule is connected to the output port.

[0015] In the process of creating the temporary $dsp unit, the corresponding $mul unit is deleted until all $mul units are created with a corresponding $dsp unit.

[0016] A device for synthesizing a circuit description into a DSP module in an EDA runs the method for synthesizing a circuit description into a DSP module in an EDA.

[0017] Compared with the prior art, the present invention has the following beneficial effects:

[0018] The present invention reduces the number of logic units and the chip utilization rate by integrating multiplication, multiplication-addition and accumulation operations with DSP modules, making the synthesis modules of EDA tools more efficient and richer, and providing a better and more efficient design environment for FPGA chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0020] Figure 1 1 is a flow chart of a method for synthesizing a circuit description into a DSP module in EDA of the present invention;

[0021] Figure 2 A schematic diagram of a multiplication-addition type binary chain in a method for synthesizing a circuit description into a DSP module in EDA of the present invention;

[0022] Figure 3 Schematic diagram of a four-multiply-add type binary chain representation in the method of synthesizing a circuit description into a DSP module in EDA of the present invention;

[0023] Figure 4The pseudo code of the stratix_mac_mult submodule in the DSP module in the preferred embodiment of the present invention;

[0024] Figure 5 The pseudo code of the stratix_mac_out submodule in the DSP module in the preferred embodiment of the present invention is as follows;

[0025] Figure 6 Pseudocode diagrams defining five mappings: simple multiplication, 36-bit multiplication, multiply-accumulate, double multiply-accumulate, and quadruple multiply-accumulate.

[0026] Figure 7 Schematic diagram of pseudo code of the mapped $dsp unit in a preferred embodiment of the present invention;

[0027] Figure 8 A Verilog file description diagram of a four-multiplication-addition circuit in a preferred embodiment of the present invention;

[0028] Figure 9 Schematic diagram of pseudo code of the port connection relationship after processing of the four multiplication and addition circuit in the preferred embodiment of the present invention;

[0029] Figure 10 A pseudo code diagram for defining eight network types for a quad-multiply-add circuit in a preferred embodiment of the present invention is shown;

[0030] Figure 11 This is a pseudo code diagram of a preferred embodiment of the present invention in which a line network signal is connected to a four-multiply-add circuit as an input signal. DETAILED DESCRIPTION

[0031] The following is a clear and complete description of the technical solutions in the specific embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of the present invention.

[0032] Example 1:

[0033] like Figure 1 As shown, this embodiment discloses a method for synthesizing a circuit description into a DSP module in EDA, comprising the following steps:

[0034] The $mul (multiplication) unit, $add (addition) unit, and $sub (accumulation) unit in the RTLIL (Register Transfer Level Intermediate Language) level unit under the multiplication item are collected, and the two inputs of the $mul unit are used as child nodes, and the outputs are used as the parent node of the binary linked list at this level and the child node of the binary linked list at the next level, thereby constructing a binary linked list; the type of DSP is obtained based on the binary linked list, and a temporary $dsp unit is created; the $dsp unit is mapped to the set target DSP module, and a synthesis netlist file is output. The optimized design of the present invention reduces the number of logic units and the chip utilization rate by synthesizing multiplication, multiplication-addition, and accumulation operations with DSP modules, making the synthesis module of the EDA tool more efficient and rich, and providing a better and more efficient design environment for FPGA chip design.

[0035] Specifically, the following steps are included:

[0036] S1, read in the Verilog file.

[0037] S2, parses the lexical and grammatical information in the Verilog file into an AST (Abstract Syntax Tree).

[0038] S3, converts AST into RTLIL-level units.

[0039] S4, determine whether the RTLIL-level unit contains the $mul unit, if so, enter S5, if not, process it as other type of unit and enter S10.

[0040] S5, select the first $mul unit, find its associated $add unit or $sub unit, and build the first-level binary linked list with the two inputs of the first $mul unit as child nodes and the output as the parent node; find the second $mul unit under the $add unit or $sub unit associated with the first $mul unit, with the two inputs of the second $mul unit as child nodes and the output as the parent node, and build the first-level binary linked list with the parent node of the first $mul unit and the parent node of the second $mul unit as child nodes and the output of the $add unit as the parent node. Or construct a second-level binary linked list with the $sub unit as the parent node; ...; find the Nth $mul unit under the $sub unit item associated with the N-1th $mul unit, with the two inputs of the Nth $mul unit as child nodes and the output as the parent node, and construct an Nth-level binary linked list with the parent node of the N-1th $mul unit and the parent node of the Nth $mul unit as child nodes and the $sub unit as the parent node; the first-level binary linked list to the Nth-level binary linked list constitute a complete binary linked list, where N is a non-zero natural number.

[0041] Reference Figure 2 As shown in the figure, when N is 2, a binary linked list of multiplication and addition type is formed.

[0042] Reference Figure 3 As shown in the figure, when N is 4, a binary linked list of four multiplication and addition type is formed.

[0043] S6, judging whether the type of DSP is a simple multiplication type or a non-simple multiplication type through a binary linked list.

[0044] The simple multiplication type is the type of DSP when N in step S5 is 1, that is, there is only one $mul unit.

[0045] The non-simple multiplication type is the DSP type when N in step S5 is not 1, that is, there is more than one $mul unit. When N is 2, two $mul units are added to form an $add unit, which is a multiply-add type. When N is greater than 2, N $mul units form a $sub unit, which is a multiply-accumulate type.

[0046] S7, create a temporary $dsp unit, delete the first $mul unit in the first-level binary linked list, and return to step S4, looping N times until all $mul units are deleted and N corresponding $dsp units are created.

[0047] When N is 1, after returning to step S4, since the $mul unit has been deleted, the judgment in step S4 is no, and other types of units are processed, and step S10 is entered to directly output the integrated netlist file.

[0048] When N is greater than 1, after returning to step S4, since the first-level $mul unit has been deleted, there are still N-1 levels of $mul units left, so the judgment in step S4 is yes, and then after going through steps S5, S6 and S7 in sequence, it returns to step S4 and repeats the cycle N times until all $mul units are deleted.

[0049] S8, mapping the $dsp unit to a corresponding temporary unit according to its operation mode (operation_mode) parameter.

[0050] Reference Figure 7 As shown, if the operation_mode parameter of the mapped $dsp unit is TWO_LEVEL_ADDER, the port is connected to DATA_A, DATA_B is connected to the input port signals a, b, c, d, e, f, g, and the RESULT port is connected to the output port signal product.

[0051] S9, mapping the temporary unit to the target DSP module defined by the chip device library.

[0052] During the determination process in step S6, an algorithm can be used to check the type of DSP represented by the binary linked list. In step S8, the mapping process for the $dsp unit includes, but is not limited to, creating five indexes: simple multiplication, 36-bit multiplication, multiply-accumulate, double multiply-accumulate, and quad multiply-accumulate. The target DSP module is then mapped and generated according to the mapping definitions in the indexes.

[0053] Reference Figure 4 and Figure 5 As shown in the figure, the DSP module consists of two submodules: stratix_mac_mult and stratix_mac_out. The connection relationship between the two submodules is: the stratix_mac_mult part receives the input signal, the output signal of stratix_mac_mult is connected to the stratix_mac_out input port, and the output signal of stratix_mac_out is connected to the output port.

[0054] Reference Figure 6 As shown, during the mapping process, five DSP types are defined: OUTPUT_ONLY (simple multiplication), 36_BIT_MULTIPLY (36-bit multiplication), ACCUMULATOR (multiplication-accumulation), ONE_LEVEL_ADDER (double multiplication-addition), and TWO_LEVEL_ADDER (quadruple multiplication-addition). During mapping, the first step is to loop through the DSP to determine whether it contains a $mul unit. A DSP must have at least one multiplication unit; if there is no $mul, there is no need to process it. Next, a $mul unit is selected as a node in a binary linked list, and all $add units, $sub units, and $mul units are traversed to find all RTLIL-level units related to the $mul unit, returning the root node of the binary linked list. The binary linked list is then algorithmically parsed to determine the type of DSP it represents. Finally, $dsp unit conversion is performed according to different rules based on the DSP type in the binary linked list. For the DSP type of simple multiplication, the clock cycle delay beat is detected. Different delay periods will affect the input signal delay and output signal delay in the stratix_mac_mult module, as well as the output signal delay in the stratix_mac_out module.

[0055] S10, output the integrated netlist file.

[0056] S11, end.

[0057] In the implementation process of the method, the specific pseudo code is as follows:

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[0070] Example 2:

[0071] Reference Figure 8 and Figure 9 As shown in FIG, this embodiment discloses a method for synthesizing a circuit description into a DSP module in EDA. The method is a four-multiplication-addition Verilog file description supported by the first embodiment. The circuit contains four multiplication operations and an asynchronous clear operation. After RTLIL-level unit processing (Yosys open source code processing), the following is generated. Figure 9 The 4 $mul units and 3 $add units shown (not all). Figure 9 By analyzing the port connection relationship of each unit in the , we can conclude that there is a relationship between these units, for example, the signal of the output port Y of $mul is exactly the input signal of the input port A or B of a certain $add unit. The relationship is as follows Figure 3 shown.

[0072] Reference Figure 10 As shown in the figure, 8 net types DATA_A0, DATA_A1, DATA_A2, DATA_A3, DATA_B0, DATA_B1, DATA_B2 and DATA_B3 are defined, and the same bit width of DATA_A and DATA_B signals are assigned to these 8 net signals. In the chip device library, the type of quad multiplication and addition instantiates 4 stratix_mac_mult and 1 stratix_mac_out. The input signals of the four multiplications are connected with these net signals, refer to Figure 11As shown in the figure, in one of the instantiated units, stratix_mac_mult, port dataa is connected to DATA_A0, and port datab is connected to DATA_B0. In the instantiated unit stratix_mac_out, the parameter operation_mode value is two_level_adder. The signal connected to port dataa is the dataout output port signal of the first stratix_mac_mult submodule. The signals connected to ports datab, datac, and datad in the remaining stratix_mac_out submodules are also the dataout output port signals of the other three stratix_mac_mult submodules. The output port dataout of the stratix_mac_out submodule is connected to the output port RESULT. As mentioned above, the stratix_mac_mult submodule is connected to the input port, and the stratix_mac_out submodule is connected to the output port.

[0073] Example 3:

[0074] This embodiment discloses a device for synthesizing a circuit description into a DSP module in an EDA. The method for synthesizing a circuit description into a DSP module in an EDA in the first or second embodiment is executed in the device.

[0075] The above describes in detail the method and apparatus provided by the present invention for synthesizing circuit descriptions into DSP modules in EDA tools. Specific examples are used herein to illustrate the method and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims.

Claims

1. A method for synthesizing a circuit description into a DSP module in EDA, characterized in that: The following steps are involved: Collect the $mul unit, $add unit, and $sub unit in the RTLIL-level unit under the multiplication item, use the two inputs of the $mul unit as child nodes, and output the corresponding parent nodes of the binary linked list at this level and the child nodes of the binary linked list at the next level to construct a binary linked list; The type of DSP is obtained according to the binary linked list, and a temporary $dsp unit is created; Map the $dsp unit to the set target DSP module and output the integrated netlist file; When there are N $mul units, select the first $mul unit, find its associated $add unit or $sub unit, and build a first-level binary linked list with the two inputs of the first $mul unit as child nodes and the output as the parent node; find the second $mul unit under the $add unit or $sub unit associated with the first $mul unit, with the two inputs of the second $mul unit as child nodes and the output as the parent node, and build a first-level binary linked list with the parent node of the first $mul unit and the parent node of the second $mul unit as child nodes , build a second-level binary linked list with the $add unit or the $sub unit as the parent node; search in sequence to the Nth $mul unit under the $sub unit item associated with the N-1th $mul unit, with the two inputs of the Nth $mul unit as child nodes and the output as the parent node, build an Nth-level binary linked list with the parent node of the N-1th $mul unit and the parent node of the Nth $mul unit as child nodes and the $sub unit as the parent node; the first-level binary linked list to the Nth-level binary linked list constitute a complete binary linked list, where N is a positive integer.

2. The method for synthesizing a circuit description into a DSP module in EDA according to claim 1, characterized in that: In the process of constructing the binary linked list, first select any $mul unit as a node of the binary linked list, and traverse the $add unit, the $sub unit and the $mul unit to find all the RTLIL-level units related to the $mul unit, and return the root node of the binary linked list.

3. The method for synthesizing a circuit description into a DSP module in an EDA according to claim 1, wherein: The method for obtaining the RTLIL-level unit is to parse the lexical structure and syntax in the Verilog file into AST and then convert the AST into the RTLIL-level unit.

4. The method for synthesizing a circuit description into a DSP module in an EDA according to claim 1, wherein: The type of the $dsp unit is simple multiplication, 36-bit multiplication, multiply-accumulate, double multiply-accumulate, or quad multiply-accumulate.

5. The method for synthesizing a circuit description into a DSP module in EDA according to claim 4, characterized in that: In the simple multiplication type, the delay beat of the clock cycle of the DSP module is detected.

6. The method for synthesizing a circuit description into a DSP module in EDA according to claim 4, characterized in that: In the four-multiply-add type, the circuit includes four multiplication operations with asynchronous clear operations.

7. The method for synthesizing a circuit description into a DSP module in EDA according to claim 1, wherein: The DSP module is composed of two submodules, wherein one submodule is partially connected to the input signal, and its output signal is connected to the input port of the other submodule, and the output signal of the other submodule is connected to the output port.

8. The method for synthesizing a circuit description into a DSP module in EDA according to claim 7, characterized in that: In the process of creating the temporary $dsp unit, the corresponding $mul unit is deleted until all $mul units are created with a corresponding $dsp unit.

9. A device for synthesizing a circuit description into a DSP module in an EDA, characterized in that: A method for synthesizing a circuit description into a DSP module in an EDA according to any one of claims 1 to 8.

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