Memory devices, methods of operating same, and memory systems including same

Abstract

The present application relates to a memory device, an operating method thereof, and a memory system including the same. A memory device includes a page buffer including a first latch and a second latch, a control circuit configured to perform an operation of reading data of a selected word line and storing the data in the first latch, then perform an operation of discharging the selected word line, then perform an operation of moving the data of the first latch to the second latch, and then perform an operation of outputting the data of the second latch to the outside, and control logic configured to control the control circuit such that, when a second cache read command or a third cache read command is input in a section in which a discharge for a first word line is performed in response to an input of a first cache read command for the first word line, an execution section of the discharge for the first word line and an execution section of the moving at least partially overlap each other.

Description

TECHNICAL FIELD

[0001] Embodiments of the disclosure relate to semiconductor design technology, and more particularly, to a memory device supporting a cache read operation, an operating method of the memory device, and a memory system including the memory device. BACKGROUND

[0002] A memory system is a storage device implemented using a semiconductor such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), or the like. Memory systems are classified into volatile memory devices and nonvolatile memory devices. A volatile memory device is a memory device in which data stored therein is lost when power is interrupted. Representative examples of the volatile memory device include static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and the like. A nonvolatile memory device is a memory device in which data stored therein is retained even when power is interrupted. Representative examples of the nonvolatile memory device include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), and the like. The flash memory is mainly classified into a NOR type memory and a NAND type memory.

[0003] Recently, a computer environment paradigm has shifted to ubiquitous computing, which enables access to a computer system anytime and anywhere. As a result, the use of portable electronic devices such as mobile phones, digital cameras, notebook computers, and the like has increased. Such portable electronic devices generally use or include a memory system, i.e., a data storage device, which uses or embeds at least one memory device. The data storage device can be used as a main storage device or an auxiliary storage device of the portable electronic device.

[0004] In a computing device, unlike a hard disk, a data storage device implemented as a nonvolatile semiconductor memory device has advantages in that it has excellent stability and durability because it does not have a mechanical driving part (e.g., a mechanical arm), and has a high data access speed and low power consumption. Examples of such a data storage device include a universal serial bus (USB) memory device, a memory card having various interfaces, and a solid state drive (SSD). SUMMARY

[0005] Various embodiments of the disclosure relate to a memory device capable of efficiently performing a cache read operation, an operating method of the memory device, and a memory system including the memory device.

[0006] The technical problem to be solved by the present disclosure is not limited to the above technical problem, and other technical problems not mentioned will be clearly understood by those skilled in the art to which the present disclosure belongs from the following description.

[0007] According to an embodiment of the present application, a memory device can include: a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines; a plurality of page buffers coupled to the plurality of bit lines, each page buffer including a first latch and a second latch; a control circuit configured to perform a storing operation of reading data of a page coupled to a word line selected from among the plurality of word lines and storing the read data in the first latch, a discharging operation of discharging the selected word line after the storing operation, a moving operation of moving data of the first latch to the second latch after the storing operation, and an output operation of outputting data of the second latch to the outside after the moving operation; and control logic configured to control the control circuit such that, when a second cache read command or a third cache read command is input in an interval in which the storing operation or the discharging operation for a first word line is performed in response to an input of a first cache read command for caching reading data of a page coupled to the first word line among the plurality of word lines, an execution interval of the discharging operation for the first word line and an execution interval of the moving operation at least partially overlap each other.

[0008] The second cache read command can be a command for caching reading data of a page coupled to a second word line among the plurality of word lines, and the third cache read command can be a command for ending a cache read operation for the first word line after the cache read operation for the first word line is performed.

[0009] When the second cache read command or the third cache read command is input in an interval in which the storing operation for the first word line is performed, the control logic can control the control circuit to start the moving operation together at a start time of the discharging operation for the first word line.

[0010] When the second cache read command or the third cache read command is input in an interval in which the discharging operation for the first word line is performed, the control logic can control the control circuit to start the moving operation at a time at which it is determined that the second cache read command or the third cache read command has been input.

[0011] When the second cache read command is input in an interval in which the storing operation or the discharging operation for the first word line is performed, the control logic can control the control circuit to start a preparation operation for preparing the storing operation for the second word line when the discharging operation and the moving operation for the first word line are completely performed, and can control the control circuit to perform the storing operation and the output operation for the second word line together when the preparation operation is completely performed.

[0012] The control logic can control the control circuit to perform the operation of selecting the second word line by decoding an address input together with the second cache read command and the operation of resetting the first latch as a preparation operation.

[0013] When the third cache read command is input in an interval in which the storing operation or the discharging operation for the first word line is performed, the control logic can control the control circuit to perform the output operation when the discharging operation for the first word line and the moving operation for the first word line are completely performed.

[0014] According to an embodiment of the present application, a memory system can include a memory device including a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of page buffers coupled to the plurality of bit lines, each page buffer including a first latch and a second latch, and a controller configured to generate a first cache read command for caching reading data of a page coupled to a first word line among the plurality of word lines, transmit the first cache read command to the memory device, generate a second cache read command or a third cache read command, and transmit the second cache read command or the third cache read command to the memory device. When the second cache read command or the third cache read command is input in an interval in which a first storing operation of reading data of the page coupled to the first word line and storing the read data in the first latch in response to the first cache read command is performed or a discharging operation of discharging the first word line after the first storing operation is performed, the memory device can perform the discharging operation and a moving operation of moving data of the first latch to the second latch in at least partially overlapping manner.

[0015] The controller can generate the second cache read command and transmit the second cache read command to the memory device so as to cache read data of a page coupled to a second word line among the plurality of word lines, and after the cache read operation for the first word line is performed, the controller can generate the third cache read command and can transmit the third cache read command to the memory device so as to end the cache read operation for the first word line.

[0016] When the second cache read command or the third cache read command is input in an interval in which the first storing operation is performed, the memory device can start the moving operation together at a start time of the discharging operation.

[0017] When the second cache read command or the third cache read command is input in an interval in which the discharging operation is performed, the memory device can start the moving operation when it is determined that the second cache read command or the third cache read command has been input.

[0018] When the second cache read command is input in an interval in which the first storing operation or the discharging operation is performed, the memory device can start a preparation operation of the second storing operation for preparing to read data of a page coupled to the second word line and store the read data in the second latch when the discharging operation and the moving operation are completely performed, and can perform the second storing operation and an output operation of outputting data of the second latch to the controller when the preparation operation is completely performed.

[0019] The memory device can perform an operation of selecting the second word line by decoding an address input together with the second cache read command and an operation of resetting the first latch as the preparation operation.

[0020] When the third cache read command is input in an interval in which the first storing operation or the discharging operation is performed, the memory device can perform the output operation when the discharging operation is completely performed.

[0021] According to an embodiment of the present application, an operation method of a memory device including a memory cell array including a plurality of memory cells coupled between a plurality of word lines and a plurality of bit lines and a plurality of page buffers coupled to the plurality of bit lines, each page buffer including a first latch and a second latch, the operation method can include a first storing operation of storing data of a page coupled to a first word line among the plurality of word lines in the first latch in response to an input of a first cache read command, a discharging operation of discharging the first word line after the first storing operation, a moving operation of moving data of the first latch to the second latch after the first storing operation, and a parallel execution operation of executing an execution interval of the discharging operation and an execution interval of the moving operation in a manner that the execution intervals partially overlap with each other when a second cache read command or a third cache read command is input in an interval in which the first storing operation or the discharging operation is performed.

[0022] The second cache read command can be a command for caching reading data of a page coupled to a second word line among the plurality of word lines, and the third cache read command can be a command for ending a cache read operation for the first word line after the cache read operation for the first word line is performed.

[0023] The parallel execution operation can include starting the moving operation together with a start time of the discharging operation when the second cache read command or the third cache read command is input in an interval in which the first storing operation is performed, and starting the moving operation when it is determined that the second cache read command or the third cache read command has been input when the second cache read command or the third cache read command is input in an interval in which the discharging operation is performed.

[0024] The operation method can further include storing data of a page coupled to the second word line in the first latch in response to input of the second cache read command, outputting data of the second latch to the outside after the moving operation, and starting a preparation operation for preparing a second storage operation when the second cache read command is input in the parallel execution operation, the preparation operation being started when the parallel execution operation is completely executed, and the second storage operation being executed together with the output operation when the preparation operation is completely executed.

[0025] The preparation operation can include an operation of selecting the second word line by decoding an address input together with the second cache read command and an operation of resetting the first latch.

[0026] The operation method can further include executing the output operation when a third cache read command is input in the parallel execution operation, the output operation being executed when the parallel execution operation is completely executed.

[0027] According to an embodiment of the present application, a memory system can include a memory device including a plurality of pages and a plurality of page buffers coupled to a plurality of bit lines, each page including a plurality of cells coupled to a word line among a plurality of word lines, each page buffer including a first latch and a second latch, and a controller configured to sequentially generate a first cache read command and a second cache read command. The memory device can be configured to read data of a first page among the plurality of pages in response to the first cache read command, store the data of the first page in the first latch, determine whether the second cache read command is received while reading the data of the first page and storing the data of the first page, and perform discharge of a first word line associated with the first page and movement of the data of the first page stored in the first latch to the second latch in parallel when it is determined that the second cache read command is received while reading the data of the first page and storing the data of the first page.

[0028] The memory device can be further configured to output the data of the first page in the second latch to the controller.

[0029] According to the present technology, in a memory device for supporting a cache read operation, an operation of discharging a word line and an operation of moving data of a sense latch to a cache latch, which are required to be performed between two consecutive cache read operations, can be performed in parallel.

[0030] Accordingly, time required for a cache read operation can be minimized. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1 FIG. 1 is a diagram illustrating an example of a memory system according to an embodiment of the present disclosure.

[0032] Figure 2 FIG. 1 is a diagram illustrating an example of a memory device according to an embodiment of the present disclosure.

[0033] Figure 3 FIG. 2 is a diagram illustrating an example of a cache read operation according to an embodiment of the present disclosure.

[0034] Figures 4 to 7 FIG. 3 is a diagram illustrating a cache read operation according to an embodiment of the present disclosure.

[0035] Figure 8 FIG. 4 is a flowchart illustrating a cache read operation according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Various examples of the present disclosure are described in detail below with reference to the attached drawing figures. However, aspects and features of the present application can be embodied in different ways to form other embodiments including variations of any of the disclosed embodiments. Therefore, the present application is not limited to the embodiments set forth herein. Rather, the described embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. Throughout the present disclosure, like reference numerals refer to like elements in the various drawings and examples. It should be noted that a reference to “an embodiment,” “another embodiment,” etc., does not mean the same embodiment unless specifically referred to as such. Different instances of an embodiment can not necessarily be the same.

[0037] It should be understood that although the terms “first,” “second,” “third,” etc. can be used in this disclosure to identify various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element that has the same or similar name as the distinguished element. Thus, a first element in one instance can be called a second or third element in another instance without indicating any change in the elements themselves.

[0038] The drawings are not necessarily to scale and, in some instances, proportions can have been exaggerated for clarity of illustration purposes. When an element is referred to as being connected or coupled to another element, it can be directly connected or coupled to the other element or connected or coupled to the other element via one or more intervening elements. In addition, it will be understood that when an element is referred to as being between two elements, it can be the only element between the two elements or one or more intervening elements can also be present.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the terms "one" and "another" are intended to mean one or more unless the context clearly indicates otherwise.

[0040] It will be further understood that the terms "comprises" and "comprising", when used in this specification, specify the presence of stated elements, but do not preclude the presence or addition of one or more other elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0041] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art in the field of the application, in view of the disclosure. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the specification and relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0042] In the following description, numerous specific details are set forth to provide a thorough understanding of the present application. The present application can be practiced without some or all of these specific details. In other instances, well known process structures and / or processes have not been described in detail in order not to unnecessarily obscure the present application.

[0043] It should also be noted that, as will be apparent from the following description, features and / or elements of one embodiment can be utilized with or incorporated into another embodiment unless otherwise clearly indicated herein.

[0044] Embodiments of the present disclosure are described in detail below with reference to the attached drawing figures, wherein the like reference numerals refer to like elements.

[0045] Figure 1 FIG. 1 is a diagram illustrating an example of a memory system according to an embodiment of the present disclosure.

[0046] Referring to Figure 1 , the data processing system can include a host 102 interfaced or operatively coupled with the memory system 110.

[0047] The host 102 can include any of portable electronic devices such as a mobile phone, an MP3 player, a laptop computer, etc., and electronic devices such as a desktop computer, a game machine, a television (TV), a projector, etc.

[0048] The host 102 also includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 102. The OS can provide interoperability between the host 102 and a user using the memory system 110 interfaced with the memory system 110. The OS can support functions and operations corresponding to a user request. By way of example, and not limitation, the OS can be classified into a general-purpose operating system and a mobile operating system according to mobility of the host 102. The general-purpose operating system can be classified into a personal operating system and an enterprise operating system according to system requirements or a user environment. The personal operating system including Windows and Chrome can be subject to a support service for general-purpose. However, the enterprise operating system can be specialized for securing and supporting high performance, which includes Windows server, Linux, Unix, etc. In addition, the mobile operating system can include Android, iOS, Windows mobile, etc. The mobile operating system can be subject to a support service or a function for mobility (e.g., a power saving function). The host 102 can include a plurality of operating systems. The host 102 can execute a plurality of operating systems interlocked with the memory system 110 corresponding to a user request. The host 102 can transmit a plurality of commands corresponding to a user request to the memory system 110, thereby performing operations corresponding to the commands within the memory system 110.

[0049] The storage device for the memory system 110 can be implemented with a volatile memory device such as a dynamic random access memory (DRAM) and a static RAM (SRAM) and / or a non-volatile memory device such as a read only memory (ROM), a mask ROM (MROM), a programmable ROM (PROM), an erasable programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a ferroelectric RAM (FRAM), a phase change RAM (PRAM), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM or ReRAM), and a flash memory.

[0050] The memory system 110 can include a controller 130 and a memory device 150. The memory device 150 can store data to be accessed by the host 102. The controller 130 can control an operation of storing data in the memory device 150.

[0051] The controller 130 and the memory device 150 can be integrated into a single semiconductor device, which can be included in any one of various types of memory systems as discussed in examples above.

[0052] By way of example and not limitation, the controller 130 and the memory device 150 can be implemented with an SSD. When the memory system 110 is used as an SSD, the operating speed of the host 102 connected to the memory system 110 can be improved more than the operating speed of the host 102 implemented with a hard disk. In addition, the controller 130 and the memory device 150 can be integrated into one semiconductor device to form a memory card such as a PC card (PCMCIA), a compact flash card (CF), a memory card such as a smart media card (e.g., SM, SMC), a memory stick, a multimedia card (e.g., MMC, RS-MMC, micro-SD), a secure digital (SD) card (e.g., SD, mini-SD, micro-SD, SDHC), a universal flash storage, and the like.

[0053] The memory system 110 can be configured as a component of, for example, a computer, an ultra-mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, a smartphone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a 3D (3D) TV, a smart TV, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0054] The memory device 150 can be a non-volatile memory device and can retain data stored therein even in the absence of power supply. The memory device 150 can store data provided by the host 102 through a write operation and provide data stored therein to the host 102 through a read operation.

[0055] In this specification, the memory device 150 is a NAND flash memory as an example. According to an embodiment, the memory device 150 can be implemented as a three-dimensional array structure.

[0056] The present disclosure can also be applied to a flash memory device in which a charge storage layer is composed of a conductive floating gate (FG), and a charge-trapping flash memory (CTF) in which a charge storage layer is composed of an insulating film.

[0057] Specifically, the memory device 150 can include a memory cell array 151 and a plurality of page buffers 153. The memory cell array 151 can include a plurality of memory cells (not shown) connected between a plurality of word lines (not shown) and a plurality of bit lines BL. The plurality of page buffers 153 can be connected to the memory cell array 151 through the plurality of bit lines BL. That is, each of the plurality of page buffers 153 can be connected to at least one bit line BL to temporarily store at least one bit of data to be read from / written to at least one memory cell.

[0058] The memory device 150 is configured to receive a command and an address from the controller 130 and access a region of the memory cell array 151 selected by the address. That is, the memory device 150 can perform an operation corresponding to the command on the region selected by the address. For example, the memory device 150 can perform a write operation (a program operation), a read operation, and an erase operation. During the program operation, the memory device 150 programs data in the region selected by the address. During the read operation, the memory device 150 reads data from the region selected by the address. During the erase operation, the memory device 150 erases data stored in the region selected by the address.

[0059] According to an embodiment, the read operation performed by the memory device 150 can be classified into a normal read operation and a cache read operation.

[0060] During the normal read operation, the memory device 150 can receive a normal read command and an address from the controller 130. The memory device 150 can read data stored in the region selected by the address and store the read data in one of the page buffers 153. Then, the read data stored in one of the page buffers 153 can be output in response to a data output command input from the controller 130.

[0061] During the cache read operation, the memory device 150 can receive a cache read command and an address from the controller 130. The address provided to the memory device 150 during the cache read operation can be an address corresponding to a plurality of word lines (a plurality of pages). Alternatively, the address provided to the memory device 150 during the cache read operation can be an address that is continuously changed according to a method set in response to each of a plurality of cache read commands received continuously. In response to the cache read command, the memory device 150 can continuously read data requested according to the cache read command and corresponding to a plurality of word lines (a plurality of pages) in page units.

[0062] The cache read operation can be an operation of reading data of one page among a plurality of pages included in the memory cell array 151, storing the read page data in the plurality of page buffers 153, reading data of another page of the memory cell array 151 while outputting the page data stored in the plurality of page buffers 153 to the controller 130, and storing the read another page data in the plurality of page buffers 153.

[0063] At this time, at least one page can be coupled to one of a plurality of word lines included in the memory cell array 151. For example, when each of a plurality of memory cells coupled to one word line is a single-level cell (SLC) capable of storing 1-bit data, one page can be coupled to one word line. Also, when each of a plurality of memory cells coupled to one word line is a multi-level cell (MLC) capable of storing 2-bit data, two pages can be coupled to one word line. Also, when each of a plurality of memory cells coupled to one word line is a triple-level cell (TLC) capable of storing 3-bit data, three pages can be coupled to one word line.

[0064] Since at least one page as described above can be coupled to one word line, according to an embodiment, the cache read operation can be an operation of reading data of a first page among a first page and a second page coupled to one word line selected from a plurality of word lines included in the memory cell array 151, storing the read first page data in the plurality of page buffers 153, reading the second page data while outputting the stored first page data to the controller 130, and storing the read second page data in the plurality of page buffers 153. For reference, in the following description, one page is coupled to one word line; however, this is only one embodiment, and according to the designer's choice, a plurality of pages can also be coupled to one word line.

[0065] In some embodiments, each of the plurality of page buffers 153 can include a first latch (first LAT) and a second latch (second LAT). In the drawings, it can be seen that only one page buffer among the plurality of page buffers 153 is illustrated, and thus only one first LAT and one second LAT are illustrated. However, this is only for convenience of description, and in fact, each of the plurality of page buffers 153 can be connected to at least one bit line BL, and the number of page buffers can vary depending on the number of bit lines. Also, in the drawings, two latches (first LAT and second LAT) are included in each of the plurality of page buffers 153; however, this is only for convenience of description, and a larger number of latches can also be included according to the designer's choice.

[0066] According to the implementation, the cache read operation can be the following: read page data stored in the first word line among the multiple word lines included in the memory cell array 151, store the read data in the first LAT included in each of the multiple page buffers 153, move the page data stored in the first LAT to the second LAT, and while outputting the data of the second LAT to the controller 130, read the page data stored in the second word line among the multiple word lines included in the memory cell array 151, and store the read data in the first LAT.

[0067] More specifically, the controller 130 can generate a first cache read command and transmit it to the memory device 150, generate a second cache read command or a third cache read command, and then transmit the second cache read command or the third cache read command to the memory device 150. That is, the controller 130 can sequentially generate the first cache read command and the second cache read command and transmit them to the memory device 150, or it can sequentially generate the first cache read command and the third cache read command and transmit them to the memory device 150. In this case, the first cache read command can be a command for reading data (hereinafter referred to as first word line data) of a page connected to a first word line among the multiple word lines included in the memory device 150. Furthermore, the second cache read command can be a command for reading data (hereinafter referred to as second word line data) of a page connected to a second word line among the multiple word lines included in the memory device 150. In other words, when the controller 130 sequentially generates a first cache read command and a second cache read command and transmits them to the memory device 150, the data of the first word line and the data of the second word line among the multiple word lines included in the memory device 150 can be continuously output through the cache read operation. Furthermore, the third cache read command can be a command used to complete the cache read operation on the first word line and then end the cache read operation. That is, when the controller 130 sequentially generates a first cache read command and a third cache read command and transmits them to the memory device 150, the data of the first word line among the multiple word lines included in the memory device 150 can be output through the cache read operation, and then the cache read operation can be ended.

[0068] In this implementation, a cache read operation can begin when the controller 130 generates a first cache read command and transmits it to the memory device 150. Furthermore, the relationship between the first cache read command and a second or third cache read command can imply two consecutive cache read commands. For example, cache read commands generated by the controller 130 for a first time, a second time, and a third time are consecutively transmitted to the memory device 150. In this case, from the perspective of a cache read command generated for the second time, a cache read command generated for the first time can be the first cache read command, and a cache read command generated for the second time can be the second cache read command. From the perspective of a cache read command generated for the third time, a cache read command generated for the second time can be the first cache read command, and a cache read command generated for the third time can be either the second or third cache read command. When the cache read command generated for the third time is the second cache read command, a cache read command generated for a fourth time can exist after the cache read command generated for the third time. On the other hand, when the cache read command generated for the third time is a third cache read command, the cache read operation can be terminated after the cache read command generated for the third time. After the cache read operation is completed, when the controller 130 generates a normal read command and sends the normal read command to the memory device 150, the memory device 150 can perform a normal read operation. Furthermore, after the cache read operation is completed, when the controller 130 generates a first cache read command and sends the first cache read command to the memory device 150, the memory device 150 can perform a cache read operation again.

[0069] Then, the memory device 150 can perform a "first store operation" that, in response to a first cache read command transmitted from the controller 130, reads page data of a first word line and stores the read page data in a first LAT included in each of the plurality of page buffers 153. Furthermore, the memory device 150 can perform a "discharge operation" to discharge the first word line after the "first store operation". Furthermore, the memory device 150 can perform a "move operation" to move page data from the first LAT to a second LAT after the "first store operation". Furthermore, the memory device 150 can perform an "output operation" to output page data from the second LAT to the controller 130 after the "move operation". Furthermore, when the controller 130 transmits a second cache read command after the first cache read command, after completing the "discharge operation" and the "move operation", the memory device 150 can perform a "second store operation" that, in response to the second cache read command transmitted from the controller 130, reads data of a second word line and stores the read data in a first LAT included in each of the plurality of page buffers 153. Furthermore, when the controller 130 transmits a third cache read command after the first cache read command, the memory device 150 can end the cache read operation after completing the "output operation". For reference, performing a "discharge operation" to discharge the first word line can mean initializing the potential level of the first word line and the bit lines connected to the first word line to a set level.

[0070] When the memory device 150 performs a cache read operation, if a "move operation" corresponding to a cache read command for a second time input is performed while the "output operation" corresponding to the cache read command for the first time input has not been fully executed, the data corresponding to the cache read command for the first time input and the data corresponding to the cache read command for the second time input may be mixed up. For example, while the second LAT of the page buffer 153 is outputting data corresponding to the cache read command for the first time input, when the data corresponding to the cache read command for the second time input moves from the first LAT to the second LAT, the data corresponding to the cache read command for the first time input and the data corresponding to the cache read command for the second time input may be mixed up in the second LAT.

[0071] Therefore, the memory device 150 can execute a "shift operation" corresponding to a cache read command input at a second time after confirming that an "output operation" corresponding to a cache read command input at a first time has been fully executed. In other words, the memory device 150 can confirm that an output operation corresponding to a cache read command input at a third time, which is input later than the cache read command input at the second time, has been fully executed. This is because the existence of a cache read command input at a third time indicates that the "output operation" of the cache read command input at the first time has been fully executed. Therefore, when a cache read command input at a third time exists, the memory device 150 can execute a "shift operation" corresponding to a cache read command input at a second time.

[0072] Specifically, when a second cache read command or a third cache read command is input from the controller 130 during the interval of performing a "first storage operation" or a "discharge operation", the memory device 150 can perform the "discharge operation" and the "move operation" in an at least partially overlapping manner.

[0073] More specifically, when a second cache read command or a third cache read command is input from the controller 130 during the execution of the "first storage operation", the memory device 150 can start the "move operation" at the same time as the start of the "discharge operation". That is, when a second cache read command or a third cache read command is input from the controller 130 during the execution of the "first storage operation", the memory device 150 can perform the "discharge operation" and the "move operation" in such a way that the execution intervals of the "discharge operation" and the "move operation" completely overlap with each other.

[0074] Furthermore, when a second cache read command or a third cache read command is input from the controller 130 during the "discharge operation" interval, the memory device 150 can begin a "move operation" upon confirming that the second cache read command or the third cache read command has been input from the controller 130. That is, when a second cache read command or a third cache read command is input from the controller 130 during the "discharge operation" interval, the memory device 150 can perform the "discharge operation" and the "move operation" in such a way that the execution intervals of the "discharge operation" and the "move operation" partially overlap.

[0075] Furthermore, when a second cache read command is input from the controller 130 during the execution of a "first storage operation" or a "discharge operation," the memory device 150 can begin a "preparation operation" to prepare for the "second storage operation" when the "discharge operation" and "move operation" are fully executed. Additionally, the memory device 150 can execute the "second storage operation" and the "output operation" simultaneously when the "preparation operation" is fully executed. That is, by starting the "second storage operation" and the "output operation" simultaneously when the "preparation operation" is fully executed, the memory device 150 can execute the "second storage operation" and the "output operation" in such a way that the execution intervals of the "second storage operation" and the "output operation" completely overlap. In this case, as a "preparation operation," the memory device 150 can perform operations such as decoding the address input from the controller 130 along with the second cache read command and selecting the second word line, as well as resetting the first LAT.

[0076] Furthermore, when a third cache read command is input from the controller 130 during the execution of a "first storage operation" or a "discharge operation", the memory device 150 can perform an "output operation" when the "discharge operation" and the "move operation" have been fully executed.

[0077] Figure 2 This illustrates an embodiment according to the present disclosure. Figure 1 A diagram showing an example of a memory device.

[0078] Figure 3 This is a diagram illustrating an example of a cache read operation according to an embodiment of the present disclosure.

[0079] Figures 4 to 7 This illustrates a cache read operation according to an embodiment of the present disclosure (e.g., Figure 3 The diagram shows the cache read operation described in the text.

[0080] First, refer to Figure 2 The memory device 150 may include a memory cell array 151, multiple page buffers 153, control circuitry 152, 154 and 155, and control logic 156.

[0081] The memory cell array 151 may include multiple memory cells (not shown) connected between multiple word lines WL and multiple bit lines BL. Furthermore, multiple page buffers 153 may be connected to the multiple bit lines BL. Additionally, control circuits 152, 154, and 155 may perform programming operations for transferring data to and storing data through the multiple page buffers 153 to the memory cell array 151, and for receiving data stored in the memory cell array 151 through the multiple page buffers 153 and transmitting it externally (e.g., to controller 130). Figure 1The output shows the read operation for the received data and the erase operation for erasing the data stored in the memory cell array 151. Furthermore, the control logic diagram 156 can be configured in the controller 130. Figure 1 The system controls control circuits 152, 154, and 155 and multiple page buffers 153 under the control of the controller.

[0082] More specifically, control circuits 152, 154, and 155 may include a line decoder 152, an input / output (I / O) buffer 154, and a voltage generator 155.

[0083] Voltage generator 155 can be connected to row decoder 152 and control logic 156. Voltage generator 155 can be configured to generate various voltages required for programming, reading, and erasing operations in response to voltage control signal VCON from control logic 156. The voltage generated by voltage generator 155 can be transmitted via row decoder 152 to word line WL connected to memory cell array 151.

[0084] According to one embodiment, voltage generator 155 can generate an internal power supply voltage by adjusting an external power supply voltage. The internal power supply voltage generated by voltage generator 155 can be used as the operating voltage of memory device 150. According to one embodiment, voltage generator 155 can generate multiple voltages by using either an external power supply voltage or an internal power supply voltage. For example, voltage generator 155 may include multiple pump capacitors that receive the internal power supply voltage, and multiple voltages can be generated by selectively activating the multiple pump capacitors in response to control by control logic 156.

[0085] Control logic 156 can be connected to row decoder 152, page buffer 153, I / O buffer 154, and voltage generator 155. Control logic 156 can output a voltage control signal VCON to generate the voltage required for the operation of memory device 150 in response to the command CMD input through I / O buffer 154. Control logic 156 can output a row address signal RADD and a column address signal CADD in response to the address signal ADD input through I / O buffer 154.

[0086] Furthermore, the row decoder 152 can be electrically connected to the memory cell array 151 via word line WL. The row decoder 152 can be configured to operate in response to control logic 156. The row decoder 152 can receive a row address signal RADD from the control logic 156. The row decoder 152 can be configured to decode the received row address signal RADD. The row decoder 152 can select any word line among the multiple word lines included in the memory cell array 151 in response to the decoded row address signal RADD. The row decoder 152 can transmit various operating voltages VOP (e.g., voltages for programming, reading, and erasing operations) generated by the voltage generator 155 to the multiple word lines included in the memory cell array 151.

[0087] Depending on the operating mode, the multiple page buffers 153 can operate as write drivers or sense amplifiers. During a programming operation, the multiple page buffers 153 can transmit a voltage corresponding to the data to be programmed to the bit line BL of the memory cell array 151. During a read operation, the multiple page buffers 153 can sense the data stored in the selected memory cell via the bit line BL and transmit the sensed data to the I / O buffer 154. During an erase operation, the multiple page buffers 153 can float the bit line BL of the memory cell array 151.

[0088] During programming operations, I / O buffer 154 can transfer data from external sources (e.g., to multiple page buffers 153) to multiple page buffers 153. Figure 1 The controller 130) inputs write data. During a read operation, the I / O buffer 154 can output data provided from multiple page buffers 153 to the outside. The I / O buffer 154 can transmit externally input addresses (ADD) or commands (CMD) to the control logic 156.

[0089] Refer to together Figures 1 to 3 Each of the plurality of page buffers 153 in the memory device 150 may include a first LAT to a second LAT.

[0090] The control circuits 152, 154, and 155 included in the memory device 150 can perform a storage operation S1 or S5 to read data from a word line WL1 or WL2 selected from a plurality of word lines WL included in the memory cell array 151 and store the read data in a first LAT included in each of a plurality of page buffers 153. Furthermore, after the storage operation S1 or S5, the control circuits 152, 154, and 155 can perform a discharge operation S2 to discharge the selected word line WL1 or WL2. Furthermore, after the storage operation S1 or S5, the control circuits 152, 154, and 155 can perform a move operation S3 to move data from the first LAT to a second LAT. Furthermore, after the move operation S3, the control circuits 152, 154, and 155 can perform an output operation S4 to output data from the second LAT to an external source (e.g., the controller 130).

[0091] Reference Figures 1 to 7 The control logic 156 included in the memory device 150 can control the control circuits 152, 154, and 155 to perform the following first storage operation S1: in response to an external input of a first cache read command L1 for reading data DATA1 from the first word line WL1 of the plurality of word lines WL included in the cache memory cell array 151, the control logic 156 reads the data DATA1 stored in the first word line WL1 and stores the read data DATA1 in a first LAT included in each of the plurality of page buffers 153. Furthermore, the control logic 156 can control the control circuits 152, 154, and 155 to perform a discharge operation S2 that discharges the first word line WL1 after the first storage operation S1. Additionally, the control logic 156 can control the control circuits 152, 154, and 155 to perform a move operation S3 that moves the data DATA1 stored in the first word line WL1 in the first LAT to a second LAT after the first storage operation S1. Furthermore, control logic 156 can control control circuits 152, 154, and 155 to perform the following second storage operation S5: in response to a second cache read command L2 for reading data DATA2 from the second word line WL2 of the plurality of word lines WL included in the cache memory cell array 151 (see... Figure 4The system reads data DATA2 from the second word line WL2 from the external input and stores the read data DATA2 in the first LAT. In this case, control logic 156 can control control circuits 152, 154, and 155 to perform output operation S4 and second storage operation S5 in an overlapping manner after discharge operation S2 or move operation S3 has been fully executed. Furthermore, control logic 156 can control control circuits 152, 154, and 155 to perform only output operation S4 in response to the third cache read command L4 (see...). Figure 5 The cache read operation ends upon receiving external input.

[0092] When a second cache read command L2 or a third cache read command L4 is input during the interval of executing a first storage operation S1 for the first word line WL1 in response to an external input of a first cache read command L1, or during the interval of executing a discharge operation S2 for the first word line WL1, control logic 156 can control control circuits 152, 154, and 155 to execute the execution interval of the discharge operation S2 for the first word line WL1 and the execution interval of the movement operation S3 for the first word line WL1 in such a manner that the execution intervals at least partially overlap with each other.

[0093] More specifically, refer to Figure 4 and Figure 5 When a second cache read command L2 or a third cache read command L4 is input during the interval of the first storage operation S1 for the first word line WL1 in response to an external input of the first cache read command L1, the control logic 156 can control the control circuits 152, 154 and 155 to start the movement operation S3 for the first word line WL1 together at the start time of the discharge operation S2 for the first word line WL1.

[0094] like Figure 4As shown, when a second cache read command L2 is input during the interval of a first storage operation S1 for the first word line WL1 executed in response to an external input of a first cache read command L1, for example, when the second cache read command L2 is input at time t1 included in the interval of executing the first storage operation S1, the movement operation S3 for the first word line WL1 can begin at time t2, which is the start time of the discharge operation (DISCH) S2 for the first word line WL1. Therefore, the execution interval of the discharge operation S2 for the first word line WL1 and the execution interval of the movement operation (S2C) S3 for the first word line WL1 can completely overlap with each other. According to the embodiment, as shown in the figure, when the execution interval of the movement operation S3 is shorter than the execution interval of the discharge operation S2, the execution interval of the movement operation S3 can be hidden by the execution interval of the discharge operation S2 and may be invisible. Of course, unlike the attached figure, when the execution range of the movement operation S3 is longer than the execution range of the discharge operation S2, the execution range of the discharge operation S2 can be hidden by the execution range of the movement operation S3 and may be invisible.

[0095] In this manner, in response to the input of the second cache read command L2, control logic 156 can control control circuits 152, 154, and 155 to execute the execution intervals of the discharge operation S2 and the movement operation S3 for the first word line WL1 in a manner that the execution intervals completely overlap. At this time, since the second cache read command L2 has been input at time t1, control logic 156 can control control circuits 152, 154, and 155 to execute the preparation operation L3 for the second storage operation S5 for the second word line WL2 after the discharge operation S2 and movement operation S3 for the first word line WL1 have been fully executed. That is, control logic 156 can control control circuits 152, 154, and 155 to execute the preparation operation L3 from time t3, when the discharge operation S2 and movement operation S3 for the first word line WL1 have been fully executed, to time t4. Preparation operation L3 may include selecting the second word line WL2 by decoding the address input along with the second cache read command L2, and resetting the first LAT.

[0096] Control logic 156 can control control circuits 152, 154, and 155 to start the second storage operation S5 for the second word line WL2 and the output operation S4 for the first word line WL1 together at time t4 when preparation operation L3 has been fully executed. That is, the second storage operation S5 for the second word line WL2 and the output operation S4 for the first word line WL1 can be executed in a completely overlapping manner.

[0097] like Figure 5As shown, when a third cache read command L4 is input during the interval of the first storage operation S1 for the first word line WL1 executed in response to an external input of the first cache read command L1, for example, when the third cache read command L4 is input at time t5, which is included in the interval of the first storage operation S1, the movement operation S3 for the first word line WL1 can start at time t6, which is the start time of the discharge operation S2 for the first word line WL1. Therefore, the execution interval of the discharge operation S2 for the first word line WL1 and the execution interval of the movement operation S3 for the first word line WL1 can completely overlap with each other.

[0098] In this manner, in response to the input of the third cache read command L4, control logic 156 can control control circuits 152, 154, and 155 to execute the execution intervals of the discharge operation S2 and the movement operation S3 for the first word line WL1 in a manner that the execution intervals completely overlap. At this time, since the third cache read command L4 has been input at time t5, control logic 156 can control control circuits 152, 154, and 155 to execute the output operation S4 for the first word line WL1 after the discharge operation S2 and the movement operation S3 for the first word line WL1 have been fully executed. That is, control logic 156 can control control circuits 152, 154, and 155 to start the output operation S4 for the first word line WL1 from time t7 when the discharge operation S2 and the movement operation S3 for the first word line WL1 have been fully executed. For reference, it can be seen that... Figure 4 The difference lies in Figure 5 The preparation operation L3 is not executed. This is because the third cache read command L4 is used to end the cache read operation, and there is no need to prepare for the next cache read operation.

[0099] More specifically, refer to Figure 6 and Figure 7 After the interval of the first storage operation S1 for the first word line WL1 is completed in response to the external input of the first cache read command L1, when the second cache read command L2 or the third cache read command L4 is input in the interval of the discharge operation S2 for the first word line WL1, the control logic 156 can control the control circuits 152, 154 and 155 to start the movement operation S3 for the first word line WL1 when it is confirmed that the second cache read command L2 or the third cache read command L4 has been input.

[0100] like Figure 6As shown, after the interval for executing the first storage operation S1 for the first word line WL1 in response to the external input of the first cache read command L1 is completed, when the second cache read command L2 is input during the interval for executing the discharge operation S2 for the first word line WL1, for example, when the second cache read command L2 is input at time t9 included in the interval for executing the discharge operation S2 after time t8 when the first storage operation S1 has been fully executed, the movement operation S3 for the first word line WL1 can begin at time t9 when it is confirmed that the second cache read command L2 has been input. Therefore, the execution interval of the discharge operation S2 for the first word line WL1 and the execution interval of the movement operation S3 for the first word line WL1 can partially overlap with each other.

[0101] In this manner, in response to the input of the second cache read command L2, control logic 156 can control control circuits 152, 154, and 155 to execute the execution intervals of the discharge operation S2 and the movement operation S3 for the first word line WL1 in a manner that the execution intervals partially overlap. At this time, since the second cache read command L2 has been input at time t9, control logic 156 can control control circuits 152, 154, and 155 to execute the preparation operation L3 for the second storage operation S5 for the second word line WL2 after the discharge operation S2 and the movement operation S3 for the first word line WL1 have been fully executed. That is, control logic 156 can control control circuits 152, 154, and 155 to execute the preparation operation L3 from time t10, when the discharge operation S2 and the movement operation S3 for the first word line WL1 have been fully executed, to time t11. Preparation operation L3 may include selecting the second word line WL2 by decoding the address input along with the second cache read command L2, and resetting the first LAT. Control logic 156 may control control circuits 152, 154, and 155 to start the second storage operation S5 for the second word line WL2 and the output operation S4 for the first word line WL1 together at time t11 after preparation operation L3 has been fully executed. That is, the second storage operation S5 for the second word line WL2 and the output operation S4 for the first word line WL1 may be executed in a fully overlapping manner.

[0102] like Figure 7As shown, after the interval for executing the first storage operation S1 for the first word line WL1 in response to the external input of the first cache read command L1 is completed, when the third cache read command L4 is input during the interval for executing the discharge operation S2 for the first word line WL1, for example, when the third cache read command L4 is input at time t13 included in the interval for executing the discharge operation S2 after the first storage operation S1 has been fully executed, the movement operation S3 for the first word line WL1 can begin at time t13 when it is confirmed that the third cache read command L4 has been input. Therefore, the execution interval of the discharge operation S2 for the first word line WL1 and the execution interval of the movement operation S3 for the first word line WL1 can partially overlap with each other.

[0103] In this manner, in response to the input of the third cache read command L4, control logic 156 can control control circuits 152, 154, and 155 to execute the execution intervals of the discharge operation S2 and the movement operation S3 for the first word line WL1 in a manner that the execution intervals partially overlap. At this time, since the third cache read command L4 has been input at time t13, control logic 156 can control control circuits 152, 154, and 155 to execute the output operation S4 for the first word line WL1 after the discharge operation S2 and the movement operation S3 for the first word line WL1 have been fully executed. That is, control logic 156 can control control circuits 152, 154, and 155 to begin the output operation S4 for the first word line WL1 at time t14 when the discharge operation S2 and the movement operation S3 for the first word line WL1 have been fully executed. For reference, it can be seen that... Figure 6 The difference lies in Figure 7 The preparation operation L3 is not executed. This is because the third cache read command L4 is used to end the cache read operation, and there is no need to prepare for the next cache read operation.

[0104] Figure 8 This is a flowchart illustrating a cache read operation according to an embodiment of the present disclosure.

[0105] Figure 8 The sequence of performing cache read operations in memory device 150 according to an embodiment of the present disclosure is illustrated.

[0106] Specifically, when from outside the memory device 150 (e.g., controller 130 (see...) Figure 1When a read command is input, the memory device 150 can determine whether the input read command is a first cache read command (D1). In other words, the memory device 150 can determine whether the read command input from the outside is a normal read command or a first cache read command.

[0107] When the determination result in operation D1 indicates that the read command input from the outside is a normal read command (D1 is "No"), the memory device 150 can read data from the memory cell of the selected word line corresponding to the normal address input together with the normal read command among the multiple word lines included therein, and store the read data in the first LAT (D13) of the page buffer 153.

[0108] After the data of the selected word line is stored in the first LAT of the page buffer 153 via operation D13, the memory device 150 may together perform a discharge operation (DISCH) to discharge the selected word line and a move operation (S2C) (D14) to move the data of the first LAT of the page buffer 153 to the second LAT.

[0109] The memory device 150 can output (DOUT) the data (D15) stored in the second LAT of the page buffer 153 to the outside via operation D14.

[0110] Since operations D13 to D15 are normal read operations, there will be no problem even if the discharge and move operations are performed together in operation D14. That is to say, in the case of normal read operations, since there may be no read operations to be performed before and after the normal read operation, unlike cache read operations, there are no separate restrictions on the conditions for performing the move operation to move the data stored in the first LAT included in page buffer 153 to the second LAT.

[0111] When the determination result in operation D1 indicates that the read command input from the outside is a first cache read command (D1 is "yes"), the memory device 150 can perform a first storage operation (D2) to read (READ) data from the first word line of the multiple word lines included therein, corresponding to the cache address input together with the first cache read command, and store the read data in the first LAT of the page buffer 153.

[0112] The memory device 150 can determine whether a second cache read command or a third cache read command (D3) was entered during operation D2.

[0113] When the result of operation D3 indicates that a second cache read command or a third cache read command was input during operation D2 (D3 is "Yes"), the memory device 150 can simultaneously perform a discharge operation (DISCH) for the first word line and a move operation (S2C) (D4) to move data stored in the first LAT of page buffer 153 to the second LAT. Since the execution time of operation D3 is before the start of the discharge operation for the first word line, the memory device 150 can begin the move operation to move data stored in the first LAT of page buffer 153 to the second LAT at the start of the discharge operation for the first word line. In other words, when a second cache read command or a third cache read command is input during operation D2, the memory device 150 can control the execution intervals of the discharge operation for the first word line and the move operation to move data stored in the first LAT of page buffer 153 to the second LAT to completely overlap.

[0114] When the determination result in operation D3 indicates that no second cache read command or third cache read command was entered during operation D2 (D3 is "No"), memory device 150 can discharge the first word line (DISCH) (D5).

[0115] The memory device 150 can determine whether a second cache read command or a third cache read command (D7) was entered during operation D5.

[0116] When the result of operation D7 indicates that a second cache read command or a third cache read command was input during operation D5 (D7 is "Yes"), the memory device 150 can simultaneously perform a discharge operation for the first word line and a move operation (D4) to move data stored in the first LAT of page buffer 153 to the second LAT. Since the execution time of operation D5 is after the start of the discharge operation for the first word line, the memory device 150 can begin the move operation to move data stored in the first LAT of page buffer 153 to the second LAT when it is determined that a second cache read command or a third cache read command has been input. In other words, when a second cache read command or a third cache read command is input during operation D5, the memory device 150 can control the execution intervals of the discharge operation for the first word line and the move operation to move data stored in the first LAT of page buffer 153 to the second LAT to partially overlap.

[0117] The determination result in operation D7 indicates that no second cache read command or third cache read command was input during operation D5 (D7 is "No"). This can mean that the second cache read command or third cache read command will be input after operation D5 is fully executed and the discharge operation for the first word line is fully executed (D8). In this case, there can be a difference between the time when operation D5 is fully executed and the time when the second cache read command or third cache read command is input. That is, the memory device 150 can wait for the input of the second cache read command or third cache read command after operation D5 is fully executed.

[0118] When a second cache read command or a third cache read command is entered during operation D8, the memory device 150 can perform a move operation (S2C) (D9) to move data stored in the first LAT of the page buffer 153 to the second LAT.

[0119] After performing operation D9, memory device 150 can determine which cache read command (D6) was entered during operation D8. That is, memory device 150 can determine whether a second cache read command or a third cache read command was entered during operation D8.

[0120] When the result of operation D6 indicates that a third cache read command has been input (D6 is "No"), the memory device 150 can perform an output operation (DOUT) (D10) to output the data stored in the second LAT of page buffer 153 to the outside. This is because the third cache read command is a command used to end the cache read operation, and after performing the output operation (D10) to output the data of the first word line stored in the second LAT of page buffer 153 to the outside, there is no need to prepare for a continuous cache read operation. Of course, when a read command is input during operation D10, the memory device 150 can perform operation D1 for the read command.

[0121] When the determination result in operation D6 indicates that a second cache read command has been input (D6 is "Yes"), memory device 150 may perform a preparation operation (CACHE READ READY) (D11) to prepare for reading from the second word line corresponding to the cache address input along with the second cache read command. The preparation operation may include selecting the second word line by decoding the cache address input along with the second cache read command, and resetting the first LAT included in page buffer 153.

[0122] After fully executing operation D11, memory device 150 can perform a second storage operation (D12) to read data from a memory cell on a second word line (corresponding to the cache address entered along with the second cache read command) connected to one of the multiple word lines therein, and to store the read data in the first LAT of page buffer 153; and an output operation (DOUT) to output the data from the second LAT of page buffer 153 to the outside. In other words, after fully executing operation D11, memory device 150 can control the execution intervals of the second storage operation (reading data from the second word line and storing the read data in the first LAT of page buffer 153) and the execution interval (outputting the data from the second LAT of page buffer 153 to the outside) to completely overlap.

[0123] The memory device 150 can determine whether a second cache read command or a third cache read command (D3) was entered during operation D12. That is, since operation D12 includes a second store operation that reads data from the second word line and stores the read data in the first LAT of the page buffer 153, the memory device 150 can determine during operation D3 whether a second cache read command or a third cache read command was entered while performing the read of data from the second word line.

[0124] If the determination result in operation D3 indicates that a second cache read command was entered during operation D12 (D3 is "yes"), then the word line corresponding to the cache address entered along with the second cache read command can be a different word line than the second word line, for example, a third word line.

[0125] In the above description, a word line connects to a page, thus two different word lines are selected in response to two consecutive cache read commands. If a word line connects to two or more pages, two different pages connected to a single word line can also be selected in response to two consecutive cache read commands.

[0126] The present disclosure is not limited to the above-described embodiments and drawings, and it will be apparent to those skilled in the art that various substitutions, modifications, and alterations can be made without departing from the spirit of the present disclosure and the appended claims. Furthermore, embodiments can be combined to form additional embodiments.

[0127] Cross-references to related applications

[0128] This application claims priority to Korean Patent Application No. 10-2021-0053229, filed on April 23, 2021, the entire contents of which are incorporated herein by reference.

Claims

1. A memory device comprising: A memory cell array comprising multiple memory cells connected between multiple word lines and multiple bit lines; Multiple page buffers are connected to the multiple bit lines, and each page buffer includes a first latch and a second latch; The control circuit performs a storage operation that reads data from a page connected to a word line selected from the plurality of word lines and stores the read data in a first latch, a discharge operation that discharges the selected word line after the storage operation, a move operation that moves the data from the first latch to a second latch after the storage operation, and an output operation that outputs the data from the second latch to an external location after the move operation. as well as Control logic that controls the control circuit such that when a second cache read command or a third cache read command is input during a period in which a storage operation or a discharge operation is performed for the first word line in response to the input of a first cache read command for cache reading data of a page connected to the first word line of the plurality of word lines, the execution period of the discharge operation for the first word line and the execution period of the move operation for the first word line at least partially overlap with each other.

2. The memory device according to claim 1, wherein, The second cache read command is a command used to read data from a page connected to the second word line among the plurality of word lines, and The third cache read command is used to terminate the cache read operation for the first word line after the cache read operation for the first word line has been executed.

3. The memory device according to claim 2, wherein, When the second cache read command or the third cache read command is input during the interval of the storage operation for the first word line, the control logic controls the control circuit to start the movement operation together with the start time of the discharge operation for the first word line.

4. The memory device according to claim 3, wherein, When the second cache read command or the third cache read command is input during the interval in which the discharge operation for the first word line is performed, the control logic controls the control circuit to start the movement operation at the time when it is determined that the second cache read command or the third cache read command has been input.

5. The memory device according to claim 2, wherein, When a second cache read command is input during the interval of the storage operation or the discharge operation for the first word line, the control logic controls the control circuit to start a preparation operation for the storage operation for the second word line when the discharge operation and the move operation for the first word line are fully executed, and controls the control circuit to execute the storage operation and the output operation for the second word line together when the preparation operation is fully executed.

6. The memory device according to claim 5, wherein, The control logic controls the control circuit to perform the operation of selecting the second word line by decoding the address input along with the second cache read command and resetting the first latch as the preparation operation.

7. The memory device according to claim 5, wherein, When the third cache read command is input during the interval of the storage operation or the discharge operation for the first word line, the control logic controls the control circuit to perform the output operation when the discharge operation for the first word line and the move operation for the first word line are fully executed.

8. A memory system comprising: A memory device includes a memory cell array and a plurality of page buffers. The memory cell array includes a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines. The plurality of page buffers are connected to the plurality of bit lines. Each page buffer includes a first latch and a second latch. as well as The controller generates a first cache read command for reading data from a page connected to a first word line among the plurality of word lines, transmits the first cache read command to the memory device, generates a second cache read command or a third cache read command, and transmits the second cache read command or the third cache read command to the memory device. Specifically, when the second cache read command or the third cache read command is input during the interval of a first storage operation that reads data of a page connected to the first word line in response to the first cache read command and stores the read data in the first latch, or a discharge operation that discharges the first word line after the first storage operation, the memory device performs the discharge operation and the move operation that moves the data of the first latch to the second latch in such a way that the execution intervals at least partially overlap.

9. The memory system according to claim 8, wherein, The controller generates the second cache read command and transmits it to the memory device so that the cache reads data from the page connected to the second word line among the plurality of word lines. After performing a cache read operation for the first word line, the controller generates the third cache read command and transmits the third cache read command to the memory device to terminate the cache read operation for the first word line.

10. The memory system according to claim 9, wherein, When the second cache read command or the third cache read command is entered during the period in which the first storage operation is performed, the memory device starts the move operation together with the start time of the discharge operation.

11. The memory system according to claim 10, wherein, When the second cache read command or the third cache read command is input during the interval in which the discharge operation is performed, the memory device begins the move operation upon determining that the second cache read command or the third cache read command has been input.

12. The memory system according to claim 9, wherein, When the second cache read command is input during the interval of executing the first storage operation or the discharge operation, the memory device begins a preparation operation for a second storage operation when the discharge operation and the move operation are fully executed, in order to read the data of the page connected to the second word line and store the read data in the first latch, and executes the second storage operation and outputs the data of the second latch to the controller when the preparation operation is fully executed.

13. The memory system according to claim 11, wherein, The memory device performs the operation of selecting the second word line by decoding the address input along with the second cache read command and resetting the first latch as a preparation operation.

14. The memory system according to claim 11, wherein, When the third cache read command is input during the interval of executing the first storage operation or the discharge operation, the memory device performs an output operation when the discharge operation and the move operation are fully executed.

15. A method of operating a memory device, the memory device comprising a memory cell array and a plurality of page buffers, the memory cell array comprising a plurality of memory cells connected between a plurality of word lines and a plurality of bit lines, the plurality of page buffers being connected to the plurality of bit lines, each page buffer comprising a first latch and a second latch, the method comprising the following steps: A first storage operation that stores data of a page connected to a first word line among the plurality of word lines in the first latch in response to input of a first cache read command; A discharge operation that discharges the first word line after the first storage operation; A move operation that moves the data from the first latch to the second latch after the first storage operation; as well as When a second cache read command or a third cache read command is input during the interval of executing the first storage operation or the discharge operation, the execution intervals of the discharge operation and the movement operation are executed in parallel in such a way that the execution intervals partially overlap.

16. The operating method according to claim 15, wherein, The second cache read command is a command used to read data from a page connected to the second word line among the plurality of word lines, and The third cache read command is used to end the cache read operation for the first word line after performing the cache read operation for the first word line.

17. The operating method according to claim 16, wherein, The parallel execution operation includes the following steps: When the second cache read command or the third cache read command is entered during the period in which the first storage operation is performed, the move operation begins simultaneously at the start time of the discharge operation; and When the second cache read command or the third cache read command is input during the interval in which the discharge operation is performed, the movement operation begins when it is determined that the second cache read command or the third cache read command has been input.

18. The operating method according to claim 16, further comprising the following steps: In response to the input of the second cache read command, the data of the page connected to the second word line is stored in the first latch; After the movement operation, the data from the second latch is output to the outside; as well as When the second cache read command is entered in the parallel execution operation, a preparation operation for preparing the second storage operation begins when the parallel execution operation is fully executed, and the second storage operation and the output operation are executed together when the preparation operation is fully executed.

19. The operating method according to claim 18, wherein, The preparation operation includes selecting the second word line by decoding the address input along with the second cache read command, and resetting the first latch.

20. The operating method according to claim 17, further comprising the following steps: When the third cache read command is input in the parallel execution operation, the output operation is performed when the parallel execution operation is fully executed.

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