One-time programmable memory elements

Abstract

The present invention discloses a single-time programmable memory device, which mainly includes a first memory cell area, wherein the first memory cell area further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on the other side of the first source line, a first diffusion region extending along a second direction on both sides of the first word line and the second word line, and a first metal interconnect connecting the first word line and the second word line.

Description

Technical Field

[0001] The present invention relates to a non-volatile memory element, and in particular to a one-time programmable memory element. Background Art

[0002] Semiconductor memory devices have been widely used in various electronic devices. For example, non-volatile memory is widely used in mobile phones, digital cameras, personal digital assistants, mobile computing devices, and other applications. Generally speaking, non-volatile memory mainly includes multi-time programmable (MTP) memory and one-time programmable (OTP) memory. Compared with rewritable memory, one-time programmable memory has the advantages of lower manufacturing cost and less loss of stored data. However, one-time programmable memory can only perform one-time data burning. Once the bits of specific memory cells in a specified memory block are rewritten through a one-time data writing program, those specific memory cells in the specified memory block cannot be burned again.

[0003] Since existing one-time programmable memory devices still have disadvantages such as weak read current in read mode and long stress time in program mode, how to improve the existing one-time programmable memory device architecture to solve the above problems is an important issue today. Summary of the Invention

[0004] One embodiment of the present invention discloses a one-time programmable memory device, which mainly includes a first memory cell region, wherein the first memory cell region further includes a first source line extending along a first direction on a substrate, a first word line extending along the first direction on one side of the first source line, a second word line extending along the first direction on the other side of the first source line, a first diffusion region extending along a second direction on both sides of the first word line and the second word line, and a first metal interconnect connecting the first word line and the second word line. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Figure 1 FIG. 1 is a schematic diagram of a layout of a one-time programmable memory device according to an embodiment of the present invention.

[0006] Description of main component symbols

[0007] 12: Base

[0008] 14: Storage unit area

[0009] 16: Storage unit area

[0010] 18: Storage unit area

[0011] 20: Storage unit area

[0012] 22: Storage unit area

[0013] 24: Storage unit area

[0014] 26: Source line

[0015] 28: Character Line

[0016] 30: Character line

[0017] 32: Source line

[0018] 34: Character Line

[0019] 36: Character Line

[0020] 38: Source line

[0021] 40: Character line

[0022] 42: Character Line

[0023] 44: Diffusion Zone

[0024] 46: Diffusion Zone

[0025] 48: Contact plug

[0026] 50:Metal interconnect

[0027] 52:Metal interconnect

[0028] 54:Metal interconnect DETAILED DESCRIPTION

[0029] Certain words are used in the specification and subsequent claims to refer to specific components. It should be understood by those with ordinary skill in the art that manufacturers may use different terms to refer to the same component. This specification and subsequent claims do not use differences in name as a way to distinguish components, but rather use differences in the functions of the components as the basis for distinction. The word "including" mentioned throughout the specification and subsequent claims is an open-ended term and should be interpreted as "including but not limited to". In addition, the word "connect" or "couple" herein includes any direct and indirect electrical connection means. Therefore, if the text describes a first device connected to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means.

[0030] Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram of the layout of a one-time programmable memory element according to an embodiment of the present invention. Figure 1As shown, the one-time programmable memory device of the present invention primarily comprises a substrate 12 formed of a semiconductor material, which may be selected from the group consisting of silicon, germanium, a silicon-germanium composite, silicon carbide, gallium arsenide, etc. Six memory cell regions, such as memory cell region 14, memory cell region 16, memory cell region 18, memory cell region 20, memory cell region 22, and memory cell region 24, are then defined on substrate 12. Each memory cell region preferably includes at least one source line, two word lines disposed on either side of the source line, and a diffusion region disposed between the source line and the word line in subsequent fabrication processes.

[0031] In this embodiment, the substrate 12 mainly includes a source line 26 extending along a first direction, such as the Y direction, on the substrate 12, a word line 28 extending along the same Y direction on one side of the source line 26, a word line 30 extending along the Y direction on the other side of the source line 26, a source line 32 extending along the Y direction on one side of the word line 28, a word line 34 extending along the Y direction on one side of the source line 32, a word line 36 extending along the Y direction on the other side of the source line 32, a source line 38 extending along the Y direction on one side of the word line 30, a word line 40 extending along the Y direction on one side of the source line 38, a word line 42 extending along the Y direction on the other side of the source line 38, and a diffusion region 44 extending along the Y direction. Diffusion regions 46 extend along a second direction, such as the X direction, on both sides of source line 26, word lines 28 and 30, source line 32, word lines 34 and 36, source line 38, and word lines 40 and 42. Diffusion regions 46 extend along a second direction, such as the X direction, on both sides of source line 26, word lines 28 and 30, source line 32, word lines 34 and 36, source line 38, and word lines 40 and 42. Contact plugs 48 are provided in diffusion regions 44 and 46, source lines 26, 32, 38, and word lines 28, 30, 34, 36, and 40, and metal interconnects 50, 52, and 54 connect contact plugs 48. In this embodiment, contact plugs 48 provided on diffusion regions 44 and 46 are also referred to as bit line contacts.

[0032] Taking the two groups of memory cell areas 14 and 16 in the middle as an example, the upper memory cell area 14 mainly includes the aforementioned source line 26, the word lines 28 and word lines 30 on both sides of the source line 26, the diffusion area 44 arranged on both sides of the source line 26 and on both sides of the word lines 28 and 30, the contact plugs 48 arranged on the diffusion areas 44 on both sides of the word lines 28 and 30 and directly above the word lines 28 and 30, and the metal interconnection lines 50 connected to the contact plugs 48, wherein the metal interconnection lines 50 are preferably the first layer of metal interconnection layer on the contact plugs 48 and connect the two word lines 28 and 30 through the contact plugs 48 arranged directly above the word lines 28 and 30. The memory cell region 16 below includes a source line 26, word lines 28 and 30 on either side of the source line 26, diffusion regions 46 disposed on either side of the source line 26 and on either side of the word lines 28 and 30, and contact plugs 48 disposed on the diffusion regions 46 on either side of the word lines 28 and 30 and directly above the word lines 28 and 30.

[0033] Looking at the two memory cell regions 18 and 20 on the left, the upper memory cell region 18 includes a source line 32, word lines 34 and 36 on either side of source line 32, diffusion regions 44 disposed on either side of source line 32 and on either side of word lines 34 and 36, contact plugs 48 disposed directly above word lines 34 and 36, and metal interconnects 52 electrically connecting word lines 34 and 36 via contact plugs 48. The lower memory cell region 20 includes a source line 32, word lines 34 and 36 on either side of source line 32, diffusion regions 46 disposed on either side of source line 32 and on either side of word lines 34 and 36, and contact plugs 48 disposed directly above source line 32.

[0034] Like the two memory cell regions 18 and 20 on the left, the two memory cell regions 22 and 24 on the right also include similar configurations. For example, the upper memory cell region 22 on the right includes a source line 38, word lines 40 and 42 on either side of the source line 38, diffusion regions 44 disposed on either side of the source line 38 and on either side of the word lines 40 and 42, contact plugs 48 disposed directly above the word lines 40 and 42, and metal interconnects 54 electrically connecting the word lines 40 and 42 via contact plugs 48. The lower memory cell region 24 includes a source line 38, word lines 40 and 42 on either side of the source line 38, diffusion regions 46 disposed on either side of the source line 38 and on either side of the word lines 40 and 42, and contact plugs 48 disposed directly above the source line 38. It should be noted that although the one-time programmable memory device in this embodiment uses six memory cell areas as an example, it is not limited to this number. According to other embodiments of the present invention, multiple memory cell areas configured in the manner described above can be defined on the substrate 12 based on the manufacturing process or product requirements. Such variations are also within the scope of the present invention.

[0035] In this embodiment, each source line 26, 32, 38 and word line 28, 30, 34, 36, 40, 42 includes a gate structure and spacers (not shown) disposed around the gate structure. Diffusion regions 44 and 46 on either side of the source lines 26, 32, 38 and word lines 28, 30, 34, 36, 40, 42 serve as source / drain regions. Each gate structure may be a polysilicon gate or a metal gate. Each gate structure may be fabricated using a gate-first process, a gate-last process (high-k first), or a gate-last process (high-k last) depending on the fabrication process requirements. Taking the metal gate of the present invention as an example, each gate structure may include components such as a dielectric layer, a high-k dielectric layer, a work function metal layer, and a low-resistance metal layer.

[0036] The high-k dielectric layer may include a dielectric material having a dielectric constant greater than 4, such as hafnium oxide (HfO2), hafnium silicon oxide (HfSiO4), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al2O3), lanthanum oxide (La2O3), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), strontium titanate oxide (SrTiO3), zirconium silicon oxide (ZrSiO4), hafnium zirconium oxide (HfZrO4), strontium bismuth tantalum oxide (strontium bismuth tantalum oxide), and the like. tantalate,SrBi2Ta2O9,SBT), lead zirconate titanate (leadzirconate titanate,PbZr x Ti 1-x O3, PZT), barium strontium titanate (barium strontium titanate, Ba x Sr 1- x TiO3, BST), or a combination thereof.

[0037] The work function metal layer is preferably used to adjust the work function of the metal gate, making it suitable for an N-type transistor (NMOS) or a P-type transistor (PMOS). If the transistor is an N-type transistor, the work function metal layer can be made of a metal material with a work function of 3.9 electron volts (eV) to 4.3 eV, such as, but not limited to, titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WAl), tantalum aluminide (TaAl), hafnium aluminide (HfAl), or TiAlC (titanium aluminum carbide). If the transistor is a P-type transistor, the work function metal layer can be made of a metal material with a work function of 4.8 eV to 5.2 eV, such as, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), or tantalum carbide (TaC). A barrier layer (not shown) can be included between the work function metal layer and the low resistance metal layer. The barrier layer can be made of materials such as titanium (Ti), titanium nitride (TiN), tantalum (Ta), or tantalum nitride (TaN). The low-resistance metal layer can be selected from low-resistance materials such as copper (Cu), aluminum (Al), tungsten (W), titanium aluminum alloy (TiAl), cobalt tungsten phosphide (CoWP), or combinations thereof. Since the fabrication of the metal gate is well known in the art, it will not be further described here.

[0038] In summary, the present invention mainly discloses a layout pattern of a one-time programmable memory element, which mainly sets two word lines on both sides of a source line to reduce the overall area required for the layout pattern. Figure 1 Taking the disclosed embodiment as an example, the source line in the memory cell region is preferably immediately adjacent to two word lines on either side, and these word lines are in turn immediately adjacent to two word lines on either side. In other words, the diffusion region between the word lines on the left side preferably directly contacts the edges of the word lines, without any shallow trench isolation between the diffusion region and the word lines. Similarly, the diffusion region between the word lines on the right side preferably directly contacts the edges of the word lines, without any shallow trench isolation between the diffusion region and the word lines.

[0039] According to the preferred embodiment of the present invention, the distance between each memory cell region along the X direction can be reduced by about 0.93 times compared to the prior art through the above configuration, and the distance between each memory cell region along the Y direction can be slightly larger by 1.05 times compared to the prior art, thereby reducing the area of ​​each memory cell region by about 3% compared to the prior art. In addition, in terms of performance, since electrons are along the Figure 1 The direction of the middle arrow is transmitted from the word lines 28 and 30 on both sides to the middle source line 26. Through the above layout, the present invention can reduce the programming time while maintaining the Vpp voltage, reduce the Vpp voltage while maintaining the programming time, and increase the read current by at least twice.

[0040] The above descriptions are merely preferred embodiments of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. A one-time programmable memory element, characterized in that Include: The first storage unit area includes: A first source line extending along a first direction on the substrate, wherein the first source line is a gate structure; A first word line extending along the first direction to one side of the first source line; A second word line extending along the first direction to the other side of the first source line; A first diffusion region extending along a second direction on both sides of the first word line and the second word line; as well as The first metal interconnection line connects the first word line and the second word line. 2 . The one-time programmable memory device as claimed in claim 1 , wherein the first diffusion region is disposed between the first word line and the first source line. 3 . The one-time programmable memory device as claimed in claim 1 , wherein the first diffusion region is disposed between the first source line and the second word line. 4 . The one-time programmable memory device as claimed in claim 1 , wherein the first memory cell region further comprises a first bit line contact disposed on the first diffusion region on one side of the first word line. 5 . The one-time programmable memory device as claimed in claim 1 , wherein the first memory cell region further comprises a second bit line contact disposed on the first diffusion region on one side of the second word line.

6. The one-time programmable memory device according to claim 1 , further comprising a second memory cell area, the second memory cell area comprising: The first source line extends along the first direction; The first word line extends along the first direction to one side of the first source line; The second word line extends along the first direction to the other side of the first source line; and The second diffusion region extends along the second direction on both sides of the first word line and the second word line. 7 . The one-time programmable memory device as claimed in claim 6 , wherein the second diffusion region is disposed between the first word line and the first source line. 8 . The one-time programmable memory device as claimed in claim 6 , wherein the second diffusion region is disposed between the first source line and the second word line.

9. The one-time programmable memory device of claim 6, wherein the second memory cell region further comprises a third bit line contact disposed on the second diffusion region on one side of the first word line.

10. The one-time programmable memory device of claim 6, wherein the second memory cell region further comprises a fourth bit line contact disposed on the second diffusion region on one side of the second word line.

11. The one-time programmable memory device according to claim 6 , further comprising a third memory cell area, the third memory cell area comprising: A second source line extending along the first direction to one side of the first word line; a third word line extending along the first direction to one side of the second source line; a fourth word line extending along the first direction to the other side of the second source line; The first diffusion region extends along the second direction on both sides of the third word line and the fourth word line; as well as The second metal interconnection line connects the third word line and the fourth word line. 12 . The one-time programmable memory device as claimed in claim 11 , wherein the first diffusion region is disposed between the third word line and the second source line. 13 . The one-time programmable memory device as claimed in claim 11 , wherein the first diffusion region is disposed between the second source line and the fourth word line.

14. The one-time programmable memory device according to claim 11 , further comprising a fourth memory cell area, the fourth memory cell area comprising: The second source line extends along the first direction; The third word line extends along the first direction to one side of the second source line; The fourth word line extends along the first direction to the other side of the second source line; and The second diffusion region extends along the second direction to both sides of the third character line and the fourth character line. 15 . The one-time programmable memory device as claimed in claim 14 , wherein the second diffusion region is disposed between the third word line and the second source line. 16 . The one-time programmable memory device of claim 14 , wherein the second diffusion region is disposed between the second source line and the fourth word line.

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