Three-terminal memory transistor based on carbon nanotubes and its preparation method and use method

Abstract

The present invention provides a three-terminal carbon nanotube-based memory transistor and its preparation and use methods. The transistor comprises a substrate, a semiconductor channel disposed on the substrate, a source electrode and a drain electrode disposed on the semiconductor channel, a dielectric layer disposed on the source and drain electrodes and in the region of the semiconductor channel between the source and drain electrodes, and a gate electrode disposed on the dielectric layer. The sides of the source electrode and the drain electrode facing away from the semiconductor channel are completely covered by the dielectric layer, and the source and drain electrodes are connected via the semiconductor channel. The semiconductor channel is made of semiconducting carbon nanotubes. The present invention can simulate heterosynaptic plasticity in various ways.

Description

Technical Field

[0001] The present invention relates to the technical field of bionic synaptic devices, and in particular to a three-terminal memory transistor based on carbon nanotubes and a preparation method and a use method thereof. Background Art

[0002] The human brain outperforms traditional computers in processing complex tasks and unstructured information, such as perception, classification, and pattern recognition, with superior performance and ultra-low power consumption. Consequently, brain-inspired neuromorphic computing has seen rapid development in recent years. Neurons, synapses, and the neural system play a crucial role in brain function. Therefore, emulating elements of biological neuronal systems with artificial neurons and synapses is a key focus of hardware implementation in artificial neural networks and neuromorphic computing.

[0003] In recent years, there has been much research aimed at emulating synaptic functionality using single two-terminal, three-terminal, or multi-terminal devices. Simultaneous information transfer and self-learning in two-terminal synaptic devices is a challenging task. However, these two functions, along with coordinated control, can be readily implemented in three-terminal / multi-terminal synaptic transistors. Consequently, robust artificial neuronal networks can be developed based on synaptic transistors.

[0004] Biological studies have shown that the connection strength of synapses in the human brain is not only regulated by the preceding and following neurons, but also by the surrounding neurons, a phenomenon known as heterosynaptic plasticity. However, in previous work, in order to simulate synaptic function, the input of electrical stimulation was limited to a specific port of the device (such as the gate of a synaptic transistor or the drain of a memory transistor), and the operating voltage was relatively high, making it impossible to achieve complex synaptic properties such as heterosynaptic plasticity. Therefore, developing electronic devices that can simulate heterosynaptic plasticity is conducive to more realistically simulating biological synaptic plasticity, thereby promoting the development of neuromorphic computing. Summary of the Invention

[0005] The purpose of the present invention is to provide a three-terminal memory transistor based on carbon nanotubes and its preparation method and use method, which can simulate heterosynaptic plasticity.

[0006] The present invention is achieved through the following technical solutions:

[0007] The carbon nanotube-based three-terminal memory transistor of the present invention includes a substrate, a semiconductor channel is provided on the substrate, a source electrode and a drain electrode are provided on the semiconductor channel, a dielectric layer is provided on the source electrode and the drain electrode and in the area of the semiconductor channel between the source electrode and the drain electrode, and a gate electrode is provided on the dielectric layer; a side of the source electrode away from the semiconductor channel and a side of the drain electrode away from the semiconductor channel are completely covered by the dielectric layer, and the source electrode and the drain electrode are connected through the semiconductor channel; the material of the semiconductor channel is a semiconductor-type carbon nanotube.

[0008] Furthermore, the material of the dielectric layer is a high-k metal oxide having memristive properties, including but not limited to hafnium oxide, aluminum oxide or tungsten oxide.

[0009] Furthermore, the source electrode, the drain electrode and the gate electrode may be made of various metals, such as Ti, Au, Pt and the like.

[0010] Furthermore, the three-terminal memory transistor structure is a top-gate structure.

[0011] Furthermore, the three-terminal memory transistor may have both memristive characteristics and field effect transistor characteristics.

[0012] Furthermore, the method for preparing the three-terminal memory transistor based on carbon nanotubes comprises the following steps:

[0013] S1. Provide a substrate and perform standard cleaning on the substrate;

[0014] S2, forming a semiconductor channel on the substrate obtained in S1;

[0015] S3, developing source and drain electrode patterns on the substrate obtained in S2, depositing electrode metal material on the source and drain electrode patterns, and performing lift-off to form the source and drain electrodes;

[0016] S4, depositing a dielectric layer on the substrate obtained in S3;

[0017] S5. Develop a gate electrode pattern on the dielectric layer obtained in S4, deposit an electrode metal material on the gate electrode pattern, and perform lift-off to form a gate electrode, thereby obtaining the carbon nanotube-based three-terminal memory transistor.

[0018] Furthermore, in S3 and S5 , corresponding patterns are developed on the substrate by photolithography.

[0019] Furthermore, in S3 and S5 , the electrode metal material is deposited by evaporation, laser pulse or atomic layer deposition.

[0020] Furthermore, the preparation method of the semiconductor channel in S2 is as follows:

[0021] a1. Hydrophilizing the substrate obtained in S1 by O2 reactive ion etching;

[0022] a2. Soaking the substrate in a solution containing 3-aminopropyltriethoxysilane (APTES) for 30 minutes to form a self-assembled monolayer;

[0023] a3. Place the substrate with the APTES self-assembled monolayer obtained in a2 into the pre-dispersed semiconductor carbon nanotube solution;

[0024] a4. After soaking for a period of time, the substrate is taken out, rinsed with a large amount of deionized water, and blown dry with a nitrogen gun to obtain a carbon nanotube film on the substrate;

[0025] a5. Perform photolithography and plasma etching on the carbon nanotube film to obtain the semiconductor channel.

[0026] Compared with the prior art, the present invention has the following beneficial effects:

[0027] The three-terminal carbon nanotube-based memory transistor provided by the present invention uses a high-k metal oxide with memristive properties as the gate dielectric layer material of the field-effect transistor, which can reduce the operating voltage of the device. The side of the source electrode away from the semiconductor channel and the side of the drain electrode away from the semiconductor channel are completely covered by the dielectric layer. Therefore, the gate electrode and the drain electrode can be used as input ports for pulse signals, simulating the heterosynaptic plasticity of biological synapses in different ways; multiple input ports can simulate heterosynaptic plasticity, which is conducive to achieving multi-dimensional control of the device and providing greater flexibility for designing complex neuromorphic circuits. The structural arrangement of the present invention is that the dielectric layer can be used as a common oxide dielectric in the vertical direction and as a memristive dielectric layer in the horizontal direction, having both memristive and field-effect transistor characteristics, so that synaptic characteristics can be achieved in two ways. Carbon nanotubes are quasi-one-dimensional materials with special electrical properties. Their ultra-thin body thickness (1-2nm) and large specific surface area make them extremely sensitive to surrounding charges. The trapped charge can effectively modulate the conductivity of the carbon nanotube channel, and the retention time of the trapped charge is adjustable. During a voltage pulse applied to the gate electrode, the conductivity of the carbon nanotube (CNT) can change significantly as the charge state of nearby defects changes. During a voltage pulse applied to the drain electrode, the memristive properties of the gate dielectric layer are used to achieve bipolar simulated resistive switching behavior. The resistance state is controlled by a resistive switch near the contact via the drain electrode voltage pulse (i.e., non-volatile operation), while during reading (i.e., volatile operation), the channel conductivity can be further modulated by the gate electrode bias. Both methods can simulate heterosynaptic plasticity and effectively simulate learning and memory functions. The resulting memory transistor has great potential in realizing energy-efficient neuromorphic applications.

[0028] The invention discloses a method for preparing a three-terminal memory transistor based on carbon nanotubes. The process is simple to operate, compatible with CMOS technology, and plays a key role in improving device integration.

[0029] Furthermore, hydrophilic treatment of the substrate can remove trace pollutants on the substrate surface, eliminate uncertainties in the APTES adsorption process, and improve the uniformity and reliability of the deposited carbon nanotube film.

[0030] Furthermore, a clean substrate is soaked in a solution containing APTES. APTES will condense with the hydroxyl groups on the substrate surface and adsorb onto the substrate surface to form a self-assembled monolayer. The amino groups at its end can adsorb and fix the randomly moving carbon nanotubes in the solution, thereby forming a carbon nanotube film on the substrate surface.

[0031] In the carbon nanotube-based three-terminal memory transistor of the present invention, both the gate electrode and the drain electrode can serve as input ports for pulse signals, and two methods can be used to simulate heterosynaptic plasticity, thereby expanding the scope of application. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 Schematic diagram of the structure of a three-terminal memory transistor based on carbon nanotubes;

[0033] Figure 2 A flow chart for forming a three-terminal memory transistor based on carbon nanotubes;

[0034] Figure 3 Flowchart for solution-based carbon nanotube deposition;

[0035] Figure 4 Flowchart for forming carbon nanotube channels.

[0036] The symbols in the figure represent the following:

[0037] 1. Substrate; 2. Semiconductor channel; 3. Source electrode; 4. Drain electrode; 5. Dielectric layer; 6. Gate electrode. DETAILED DESCRIPTION

[0038] The present invention will be described in further detail below in conjunction with the accompanying drawings, which are provided to explain the present invention rather than to limit it. For the sake of clarity, the various parts in the accompanying drawings are not drawn according to the true scale.

[0039] Hereinafter, an example of a three-terminal memory transistor based on carbon nanotubes and a method for manufacturing the same according to the present invention will be described with reference to the accompanying drawings.

[0040] Reference Figure 1The present invention provides a three-terminal carbon nanotube-based memory transistor. The device includes a substrate 1, on which is disposed a semiconductor channel 2. A source electrode 3 and a drain electrode 4 are disposed on the semiconductor channel 2. A dielectric layer 5 is disposed on the source electrode 3 and the drain electrode 4, and in the region of the semiconductor channel 2 between the source electrode 3 and the drain electrode 4. A gate electrode 6 is disposed on the dielectric layer 5. The side of the source electrode 3 facing away from the semiconductor channel 2 and the side of the drain electrode 4 facing away from the semiconductor channel 2 are completely covered by the dielectric layer 5. The source electrode 3 and the drain electrode 4 are connected via the semiconductor channel 2. The semiconductor channel 2 is made of semiconducting carbon nanotubes. The dielectric layer 5 is made of a high-k metal oxide having memristive properties.

[0041] The three-terminal memory transistor has two methods for simulating memory and learning functions. When an electric pulse is applied to the drain electrode 4, the high-k metal oxide with memristive properties generates oxygen vacancies under the stimulation of the electric pulse, forming conductive filaments. The accumulation of conductive filaments is similar to the signal transmission in biological neurons. The drain electrode 4 can be regarded as a presynaptic neuron, the source electrode 3 as a postsynaptic neuron, and the gate electrode 6 as a heterosynaptic neuron. The resistance state of the dielectric layer 5 is regarded as the synaptic weight. By applying an electric pulse to the drain electrode 4, the resistance of the dielectric layer 5 is adjusted, simulating heterosynaptic plasticity and thus achieving the simulation of learning and memory functions. When an electric pulse is applied to the gate electrode 6, the oxygen vacancies and trapped charges in the dielectric layer 5 will screen the gate voltage and affect the conductance of the carbon nanotube channel. This process is very similar to the release of neurotransmitters, which causes changes in the postsynaptic potential of biological neurons. If the gate electrode 6 is regarded as a presynaptic neuron and the source / drain electrodes as heterosynaptic neurons, the carbon nanotube three-terminal memory transistor can naturally simulate the updating of synaptic weights.

[0042] The present invention also provides a method for preparing the above-mentioned three-terminal memory transistor based on carbon nanotubes, such as Figure 2 As shown, the following steps are included:

[0043] S1.1. Provide a substrate and perform standard cleaning on the substrate;

[0044] S1.2, depositing a pre-dispersed carbon nanotube solution onto a substrate using a solution method to pattern carbon nanotube channels;

[0045] S1.3, depositing source and drain electrodes at both ends of the carbon nanotube channel on the substrate;

[0046] S1.4, depositing a dielectric layer on the source electrode, the drain electrode, and the region of the semiconductor channel 2 between the source electrode 3 and the drain electrode 4;

[0047] S1.5. Depositing a gate electrode on the dielectric layer to obtain a three-terminal memory transistor based on carbon nanotubes.

[0048] The preparation method further includes annealing the dielectric layer, gate electrode, source electrode, and drain electrode after forming them, wherein the annealing conditions are 20-300° C. for 1-2 hours, and the specific annealing conditions are selected according to actual needs.

[0049] In this embodiment, the substrate may be a silicon dioxide substrate, but is not limited thereto. Other substrates may also be used, such as flexible substrates and polyethylene terephthalate (PET), which are not listed here. The standard cleaning procedure for the substrate before use includes ultrasonic cleaning with acetone, isopropyl alcohol, and ethanol, followed by drying under a nitrogen stream.

[0050] In this embodiment, the gate, source, and drain electrodes may be made of metal materials such as Ti, Au, Al, Ag, and Pt. These materials are not specified here and can be selected based on actual needs. The deposition method may be electron beam evaporation, laser pulse deposition, or magnetron sputtering. These materials are not specified here and can be selected based on actual needs, but the deposition must ensure that the carbon nanotube layer is not damaged.

[0051] In this embodiment, the dielectric layer material is high-k metal oxide, and the deposition method can be electron beam evaporation or atomic layer deposition (ALD). The method can be selected based on the material, but it must be ensured that the carbon nanotube layer is not damaged after deposition.

[0052] This example uses a solution method to deposit a pre-dispersed carbon nanotube solution onto a substrate. The specific process steps are as follows: Figure 3 ,include:

[0053] S2.1. Perform standard cleaning on the substrate;

[0054] S2.2, performing a hydrophilic treatment on the cleaned substrate by O2 reactive ion etching;

[0055] S2.3. Soak the clean substrate in a solution containing 3-aminopropyltriethoxysilane (APTES) for 30 min to form a self-assembled monolayer.

[0056] S2.4, placing the substrate with the APTES self-assembled monolayer into the pre-dispersed carbon nanotube solution;

[0057] S2.5. After soaking for a period of time, take out the substrate, rinse it with a large amount of deionized water, and blow it dry with a nitrogen gun. At this point, the carbon nanotube film is successfully deposited on the prepared substrate.

[0058] The carbon nanotubes used in this example are purchased semiconductor-enriched carbon nanotubes, which are dispersed in nitrogen-methylpyrrolidone (NMP) solvent using an ultrasonic grinder.

[0059] This example uses a method of photolithography combined with plasma etching to form carbon nanotube channels. The specific process steps are as follows: Figure 4 ,include:

[0060] S3.1, spin coating a negative photoresist on the substrate on which the carbon nanotube film has been deposited, as prepared in step S2.5;

[0061] S3.2, exposure;

[0062] S3.3, etching away the carbon nanotubes outside the channel region using a plasma etching method;

[0063] S3.4. Soak and clean the sample after photolithography in step S3.3 with acetone, isopropyl alcohol, and anhydrous ethanol in sequence to remove the photoresist.

[0064] The width of the carbon nanotube channel can be 10 to 30 micrometers, and the length can be 0.5 to 1 micrometer. The carbon nanotube channel can be etched using other etching processes known in the art, and the process parameters can be adjusted according to actual conditions.

[0065] The preparation method of a three-terminal memory transistor based on carbon nanotubes is described in detail below with reference to a specific embodiment:

[0066] Example 1

[0067] Step 1: Use a Si / SiO2 substrate with a Si thickness of 500 μm and a SiO2 thickness of 300 nm. Clean it with acetone, isopropyl alcohol, and anhydrous ethanol in sequence, rinse with deionized water, and blow dry with nitrogen.

[0068] Step 2: Use an ultrasonic grinder to disperse the purchased semiconductor carbon nanotube solid in NMP organic solvent to obtain a stable and reliable dispersed carbon nanotube solution.

[0069] Step 3: The substrate obtained in step 1 is hydrophilized by O2 reactive ion etching and then immersed in a solution containing APTES for 30 minutes to form a self-assembled monolayer on the surface of the substrate.

[0070] Step 4: Place the substrate obtained in step 4 into the pre-dispersed carbon nanotube solution obtained in step 2, soak for a period of time, take it out, rinse it with a large amount of deionized water, and blow dry it with a nitrogen gun to complete the deposition of the carbon nanotube film.

[0071] Step 5: Spin-coat a negative photoresist on the substrate obtained in step 4, expose it, and then use plasma etching to etch away the carbon nanotubes outside the channel area. Then, soak and clean it with acetone, isopropyl alcohol, and anhydrous ethanol in sequence to remove the photoresist and obtain a channel with a width of 30 μm and a length of 1 μm.

[0072] Step 6: Use electron beam lithography to pattern the source electrode deposition area and the drain electrode deposition area, then use electron beam evaporation to deposit 10nm Ti as an adhesion layer and then deposit 100nm Au in the source electrode deposition area. Similarly, use electron beam evaporation to deposit 10nm Ti as an adhesion layer and then deposit 100nm Au in the drain electrode deposition area. After lift-off, the source electrode and drain electrode are formed in the source electrode and drain electrode deposition areas.

[0073] Step 7: Deposit a 20 nm thick HfO2 dielectric layer on the substrate obtained in step 6 using ALD, using Hf(NMe2)4 and H2O as precursors and N2 as carrier gas.

[0074] Step 8: Use electron beam lithography to pattern the gate electrode deposition area, then use electron beam evaporation to deposit 10nm Ti as an adhesion layer, and then deposit 100nm Au on the gate electrode deposition area. After lift-off, a gate electrode is formed in the gate electrode deposition area, and finally a carbon-based multi-terminal bionic synaptic device is obtained.

[0075] The above embodiments are only several ways to implement the present invention, and the present invention is not limited thereto.

[0076] The three-terminal memory transistor based on carbon nanotubes prepared by the present invention can simulate the learning and memory functions of synapses. Method 1: The electrical stimulation received by the gate electrode of the device can be regarded as a presynaptic signal, the electrical stimulation received by the drain electrode of the device can be regarded as the influence of heterosynaptic neurons on the synapses, and the conductance of the semiconductor channel can be regarded as the synaptic weight. When the gate electrode is stimulated by long-term continuous positive / negative pulses, the conductivity of the semiconductor channel will increase / decrease in a step-by-step manner, and tend to stabilize after applying multiple pulse cycles. This phenomenon is similar to the long-term potentiation (LTP) / long-term depression (LTD) plasticity of the synapse. Method 2: The drain electrode can be regarded as a presynaptic neuron, the source electrode as a postsynaptic neuron, the gate electrode as a heterosynaptic neuron, the resistance state of the dielectric layer as the synaptic weight, and the resistance of the dielectric layer is adjusted by applying an electric pulse through the drain electrode to simulate synaptic plasticity. When the drain electrode is stimulated by long-term, continuous positive / negative pulses, the dielectric layer's resistance continuously increases / decreases, stabilizing after multiple pulse cycles. This phenomenon is similar to the long-term potentiation (LTP) / long-term depression (LTD) plasticity of synapses. When the gate / drain electrodes are stimulated by pulse pairs with a fixed time interval, the spike timing-dependent plasticity (STDP) can be measured by adjusting the time interval between the two pulses. These results have applications in pattern recognition, sequence learning, and consistency detection.

[0077] The above content is only for explaining the technical idea of the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A method for using a three-terminal memory transistor based on carbon nanotubes, characterized in that: The carbon nanotube-based three-terminal memory transistor comprises a substrate (1), a semiconductor channel (2) is provided on the substrate (1), a source electrode (3) and a drain electrode (4) are provided on the semiconductor channel (2), a dielectric layer (5) is provided on the source electrode (3) and the drain electrode (4) and in a region of the semiconductor channel (2) between the source electrode (3) and the drain electrode (4), and a gate electrode (6) is provided on the dielectric layer (5); a side of the source electrode (3) away from the semiconductor channel (2) and a side of the drain electrode (4) away from the semiconductor channel (2) are all covered by the dielectric layer (5); the material of the semiconductor channel (2) is a semiconductor-type carbon nanotube, and the material of the dielectric layer (5) is a high-k metal oxide; How to use: The drain electrode (4) is regarded as a presynaptic neuron, the source electrode 3 is regarded as a postsynaptic neuron, the gate electrode 6 is regarded as a heterosynaptic neuron, and the resistance state of the dielectric layer (5) is regarded as a synaptic weight. An electric pulse is applied to the drain electrode (4) to adjust the resistance of the dielectric layer (5) to simulate heterosynaptic plasticity; Alternatively, the gate electrode (6) is used as a presynaptic neuron, the source electrode / drain electrode is used as a heterosynaptic neuron, and the conductance of the semiconductor channel is used as the synaptic weight. Applying an electric pulse to the gate electrode (6) can simulate the update of the synaptic weight.

2. The method for using the three-terminal memory transistor based on carbon nanotubes according to claim 1, characterized in that: The material of the dielectric layer (5) is hafnium oxide, aluminum oxide or tungsten oxide.

3. The method for using the three-terminal memory transistor based on carbon nanotubes according to claim 1, characterized in that: The materials of the source electrode (3), the drain electrode (4) and the gate electrode (6) are independently Ti, Au or Pt.

4. The method for using the three-terminal memory transistor based on carbon nanotubes according to claim 1, characterized in that: A method for preparing a three-terminal memory transistor based on carbon nanotubes, comprising: S1. forming a semiconductor channel on a substrate; S2. depositing electrode metal materials on the semiconductor channel to form a source electrode and a drain electrode; S3, depositing a dielectric layer on the source electrode, the drain electrode and the region where the semiconductor channel is located between the source electrode and the drain electrode; S4. Depositing an electrode metal material on the dielectric layer to form a gate electrode, thereby obtaining the carbon nanotube-based three-terminal memory transistor.

5. The method for using the three-terminal memory transistor based on carbon nanotubes according to claim 4, characterized in that: S1 specifically includes: a1. Hydrophilizing the substrate by O2 reactive ion etching; a2. Soaking the hydrophilized substrate in a solution containing 3-aminopropyltriethoxysilane to form a self-assembled monolayer; a3. Soaking the substrate with the self-assembled monolayer obtained in a2 into a pre-dispersed semiconductor carbon nanotube solution; a4, cleaning and drying the substrate soaked in a3, and obtaining a carbon nanotube film on the substrate; a5. Perform photolithography and plasma etching on the carbon nanotube film to form a semiconductor channel on the substrate.

6. The method for using the three-terminal memory transistor based on carbon nanotubes according to claim 5, characterized in that: a5 specifically comprises: spin coating negative photoresist on the carbon nanotube film, photolithography, and etching away the carbon nanotubes outside the channel region by plasma etching; and removing the photoresist by soaking and cleaning with acetone, isopropyl alcohol, and anhydrous ethanol to form a semiconductor channel on the substrate.

7. The method for using the three-terminal memory transistor based on carbon nanotubes according to claim 4, characterized in that: In S2 and S4, electrode metal materials are deposited by evaporation, laser pulse or atomic layer deposition.

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