Radar signal processing system with self-interference cancellation function

Abstract

The present invention discloses a radar signal processing system with a self-interference elimination function, comprising an analog front end (AFE) processor, an analog-to-digital converter (ADC), an adaptive interference canceller (AIC) and a digital-to-analog converter (DAC). The AFE processor receives an original input signal and generates an analog input signal, the ADC converts the analog input signal into a digital input signal, the AIC generates a digital interference signal by performing adaptive interference elimination processing according to the digital input signal, the DAC converts the digital interference signal into an analog interference signal, and finally the analog interference signal is fed back to the AFE processor, and the AFE processor eliminates the analog interference signal from the original input signal when performing front-end processing, thereby reducing the static interference generated by leakage from a nearby transmitter during front-end processing.

Description

Technical Field

[0001] The present invention relates to a radar system, in particular to a radar system with a self-interference elimination function. Background Art

[0002] See also Figure 8 The frequency modulated continuous wave (FMCW) radar system is a radar system having a processor 81, a transmitter 82 and a receiver 83. The transmitter 82 broadcasts a detection signal, which is a continuous wave of a known frequency. The detection signal hits the target A1 and is reflected by the target A1. Then, the reflected detection signal is received by the receiver 83. Since the frequency of the detection signal is known and the frequency of the reflected detection signal can be detected, the processor 81 calculates the speed and distance of the target A1 according to the principle of Doppler effect and frequency response. However, since the transmitter 82 and the receiver 83 are set in close positions, the leaked detection signal will also be received by the receiver 83. The leaked detection signal is a harmful signal, which will interfere with the actually received reflected detection signal, resulting in calculation errors of the processor 81. This situation is also called self-interference of the radar system.

[0003] See also Fig. 9 , the conventional method for dealing with the self-interference problem is to set an adaptive interference canceller (Adaptive Interference Canceller, AIC) in a digital signal processor. The processor 81 may include: an analog front end (AnalogFont End, AFE) 811, which is used to perform front-end processing on the detection signal; an analog-digital converter (Analog-DigitalConverter ADC) 812, which is used to convert the detection signal into a digital detection signal, and then transmit the digital detection signal to a digital signal processor (Digital Signal Processor, DSP) 813 for further calculation. The adaptive interference canceller 813A in the DSP 813 is usually used to calculate the static interference signal of static objects in the environment. In theory, the static interference signal should include the detection signal leaked by the transmitter. However, if the intensity of the leakage detection signal received by the receiver 83 is higher than a certain threshold, the leaked detection signal may cause the AFE 811 of the processor 81 to saturate. The saturation in the AFE 811 will cause serious performance degradation.

[0004] Furthermore, to avoid saturation of the analog front end of the processor 81, the system needs to achieve isolation between the receiver 83 and the transmitter 82. However, in reality, the antenna isolation technology of this radar system can only achieve an isolation effect of 20-30dB between the antenna of the transmitter 82 and the antenna of the receiver 83, which is not enough for the radar system that requires accurate detection and calculation results. Summary of the invention

[0005] The object of the present invention is to provide a radar signal processing system with a self-interference elimination function.

[0006] To achieve the above object, the radar signal processing system of the present invention receives an original input signal through a receiving antenna, comprising:

[0007] A signal input terminal, electrically connected to a receiving antenna, for receiving the original input signal;

[0008] an analog front end (AFE) processor, electrically connected to the signal input terminal, for performing front end processing according to the original input signal and generating an analog input signal;

[0009] an analog-to-digital converter (ADC), electrically connected to the analog front-end processor, and configured to convert the analog input signal into a digital input signal;

[0010] an adaptive interference canceller (AIC), electrically connected to the analog-to-digital converter, for performing adaptive interference cancellation processing on the digital input signal and generating a digital interference signal;

[0011] A digital-to-analog converter (DAC), electrically connected to the adaptive interference canceller, for converting the digital interference signal into an analog interference signal, and outputting the analog interference signal to the analog front-end processor; wherein,

[0012] The analog front-end processor removes the analog interference signal from the original input signal when performing front-end processing.

[0013] In the present invention, the digital interference signal generated by the adaptive interference canceller is further converted into an analog interference signal by a digital-to-analog converter. The analog interference signal is transmitted to the analog front-end processor to eliminate the interference part in the original input signal. Since the analog interference signal is a static interference signal calculated, it contains the self-interference signal received from the receiver, so the self-interference part in the original input signal can be offset or at least significantly degraded. Such a feedback loop directly reduces the self-interference leakage of the transmitter in the analog front-end processor, and also avoids the risk of saturation of the analog front-end processor.

[0014] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 FIG. 4 is a block diagram of a radar signal processing system according to the present invention.

[0016] Figure 2 FIG. 4 is a block diagram of a radar signal processing system according to a first embodiment of the present invention.

[0017] Figure 3 FIG. 4 is a block diagram of a radar signal processing system according to a second embodiment of the present invention.

[0018] Figure 4 FIG. 4 is a block diagram of a radar signal processing system according to the present invention.

[0019] Figure 5 FIG. 4 is a block diagram of a radar signal processing system according to a third embodiment of the present invention.

[0020] Figure 6 FIG. 4 is a block diagram of a radar signal processing system according to a fourth embodiment of the present invention.

[0021] Figure 7 FIG. 4 is another specific block diagram of the radar signal processing system of the present invention.

[0022] Figure 8 Schematic diagram of a traditional FMCW radar system.

[0023] Fig. 9 Block diagram of a conventional processor for an FMCW radar system. DETAILED DESCRIPTION

[0024] The structural principle and working principle of the present invention are described in detail below in conjunction with the accompanying drawings:

[0025] See also Figure 1, a radar processing system with a self-interference cancellation function includes a signal input terminal IN, an analog front end (AFE) processor 10, an analog-to-digital converter (ADC) 20, an adaptive interference canceller (AIC) 30, and a digital-to-analog converter (DAC) 40. The signal input terminal IN is electrically connected to a receiving antenna, and is used to receive an original input signal through the receiving antenna. The AFE processor 10 is electrically connected to the signal input terminal IN, and is used to perform front-end processing according to the original input signal and generate an analog input signal. The ADC 20 is electrically connected to the AFE processor 10, and is used to convert the analog input signal into a digital input signal. The AIC 30 is electrically connected to the ADC 20, and is used to perform an adaptive interference cancellation process on the digital input signal and generate a digital interference signal. The DAC 40 is electrically connected to the AIC 30, and is used to convert the digital interference signal into an analog interference signal and output the analog interference signal to the AFE processor 10. Among them, the AFE processor 10 eliminates the analog interference signal from the original input signal when performing the front-end processing.

[0026] The AFE processor 10 in the present invention can be constructed using various structures and perform different levels of front-end processing through different methods according to system requirements. Figure 2 As shown, in the first embodiment, the AFE processor 10 includes a trans-impedance amplifier (TIA) 11 and a programmable gain amplifier (PGA) 12. The TIA 11 is electrically connected to the signal input terminal IN and receives the original input signal. The PGA 12 is electrically connected between the TIA 11 and the ADC 20. The original input signal is converted into an analog input signal through the TIA 11 and the PGA 12, and the analog input signal is output from the PGA 12 to the ADC 20.

[0027] The analog interference signal can be fed back to the AFE processor 10 via the feedback unit 13. Figure 2 In the first embodiment of the present invention, the TIA 11 is connected to the signal input terminal IN through the feedback unit 13, and the feedback unit 13 is also connected to the DAC 40 to receive the analog interference signal. The feedback unit 13 eliminates the analog interference signal from the original input signal and outputs the original input signal after the interference is eliminated to the TIA 11.

[0028] See also Figure 3In the second embodiment of the present invention, the PGA 12 is connected to the TIA 11 through the feedback unit 13. That is, the feedback unit 13 is connected between the PGA 12 and the TIA 11. The feedback unit 13 receives the original input signal from the TIA 11. The feedback unit 13 is also connected to the DAC 40 to receive the analog interference signal. The feedback unit 13 eliminates the analog interference signal from the original input signal received by the TIA 11, and outputs the original input signal after the interference is eliminated to the PGA 12.

[0029] See also Figure 4 , the AFE processor 10 may further include a high pass filter (HPF) 14, which is connected between the TIA 11 and the feedback unit 13, that is, the feedback unit 13 is connected to the TIA 11 through the HPF 14. Therefore, the HPF 14 receives the original input signal of the TIA 11, and then filters the original input signal of the TIA 11 before outputting the original output signal to the feedback unit 13. In this way, after the original input signal is filtered, the analog interference signal is eliminated, and then it is output to the PGA 12.

[0030] See also Figure 5 In the third embodiment of the present invention, the radar processing system further includes a control input terminal CTL for receiving a control signal. The AFE processor includes a TIA 11, a PGA 12, a first feedback unit 151, a second feedback unit 152, and a first switching module 50. The TIA 11 is connected to the signal input terminal IN through the first feedback unit 151, and the PGA 12 is connected to the TIA 11 through the second feedback unit 152. The first switching module 50 connects the DAC 40 and the control input terminal CTL, and has a first output terminal and a second output terminal. The first output terminal is electrically connected to the first feedback unit 151, and the second output terminal is electrically connected to the second feedback unit 152.

[0031] When the control signal is at the first value, the first switching module 50 outputs the analog interference signal to the first feedback unit 151 , and the first feedback unit 151 eliminates the analog interference signal from the original input signal and outputs the original input signal after the interference is eliminated to the TIA 11 .

[0032] In another case, when the control signal is the second value, the first switching module 50 outputs the analog interference signal to the second feedback unit 152 , the second feedback unit 152 eliminates the analog interference signal from the original input signal received by the TIA, and outputs the original input signal after the interference is eliminated to the PGA 12 .

[0033] In this embodiment, the first switching module 50 provides a selection mechanism for the feedback point of the analog interference signal, and the negative feedback can be input before or after the TIA.

[0034] See also Figure 6 In the fourth embodiment of the present invention, the radar processing system further includes a control input terminal CTL. The AFE processor 10 includes a TIA 11, a PGA 12, a HPF 14, a first feedback unit 151, a second feedback unit 152, a first switching module 50, and a second switching module 16. The first switching module 50 is connected to the DAC 40 and the control input terminal CTL, and has a first output terminal and a second output terminal. The TIA 11 is electrically connected to the signal input terminal IN through the first feedback unit 151. The first feedback unit 151 is also connected to the first output terminal of the first switching module 50. The HPF 14 is electrically connected to the TIA 11, and is used to filter the original input signal received from the TIA 11. The second feedback unit 152 is electrically connected to the second output terminal of the first switching module 50. The second switching module 16 is electrically connected to the control input terminal CTL, and has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is connected to the TIA 11, the second input terminal is connected to the HPF 14, and the output terminal is connected to the second feedback unit 152. The PGA 12 is electrically connected between the second feedback unit 152 and the ADC 20 .

[0035] Based on the above connection mode of this embodiment, the working process of the radar signal processing system is further described below.

[0036] When the control signal is the first value, the first switching module 50 outputs the analog interference signal to the first feedback unit 151. The first feedback unit 151 eliminates the analog interference signal from the original input signal, and outputs the original input signal after the interference is eliminated to the TIA 11. The second switching module 16 outputs the original input signal after the interference is eliminated from the TIA 11 to the second feedback unit 152. The second feedback unit 152 transmits the original input signal after the interference is eliminated to the PGA 12.

[0037] When the control signal is the second value, the first switching module 50 outputs the analog interference signal to the second feedback unit 152. TIA 11 receives the original input signal through the first feedback unit 151. HPF 14 filters the original input signal. The second switching module 16 outputs the filtered original input signal to the second feedback unit 152. The second feedback unit 152 eliminates the analog interference signal from the filtered original input signal, and outputs the original input signal after the interference is eliminated to PGA 12.

[0038] In this embodiment, the AFE processor 10 switches between two different processing paths according to the control signal. The first switching module 50 determines which of the first feedback unit 151 (before the TIA 11) and the second feedback unit 152 (after the HPF 14) outputs the analog interference signal. In this way, the feedback unit that receives the analog interference signal performs interference cancellation, while the other feedback unit simply passes the received input signal to the next unit. The second switching module 16 determines whether the original input signal is filtered by the HPF 14. When the control signal is a first value, the analog interference signal is output by the first switching module 50 to the first feedback unit 151, and the original input signal after interference cancellation output from the TIA 11 is directly output to the second feedback unit 152 bypassing the HPF 14. When the control signal is a second value, the analog interference signal is output by the first switching module 50 to the second feedback unit 152. The TIA 11 receives the original input signal without interference cancellation through the first feedback unit 151, and after filtering by the HPF 14, the analog interference signal is cancelled by the second feedback unit 152.

[0039] See also Figure 7 , the ADC 20 of the radar processing system of the present invention includes a sigma-delta modulator (SDM) 21 and a decimation filter 22. The sigma-delta modulator 21 is electrically connected to the AFE processor 10, and is used to generate an initial digital signal according to an analog input signal. The decimation filter 22 is electrically connected to the sigma-delta modulator 21, and is used to sample the initial digital signal and generate a digital input signal. Preferably, the AIC 30 is installed on a digital signal processor (DSP) 3.

[0040] The DAC 40 may include an interpolator 41, a delta-sigma modulator (SDM) 42, and a filter 43. The interpolator 41 is electrically connected to the AIC 30 for receiving a digital interference signal. The delta-sigma modulator 42 is electrically connected to the interpolator 41. The filter 43 is electrically connected between the delta-sigma modulator 42 and the AFE processor 10.

[0041] In one embodiment, the radar signal processing system further includes an amplifier 60 , wherein the DAC 40 is connected to the feedback unit 13 , the first feedback unit 151 or the second feedback unit 152 through the amplifier 60 .

[0042] Of course, the present invention may have many other embodiments. Without departing from the spirit and essence of the present invention, those skilled in the art may make various corresponding changes and modifications based on the present invention, but these corresponding changes and modifications should all fall within the scope of protection of the claims attached to the present invention.

Claims

1. A radar signal processing system with a self-interference elimination function, the radar signal processing system receiving an original input signal through a receiving antenna, characterized in that: include: a signal input terminal, electrically connected to the receiving antenna, and configured to receive the original input signal; an analog front-end processor, electrically connected to the signal input terminal, for performing front-end processing according to the original input signal and generating an analog input signal; an analog-to-digital converter, electrically connected to the analog front-end processor, for converting the analog input signal into a digital input signal; an adaptive interference canceller, electrically connected to the analog-to-digital converter, for performing adaptive interference cancellation processing on the digital input signal and generating a digital interference signal; a digital-to-analog converter, electrically connected to the adaptive interference canceller, for converting the digital interference signal into an analog interference signal, and outputting the analog interference signal to the analog front-end processor; A control input terminal, used to receive a control signal; wherein, The analog front-end processor eliminates the analog interference signal from the original input signal when performing the front-end processing, and the analog front-end processor includes: a transimpedance amplifier, electrically connected to the signal input terminal, and configured to receive the original input signal; a programmable gain amplifier electrically connected between the transimpedance amplifier and the analog-to-digital converter; wherein the original input signal is converted into the analog input signal by the transimpedance amplifier and the programmable gain amplifier, and the analog input signal is output from the programmable gain amplifier to the analog-to-digital converter; a first feedback unit connected between the transimpedance amplifier and the signal input terminal; a second feedback unit connected between the programmable gain amplifier and the transimpedance amplifier; a first switching module, connected to the digital-to-analog converter and the control input terminal, and having a first output terminal and a second output terminal; wherein the first output terminal is electrically connected to the first feedback unit, and the second output terminal is electrically connected to the second feedback unit; When the control signal is a first value, the first switching module outputs the analog interference signal to the first feedback unit, the first feedback unit eliminates the analog interference signal from the original input signal, and outputs the original input signal after the interference is eliminated to the transimpedance amplifier; When the control signal is a second value, the first switching module outputs the analog interference signal to the second feedback unit, the second feedback unit eliminates the analog interference signal from the original input signal received by the transimpedance amplifier, and outputs the original input signal after interference elimination to the programmable gain amplifier.

2. The radar signal processing system with self-interference elimination function as claimed in claim 1, characterized in that: The analog front end processor comprises: a high-pass filter, electrically connected to the transimpedance amplifier, for filtering the original input signal; a second switching module, electrically connected to the control input terminal, and having a first input terminal, a second input terminal and an output terminal; wherein the first input terminal is connected to the transimpedance amplifier, the second input terminal is connected to the high-pass filter, and the output terminal is connected to the second feedback unit; wherein, When the control signal is a first value, the second switching module outputs the original input signal after interference elimination from the transimpedance amplifier to the second feedback unit, and the second feedback unit transmits the original input signal after interference elimination to the programmable gain amplifier; When the control signal is a second value, the transimpedance amplifier receives the original input signal through the first feedback unit, the high-pass filter filters the original input signal, the second switching module outputs the filtered original input signal to the second feedback unit, the second feedback unit eliminates the analog interference signal from the filtered original input signal, and outputs the original input signal after interference elimination to the programmable gain amplifier.

3. The radar signal processing system with self-interference elimination function as claimed in claim 1, characterized in that: The analog-to-digital converter comprises: a delta-sigma modulator, electrically connected to the analog front-end processor, and configured to generate an initial digital signal according to the analog input signal; A decimation filter is electrically connected to the delta-sigma modulator and is used to sample the initial digital signal and generate the digital input signal.

4. The radar signal processing system with self-interference elimination function as claimed in claim 1, characterized in that: The digital-to-analog converter comprises: an interpolator, electrically connected to the adaptive interference canceller, and configured to receive the digital interference signal; a delta-sigma modulator electrically connected to the interpolator; and A filter is electrically connected between the delta-sigma modulator and the analog front-end processor.

5. The radar signal processing system with self-interference elimination function as claimed in claim 1, characterized in that: The adaptive interference canceller is implemented in a digital signal processor.

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