A method for moving large-scale continuous data

Abstract

The present invention discloses a method for supporting large-scale continuous data migration, comprising: when a large amount of data migration mode is turned on, sending a read request to a first data storage space according to the starting address of the source address of the read / write operation; when receiving a message that the source address of the read / write operation responded by the first data storage space according to the read request is in an idle state, sending a write request to a second data storage space according to the starting address of the destination address of the read / write operation; when receiving a message that the starting address of the destination address of the read / write operation responded by the second data storage space according to the write request is in an idle state, migrating data from the source address of the read / write operation to the second data storage space by byte, and each time a data is migrated, the address is incremented until the address of the migrated data is incremented from the starting address of the source address to the ending address, and the data migration is terminated. The efficiency of DMA continuous data migration is effectively improved.

Description

Technical Field

[0001] The invention belongs to the field of data transmission, and in particular relates to a method for supporting the migration of large-scale continuous data. Background Art

[0002] In recent years, ARM embedded systems have been continuously developed and have been applied to various fields such as large databases, image processing, scientific computing, and network services. The emergence of System on a Programmable Chip (SoPC) has made the performance of embedded systems continue to improve, the processing power has become stronger, and IP core reuse technology has become more and more important. At the same time, the amount of data interaction in the system has greatly increased. The data interaction between the system memory and external devices not only has a large amount of data but also has higher and higher requirements for data transmission speed. In this process, a large number of frequent read or write operations are required, which puts higher requirements on the data transmission capacity of the system. The data transmission capacity has gradually become one of the key factors determining the performance of the entire system. With the rapid development of the Internet, the amount of information that people can obtain is increasing, and the requirements for data processing and storage rates are also increasing. Among them, the DMA method is used to provide high-speed data transmission between peripherals and memories and between memories, which can realize data transmission from memory to peripherals, peripherals to memory, and memory to memory.

[0003] In the prior art, the number of bytes that can be moved continuously in a DMA transfer request is limited, and the maximum number of bytes to be transferred is limited by the number of frames in a block, the number of rows in a frame, and the number of bytes in a row in the DMA configuration. This is because, whether in frame transfer or row transfer mode, the row index and frame index values ​​need to be considered when DMA is moving data, and the number of bits of the row index and frame index are both fixed values, resulting in low efficiency of DMA continuous data movement. Therefore, a method for moving large-scale continuous data is urgently needed. Summary of the invention

[0004] In view of the above technical problems, the present invention provides a method for supporting large-scale continuous data migration, which effectively improves the efficiency of continuous data migration.

[0005] The technical solution adopted by the present invention to solve the technical problem is:

[0006] A method for supporting large-scale continuous data movement is provided. Four 32-bit registers are added to a DMA logic channel. The first register is used to control the opening of a large-scale data movement mode. The second register is used to define the starting address of the source address of the read and write operation. The third register is used to define the ending address of the source address of the read and write operation. The fourth register is used to define the starting address of the destination address of the read and write operation. The method includes the following steps:

[0007] Step S100: when it is detected that the first register controls the large amount of data moving mode to be turned on, a read request is sent to the first data storage space according to the starting address of the source address of the read and write operation defined by the second register;

[0008] Step S200: upon receiving a message that the source address of the read / write operation in response to the read request by the first data storage space is in an idle state, sending a write request to the second data storage space according to the start address of the destination address of the read / write operation defined by the fourth register;

[0009] Step S300: When a message is received that the starting address of the destination address of the read / write operation in response to the write request is idle in the second data storage space, data is moved byte by byte from the source address of the read / write operation to the second data storage space, and the address is incremented each time a data is moved until the address of the moved data increases from the starting address of the source address to the ending address of the source address defined by the third register, and the data movement is completed.

[0010] Preferably, step S300 includes:

[0011] Step S310: upon receiving a message that the starting address of the destination address of the read / write operation in response to the write request of the second data storage space is in an idle state, data is moved byte by byte from the source address of the read / write operation;

[0012] Step S320: Each time a piece of data is moved, the address is incremented, and the moved data is temporarily stored in the data cache space;

[0013] Step S330: when the data cache space is not empty, write the data in the data cache space into the second data storage space until the address of the moved data increases from the starting address of the source address to the ending address of the source address defined by the third register to end the data movement.

[0014] Preferably, step S320 further includes: when each data satisfying a preset bit is moved, a counter is incremented by 1.

[0015] The above-mentioned method for supporting large-scale continuous data movement enables DMA to move a large amount of continuous data in one transfer request, solving the problem in the prior art that the number of continuous bytes of data moved in one DMA transfer request is limited, resulting in low efficiency of DMA continuous data movement. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flowchart of a method for moving large-scale continuous data in one embodiment of the present invention;

[0017] Figure 2 The present invention is a flowchart of an embodiment of a method for supporting large-scale continuous data migration. DETAILED DESCRIPTION

[0018] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings.

[0019] In one embodiment, Figure 1 As shown, a method for supporting large-scale continuous data movement is provided. Four 32-bit registers are added to the DMA. The first register is used to control the opening of the large-scale data movement mode. The second register is used to define the starting address of the source address of the read and write operation. The third register is used to define the ending address of the source address of the read and write operation. The fourth register is used to define the starting address of the destination address of the read and write operation. The method includes the following steps:

[0020] Step S100: when it is detected that the first register controls the large amount of data moving mode to be turned on, a read request is sent to the first data storage space according to the starting address of the source address of the read and write operation defined by the second register;

[0021] Step S200: upon receiving a message that the source address of the read / write operation in response to the read request by the first data storage space is in an idle state, sending a write request to the second data storage space according to the start address of the destination address of the read / write operation defined by the fourth register;

[0022] Step S300: When a message is received that the starting address of the destination address of the read / write operation in response to the write request is idle in the second data storage space, data is moved byte by byte from the source address of the read / write operation to the second data storage space, and the address is incremented each time a data is moved until the address of the moved data increases from the starting address of the source address to the ending address of the source address defined by the third register, and the data movement is completed.

[0023] Specifically, when the user turns on the large-scale continuous data movement mode, inputs the starting address, ending address and starting address of the source address, the starting address and ending address of the source address correspond to the first data storage space, and the starting address of the destination address corresponds to the second data storage space. DMA sends a read request to the first data storage space and a write request to the second data storage space respectively. When the first data storage space and the second data storage space are both in space state, DMA will start to move data byte by byte from the starting address of the source address and write it to the destination address. In this way, it reads and writes at the same time, and performs a large amount of continuous data movement in a short time. Each time a data is moved, the address increments. When the source address increases from the starting address to the ending address, DMA will end data reading.

[0024] The DMA of the existing inventions all need to configure 8 parameter words, but in the present invention, only 4 registers need to be configured to realize the movement of a large amount of continuous data, reducing power consumption. In the present invention, only one read and write request is needed to realize the movement of a large amount of continuous data, and the number of read and write requests is reduced, reducing network bandwidth consumption. The speed of moving continuous data is faster, improving data movement efficiency.

[0025] In one embodiment, step S300 includes:

[0026] Step S310: upon receiving a message that the starting address of the destination address of the read / write operation in response to the write request of the second data storage space is in an idle state, data is moved byte by byte from the source address of the read / write operation;

[0027] Step S320: Each time a piece of data is moved, the address is incremented, and the moved data is temporarily stored in the data cache space;

[0028] Step S330: when the data cache space is not empty, write the data in the data cache space into the second data storage space until the address of the moved data increases from the starting address of the source address to the ending address of the source address defined by the third register to end the data movement.

[0029] Furthermore, step S320 also includes: when each data satisfying a preset bit is moved, the counter is incremented by 1.

[0030] Specifically, configuring the counter can facilitate the calculation of the total amount of data transferred within the DMA.

[0031] In a detailed example, DMA0 with a data bit width of 256 bits is used for data movement, the starting address of the source address is configured as 0x70000000, the ending address is 0x7000FFFF, the destination address is 0x74000000, and a large amount of continuous data movement mode is enabled.

[0032] like Figure 2 As shown in the figure, DMA reads data from 0x70000000. Each time a byte is read, the address increases. When the read data meets 256 bits, the counter starts to add 1, and the moved data is temporarily stored in the data cache space, and so on. When the data cache space is not empty, DMA will start to write the data in the data cache space to 0x7000FFFF. From 0x70000000 to 0x7000FFFF, the counter counts 0x7FF in total, and the transmitted data is 0x7ff x256Bit.

[0033] The present invention provides a method for moving large-scale continuous data, which can realize large-scale continuous data moving by configuring only a small number of registers, reducing power consumption; reducing the number of read and write requests, reducing network bandwidth consumption; moving continuous data faster, improving data moving efficiency. It is used to solve the problem in the prior art that the number of continuous bytes moved in a DMA transmission request is limited, resulting in low efficiency of DMA continuous data moving, improve the efficiency of continuous data moving, and reduce network bandwidth consumption.

[0034] The above is a detailed introduction to a method for moving large-scale continuous data provided by the present invention. This article uses specific examples to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A method for moving large-scale continuous data, characterized in that: Four 32-bit registers are added to the DMA logic channel, the first register is used to control the opening of the large-scale data moving mode, the second register is used to define the starting address of the source address of the read and write operation, the third register is used to define the ending address of the source address of the read and write operation, and the fourth register is used to define the starting address of the destination address of the read and write operation. The method includes the following steps: Step S100: when it is detected that the first register controls the large amount of data moving mode to be turned on, sending a read request to the first data storage space according to the starting address of the source address of the read and write operation defined by the second register; Step S200: upon receiving a message that the source address of the read / write operation is in an idle state in response to the read request from the first data storage space, sending a write request to the second data storage space according to the start address of the destination address of the read / write operation defined by the fourth register; Step S300: upon receiving a message that the starting address of the destination address of the read / write operation in response to the write request is in an idle state, data is moved byte by byte from the source address of the read / write operation to the second data storage space, and the address is incremented each time a data is moved until the address of the moved data is incremented from the starting address of the source address to the ending address of the source address defined by the third register, and the data movement is terminated; Step S300 includes: Step S310: upon receiving a message that the starting address of the destination address of the read / write operation in response to the write request by the second data storage space is in an idle state, moving data byte by byte from the source address of the read / write operation; Step S320: each time a piece of data is moved, the address is incremented, and the moved data is temporarily stored in the data cache space; Step S320 also includes: each time data that meets the preset bit is moved, the counter is incremented by 1; Step S330: When the data cache space is in a non-empty state, the data in the data cache space is written into the second data storage space until the address of the moved data increases from the starting address of the source address to the ending address of the source address defined by the third register to end the data movement.

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