Structural feature patterning method and exposure mask for 3D storage device

Abstract

The present application discloses a method for patterning structural features of a 3D storage device and an exposure mask, wherein the structural features have ends. The exposure mask comprises: a substrate; and a mask pattern located on the substrate, wherein the mask pattern comprises a feature pattern and a sub-resolution auxiliary pattern in contact with the feature pattern, wherein the feature pattern corresponds to a feature structure of a storage device to be prepared, and the sub-resolution auxiliary pattern is in contact with at least part of at least one end of the feature pattern and is arranged around the end to optimize the end shape of the feature structure. In a 3D storage device, the structural features obtained by using the exposure mask can improve storage density and reliability due to the optimization of the end shape.

Description

Technical Field

[0001] The present invention relates to a memory manufacturing technology, and more particularly, to a structural feature patterning method and an exposure mask for a 3D memory device. Background Art

[0002] The improvement of storage density of memory devices is closely related to the progress of semiconductor manufacturing process. As the feature size of semiconductor manufacturing process becomes smaller and smaller, the storage density of memory devices becomes higher and higher. In order to further improve the storage density, memory devices with three-dimensional structures (i.e., 3D memory devices) have been developed. 3D memory devices include multiple memory cells stacked in a vertical direction, which can multiply the integration density on a unit area of ​​the wafer and reduce the cost.

[0003] In the manufacturing method of the 3D memory, multiple patterning processes are used to form the channel holes, gate line gaps, conductive channels, word lines, and bit line structural features of the 3D memory. In the patterning process, a mask pattern is transferred to a photoresist layer by a photolithography process to form a photoresist pattern, and an etching process is used to transfer the photoresist pattern to a semiconductor layer, a conductive layer, and / or an insulating layer, thereby forming a structural feature. However, due to the diffraction effect of the optical system, there is a difference between the mask pattern and the photoresist pattern. Optical proximity correction (OPC) can be performed in the design of the mask pattern, wherein a calculation method is used to design the mask pattern to compensate for the diffraction effect of the optical system. As the size of the device structural features is reduced to a critical size, the device structural features are increasingly affected by the optical diffraction effect. The optical proximity correction, for example, includes designing sub-resolution assist features (SRAF) in the vicinity of the device structural pattern in the mask pattern so that the corresponding photoresist pattern meets the requirements of the lithography process window. The pattern size of SRAF is close to the imaging resolution of the lithography system. It diffracts light to change the local light intensity distribution, but it will not be transferred to the photoresist under suitable lithography conditions.

[0004] However, when using a mask pattern of the same size, changing wet immersion etching to dry etching in order to reduce costs will cause the size of the photoresist pattern to change, affecting the storage density and reliability of the 3D memory device.

[0005] It is expected that the patterning methods of 3D memory devices can be further improved, and the shapes of device structural features can be optimized using SRAF to improve the storage density and reliability of 3D memory devices. Summary of the invention

[0006] The object of the present invention is to provide a method for patterning structural features of a 3D storage device and an exposure mask, wherein an L-shaped first sub-resolution auxiliary pattern is added to the corners of the opening ends of the mask pattern to increase the curvature radius of the ends, thereby obtaining device structural features with optimized shape.

[0007] According to one aspect of the present invention, there is provided an exposure mask for a 3D memory device, comprising: a substrate; and a mask pattern located on the substrate, the mask pattern comprising a feature pattern and a first sub-resolution auxiliary pattern in contact with the feature pattern, wherein the feature pattern corresponds to a feature structure of a memory device to be prepared, and the first sub-resolution auxiliary pattern is in contact with at least a portion of at least one end of the feature pattern and is disposed around the end.

[0008] Optionally, the characteristic pattern includes a middle portion and at least one end portion, the end portion is connected to the middle portion, and the end portion includes at least two corners.

[0009] Optionally, the first sub-resolution auxiliary patterns include at least two, and the first sub-resolution auxiliary patterns are in contact with at least a portion of an end corner of the characteristic pattern.

[0010] Optionally, the characteristic pattern includes an end portion, the end portion includes two corners, and each corner is correspondingly provided with a first sub-resolution auxiliary pattern having a bent structure and arranged around the corner.

[0011] Optionally, each of the first sub-resolution auxiliary patterns includes two interconnected strip patterns, and the two strip patterns are respectively parallel to two sides of the corresponding corner.

[0012] Optionally, the first sub-resolution auxiliary pattern includes a plurality of strip patterns arranged in one-to-one correspondence with the sides of the end of the characteristic pattern, and the plurality of strip patterns are connected together to be arranged around the end of the characteristic pattern.

[0013] Optionally, the first sub-resolution auxiliary pattern includes a stripe pattern parallel to one side of two corners, and the stripe pattern is connected to the side corresponding to the end of the characteristic pattern.

[0014] Optionally, the characteristic pattern includes a plurality of end portions, which are distributed in an array-like manner at intervals on two sides of the middle portion in the length direction and are respectively connected to the middle portion.

[0015] Optionally, each of the end portions is provided with a first sub-resolution auxiliary pattern surrounding the end portion and connected to the end portion.

[0016] Optionally, the first sub-resolution auxiliary pattern is connected to at least a portion of the middle portion adjacent to the end portion.

[0017] Optionally, it further includes: a plurality of second sub-resolution auxiliary graphics, wherein the second sub-resolution auxiliary graphics are respectively located between two adjacent first sub-resolution auxiliary graphics.

[0018] Optionally, it further comprises: a plurality of third sub-resolution auxiliary patterns, wherein the third sub-resolution auxiliary patterns are respectively located on a side of the second sub-resolution auxiliary pattern away from the characteristic pattern.

[0019] Optionally, a width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system.

[0020] Optionally, the feature pattern includes at least one selected from an opening and a stripe in the mask layer.

[0021] Optionally, the side of the middle part of the characteristic pattern is a fold line to obtain a width that varies along the length direction of the characteristic pattern.

[0022] Optionally, the shape of the end of the feature pattern of the photoresist pattern corresponding to the mask pattern corresponds to the shape of the end of the structural feature.

[0023] Optionally, the shape of the end of the characteristic figure of the photoresist pattern is any one selected from a semicircle and an arc.

[0024] Optionally, the widths of the end portions and the middle portions of the characteristic figures of the photoresist pattern are substantially equal.

[0025] According to another aspect of the present invention, a method for patterning structural features of a 3D memory device is provided, comprising: forming a photoresist layer on a semiconductor structure, the semiconductor structure comprising a substrate, a sacrificial stack or a gate stack; using the aforementioned exposure mask, exposing and developing the photoresist layer to form a photoresist pattern; etching the semiconductor structure through the photoresist pattern to form structural features of the 3D memory device, wherein the structural features include gate line gaps, top selection gate patterns, and at least one of other openings and strips in the 3D memory.

[0026] According to another aspect of the present invention, a 3D memory device is provided, comprising: a gate stack structure, the gate stack structure comprising alternately stacked interlayer insulating layers and gate conductor layers; a plurality of channel pillars, the channel pillars penetrating the gate stack structure; a gate line gap penetrating the stack structure to separate at least a portion of the stack structure; wherein the gate stack structure is etched using a photoresist pattern formed by the aforementioned exposure mask to form the gate line gap, an end of the gate line gap is located in the stack structure, and a radius of curvature of the end of the gate line gap is greater than a width of the gate line gap, so that the end of the gate line gap is smoother.

[0027] According to an exposure mask of an embodiment of the present invention, the mask pattern includes a feature pattern corresponding to the structural feature and a first sub-resolution auxiliary pattern connected to the feature pattern, wherein the first sub-resolution auxiliary pattern at least partially surrounds the end corners of the feature pattern and contacts a portion of the end of the feature pattern to optimize the end shape of the feature pattern. In the photolithography process, the mask pattern of the exposure mask is transferred to the photoresist layer to form a photoresist pattern, and in the etching process, the photoresist pattern is transferred to the semiconductor structure to form a structural feature. The pattern design of the exposure mask includes optimizing the shape of the first sub-resolution auxiliary pattern so that when immersion lithography is replaced by dry lithography, the structural feature can still obtain a smooth end while maintaining the critical size.

[0028] In a 3D memory device, the gate line gap or top selection gate pattern obtained by using the exposure mask can easily remove excess conductive material due to the optimized end shape and the end curvature radius being greater than the width of the middle portion, thereby improving storage density and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.

[0030] Figure 1a and 1b The circuit diagram and structural schematic diagram of a memory cell string of a 3D memory device are shown respectively.

[0031] Figure 2a and 2b A perspective view and a top view respectively show a portion of the structure of a 3D memory device.

[0032] Figure 3a and Figure 3b A gate line gap mask pattern used in a 3D memory device manufacturing method using immersion lithography and dry lithography according to a comparative example is shown.

[0033] Figure 3c and Figure 3dShows the use of Figure 3a and Figure 3b The mask pattern shown exposes a photoresist pattern that varies with the shape of the critical dimension.

[0034] Figure 4 FIG. 1 shows a gate line gap mask pattern used in a method for manufacturing a 3D memory device according to a first embodiment of the present invention.

[0035] Figure 5 Shows the use of Figure 3a and Figure 4 The mask pattern shown exposes a photoresist pattern that varies with the shape of the critical dimension.

[0036] Figure 6 The design process of the gate line gap mask pattern used in the 3D memory device manufacturing method according to the first embodiment of the present invention is shown.

[0037] Figure 7 FIG. 1 shows a gate line gap mask pattern used in a method for manufacturing a 3D memory device according to a second embodiment of the present invention.

[0038] Figure 8 FIG. 1 shows a gate line gap mask pattern used in a method for manufacturing a 3D memory device according to a third embodiment of the present invention.

[0039] Fig. 9 A top selection gate mask pattern used in a method for manufacturing a 3D memory device according to a fourth embodiment of the present invention is shown.

[0040] Fig.10 A photoresist pattern of a top selection gate used in a method for manufacturing a 3D memory device according to a fourth embodiment of the present invention is shown.

[0041] Fig.11 A top selection gate mask pattern used in a method for manufacturing a 3D memory device according to a fifth embodiment of the present invention is shown. DETAILED DESCRIPTION

[0042] The present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0043] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0044] If the purpose is to describe the situation of being directly on another layer or another area, this article will use the expression "directly on..." or "on... and adjacent to...".

[0045] In this application, the term "semiconductor structure" refers to the entire semiconductor structure formed in the various steps of manufacturing a memory device, including all layers or regions that have been formed. Many specific details of the present invention, such as the structure, materials, dimensions, processing techniques and technologies of the device are described below to facilitate a clearer understanding of the present invention. However, as can be appreciated by those skilled in the art, the present invention may be implemented without following these specific details.

[0046] In a 3D memory device, a stacked structure is used to provide gate conductors of a selection transistor and a storage transistor, and a channel column penetrating the stacked structure is used to provide a channel region of a transistor and a storage transistor. In the process of forming a gate stack structure, a sacrificial stack structure including a plurality of sacrificial layers and a plurality of interlayer insulating layers is first formed, and then a gate line slit (GLS) penetrating the sacrificial stack structure is formed. Further, the sacrificial layer is removed by etching the gate line slit and a conductive material is deposited to form a gate conductor to replace the sacrificial layer, thereby forming a gate stack structure.

[0047] The inventor of the present application has noticed that as the storage density of 3D memory devices increases, the width of the gate line gap is getting closer and closer to the critical dimension (CD). After forming the gate conductor, it is necessary to remove the conductive material in the gate line gap. However, conductive material may still remain at the end of the gate line gap, which may cause the gates of the storage transistor and the selection transistor to short-circuit and fail. It is necessary to improve the end shape of the gate line gap to improve the device yield and reliability. In the case where the adopted mask pattern includes a feature pattern corresponding to the structural feature and a sub-resolution auxiliary pattern adjacent to the feature pattern, the sub-resolution auxiliary pattern at least partially surrounds the end corners of the feature pattern to improve the roundness of the end of the structural feature. However, in order to reduce costs, when the wet immersion etching is changed to dry ArF etching, the end of the structural feature will become pointed, and then the gate short circuit problem caused by tungsten residue will occur.

[0048] The present invention may be embodied in various forms, some examples of which will be described below.

[0049] Figure 1a and 1bThe circuit diagram and the structural schematic diagram of the memory cell string of the 3D memory device are respectively shown. The memory cell string shown in this embodiment includes 4 memory cells. It can be understood that the present invention is not limited to this, and the number of memory cells in the memory cell string can be any number, for example, 32, 64, etc.

[0050] like Figure 1a As shown, the first end of the memory cell string 100 is connected to the bit line BL, and the second end is connected to the source line SL. The memory cell string 100 includes a plurality of transistors connected in series between the first end and the second end, including: a first selection transistor Q1, storage transistors M1 to M4, and a second selection transistor Q2. The gate of the first selection transistor Q1 is connected to the string selection line SSL, and the gate of the second selection transistor Q2 is connected to the ground selection line GSL. The gates of the storage transistors M1 to M4 are respectively connected to the corresponding word lines of the word lines WL1 to WL4.

[0051] like Figure 1b As shown, the first selection transistor Q1 and the second selection transistor Q2 of the memory cell string 100 include gate conductors 122 and 123, respectively, and the memory transistors M1 to M4 include gate conductors 121, respectively. The gate conductors 121, 122 and 123 are consistent with the stacking order of the transistors in the memory cell string 100, and adjacent gate conductors are separated from each other by an interlayer insulating layer, thereby forming a gate stack structure. Further, the memory cell string 100 includes a channel column 110. The channel column 110 runs through the gate stack structure. In the middle part of the channel column 110, a tunneling dielectric layer 112, a charge storage layer 113 and a blocking dielectric layer 114 are sandwiched between the gate conductor 121 and the channel region 111, thereby forming the memory transistors M1 to M4. At both ends of the channel column 110, a blocking dielectric layer 114 is sandwiched between the gate conductors 122 and 123 and the channel region 111, thereby forming the first selection transistor Q1 and the second selection transistor Q2.

[0052] In this embodiment, the channel region 111 is composed of, for example, doped polysilicon, the tunnel dielectric layer 112 and the blocking dielectric layer 114 are respectively composed of oxides, such as silicon oxide, the charge storage layer 113 is composed of an insulating layer containing quantum dots or nanocrystals, such as silicon nitride containing metal or semiconductor particles, and the gate conductors 121, 122 and 123 are composed of metals, such as tungsten. The channel region 111 is used to provide a channel region for controlling the selection transistor and the storage transistor, and the doping type of the channel region 111 is the same as that of the selection transistor and the storage transistor. For example, for N-type selection transistors and storage transistors, the channel region 111 can be N-type doped polysilicon.

[0053] In this embodiment, the core of the channel pillar 110 is the channel region 111, and the tunneling dielectric layer 112, the charge storage layer 113 and the blocking dielectric layer 114 form a stacked structure around the sidewalls of the core. In an alternative embodiment, the core of the channel pillar 110 is an additional insulating layer, and the channel region 111, the tunneling dielectric layer 112, the charge storage layer 113 and the blocking dielectric layer 114 form a stacked structure around the core.

[0054] In this embodiment, the first selection transistor Q1 and the second selection transistor Q2, and the memory transistors M1 to M4 use a common channel region 111 and a blocking dielectric layer 114. In the channel pillar 110, the channel region 111 provides source and drain regions and channel regions of multiple transistors. In an alternative embodiment, the semiconductor layer and the blocking dielectric layer of the first selection transistor Q1 and the second selection transistor Q2 and the semiconductor layer and the blocking dielectric layer of the memory transistors M1 to M4 may be formed separately in independent steps.

[0055] In the write operation, the memory cell string 100 uses the FN tunneling efficiency to write data into the selected memory transistors among the memory transistors M1 to M4. Taking the memory transistor M2 as an example, when the source line SL is grounded, the ground selection line GSL is biased to a voltage of approximately zero volts, so that the selection transistor Q2 corresponding to the ground selection line GSL is disconnected, and the string selection line SSL is biased to a high voltage VDD, so that the selection transistor Q1 corresponding to the string selection line SSL is turned on. Further, the bit line BIT2 is grounded, the word line WL2 is biased to a programming voltage VPG, for example, about 20V, and the remaining word lines are biased to a low voltage VPS1. Since only the word line voltage of the selected memory transistor M2 is higher than the tunneling voltage, the electrons in the channel region of the memory transistor M2 reach the charge storage layer 113 via the tunneling dielectric layer 112, thereby converting the data into charge stored in the charge storage layer 113 of the memory transistor M2.

[0056] In the read operation, the memory cell string 100 determines the amount of charge in the charge storage layer according to the conduction state of the selected memory transistors among the memory transistors M1 to M4, thereby obtaining data represented by the amount of charge. Taking the memory transistor M2 as an example, the word line WL2 is biased at the read voltage VRD, and the remaining word lines are biased at the high voltage VPS2. The conduction state of the memory transistor M2 is related to its threshold voltage, that is, it is related to the amount of charge in the charge storage layer, so the data value can be determined according to the conduction state of the memory transistor M2. The memory transistors M1, M3 and M4 are always in the conduction state, so the conduction state of the memory cell string 100 depends on the conduction state of the memory transistor M2. The control circuit determines the conduction state of the memory transistor M2 according to the electrical signals detected on the bit line BL and the source line SL, thereby obtaining the data stored in the memory transistor M2.

[0057] Figure 2aand 2b A perspective view and a top view of a portion of the structure of a 3D memory device are shown respectively. Figure 2a and 2b The various insulating layers in the 3D memory device are not shown.

[0058] The 3D memory device 200 includes a gate stack structure stacked on a substrate 101 and a channel pillar 110 penetrating the gate stack structure. The figure only shows a plurality of gate conductors 120 of the gate stack structure, and the interlayer insulating layer is not shown in the figure. It can be understood that in the gate stack structure, adjacent gate conductors 120 are separated from each other by an interlayer insulating layer. The internal structure of the channel pillar 110 is shown in FIG. Figure 1b The channel pillars 110 are arranged in an array, and the first ends of the plurality of channel pillars 110 in the same column are connected to the same bit line, and the second ends are connected to the substrate 101, and the second ends form a common source connection via the substrate 100. The stacked plurality of gate conductors 120 and the channel pillars 110 extending along the stacking direction together form a plurality of storage transistors and selection transistors.

[0059] The gate line gap 102 penetrates the gate stack structure along the stacking direction. In the process of forming the gate stack structure, the sacrificial layer in the sacrificial stack structure is replaced with the gate conductor of the gate stack structure, and the gate line gap 102 serves as an etching channel for removing the sacrificial layer and a deposition channel for depositing conductive material. After depositing the conductive material, the conductive material in the gate line gap 102 is further removed and filled with insulating material, so that the gate conductors at different levels are isolated from each other. Figure 2b In the illustrated embodiment, a corresponding gate line gap 102 is formed at both ends of each gate conductor 120, and the two gate line gaps 102 are two sections of characteristic patterns extending on the same straight line and separated from each other, and are opened at the side of each gate conductor 120. Since the shape of the gate conductor 120 is complementary to the shape of the gate line gap 102, the gate conductor 120 is H-shaped. In an alternative embodiment, the two gate line gaps 102 in the gate conductor 120 are two sections of characteristic patterns extending parallel to each other and staggered from each other. In another alternative embodiment, each gate conductor 120 only includes a gate line gap located near one side, and there is no gate line gap near the other side. Conductive material may remain at the end of the gate line gap 102, and the storage transistor and the selection transistor located at different levels will fail due to gate short circuit. Preferably, the end of the gate line gap 102 is increased relative to the width of the middle part, so as to reduce the conductive material remaining in the gate line gap 102 as much as possible after the gate stack structure is formed.

[0060] Although not shown in the figure, the 3D memory device 200 may further include other gate line gaps to divide the gate conductor of each layer into a plurality of gate lines. The plurality of gate lines are connected to corresponding bit lines via corresponding conductive channels.

[0061] Figure 3a and Figure 3b A gate line gap mask pattern used in a 3D memory device manufacturing method using immersion lithography and dry lithography according to a comparative example is shown. Figure 3c and Figure 3d Shows the use of Figure 3a and Figure 3b The mask pattern shown exposes a photoresist pattern that varies with the shape of the critical dimension.

[0062] In order to reduce the manufacturing cost of 3D memory devices, the inventors replaced the immersion lithography machine (IMM) with a dry lithography machine (Dry ArF). Since the lithography principles of the two are different, the size of the mask pattern needs to be adjusted to obtain feature structures with the same critical size.

[0063] The exposure mask 10 includes a substrate 11 and a mask pattern located on the substrate 11, the mask pattern includes a characteristic pattern corresponding to the structural feature, and the mask pattern is defined by a mask material formed on the substrate 11 and having different optical properties from the substrate 11 relative to the light source, wherein the substrate 11 is composed of a light-transmitting material, such as glass, and the mask pattern is defined by a mask material of an opaque material, such as chromium or molybdenum silicide. Photoresists can be divided into positive and negative according to the development characteristics, the former dissolving the exposed part in the developer during development, and the latter dissolving the unexposed part in the developer during development. If the structural feature of the device is an opening, it is simply understood that for a positive photoresist, the area of ​​the mask pattern on the substrate 11 is a light-transmitting area, and the area of ​​the non-mask pattern on the substrate 11 is covered by a mask material of an opaque material, thereby defining the mask pattern; for a negative photoresist, the area of ​​the mask pattern on the substrate 11 is covered by a mask material of an opaque material, and the area of ​​the non-mask pattern on the substrate 11 is a light-transmitting area, thereby defining the mask pattern.

[0064] In the comparative example described below, a positive photoresist is used as an etching exposure mask to form a gate line gap of a 3D memory device for illustration.

[0065] refer to Figure 3a and Figure 3b , in immersion lithography ( Figure 3a ) and dry lithography ( Figure 3b ), in order to obtain feature patterns with the same critical dimensions, the mask pattern in dry lithography is adjusted based on the mask pattern in immersion lithography. After the adjustment, the two mask patterns have the same approximate shape but different sizes.

[0066] by Figure 3a The exposure mask 10 is described as an example, and the exposure mask 10 includes a substrate 11 and a mask pattern 12 located on the substrate 11. The substrate 11 and the mask pattern 12 are composed of materials with different optical properties relative to the light source. Taking positive photoresist as an example, the substrate 11 is composed of a light-transmitting material, and the mask pattern 12 is composed of an opaque material.

[0067] The mask pattern 12 includes an opening 13 corresponding to the structural features of the 3D memory. The opening 13 in the mask pattern 12 is a characteristic pattern having a shape substantially the same as that of the gate line gap. The characteristic pattern includes a middle portion 14 and an end portion 15, each of which is rectangular and connected to each other as a whole. The middle portion 14 and the end portion 15 respectively include two side edges extending along the length direction of the characteristic pattern. The two side edges of the middle portion 14 are connected to the corresponding side edges of the end portion 15. The side edges of the middle portion 14 are broken lines to obtain a width that gradually decreases toward the end portion 15. The width of the end portion 15 is greater than the width of the middle portion 14.

[0068] Further, the mask pattern 12 also includes a first sub-resolution auxiliary pattern (i.e., SRAF) 16 adjacent to the corner of the end 15. The light transmittance characteristics of the first sub-resolution auxiliary pattern 16 are the same as the light transmittance characteristics of the feature pattern. In the case where a positive photoresist is used as an etching exposure mask to form a gate line gap of a 3D memory device, both are opening patterns (i.e., light transmittance patterns) in the mask pattern 12. In the mask pattern of this embodiment, the first sub-resolution auxiliary pattern 16 is, for example, two L-shaped openings separated from each other, respectively including a first strip pattern extending along the side of the end 15 and a second strip pattern extending from the top of the end 15, and the first strip pattern and the second strip pattern are connected to each other to form an L-shaped corner. The pattern size of the first sub-resolution auxiliary pattern 16 is close to the imaging resolution of the lithography system. For example, the width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system. Therefore, the first sub-resolution auxiliary pattern 16 diffracts light to change the local light intensity distribution, but will not be transferred into the photoresist under appropriate photolithography conditions.

[0069] However, according to the light intensity distribution diagrams corresponding to the two mask patterns, it can be understood that in dry lithography, the light intensity corresponding to the first sub-resolution auxiliary pattern 26 does not effectively adjust the light intensity of the end portion 25 of the opening 23 .

[0070] Further, refer to Figure 3c, a computational method is used to simulate the photoresist pattern, and the photoresist patterns exposed by the mask patterns of the two methods are placed in the same figure. It can be clearly seen that the ends of the characteristic patterns of the photoresist layer formed in the dry lithography are sharper, which makes it difficult to clean the tungsten material at the ends of the characteristic structure, increasing the probability of gate conductor short circuit.

[0071] Further, Figure 3d The critical dimensions of the characteristic patterns of dry lithography are adjusted to obtain a photoresist pattern exposed by multiple mask patterns with the same radius of curvature as that of immersion lithography. The marking symbols H10-H50 represent different radii of curvature of the opening end of the photoresist pattern when the critical dimensions increase successively (the end with a smaller radius of curvature is sharper). Specifically, H10 is the photoresist pattern of immersion lithography of h1; H20 is the photoresist pattern of dry lithography of h1; H30 is the photoresist pattern of dry lithography of h2; H40 is the photoresist pattern of dry lithography of h3; and H50 is the photoresist pattern of dry lithography of h4. The critical dimensions of h1 to h4 represent the specific critical dimensions during lithography, and the unit is, for example, nm. The critical dimensions of h1 to h4 increase by 10 nm successively, and the radius of curvature of the opening end of the photoresist pattern shown in H20-H50 increases successively.

[0072] The photolithography system includes, for example, a light source, a converging lens, and a projection objective. In the photolithography process, the exposure mask is located between the converging lens and the projection objective. The light source of the photolithography system emits a light beam for exposure, which irradiates the photoresist layer on the surface of the semiconductor structure via the converging lens, the exposure mask 10, and the projection objective. The portion of the photoresist layer corresponding to the opening of the exposure mask is removed in the developer to form a corresponding opening. However, due to the diffraction effect of the optical system, there is a difference between the mask pattern and the photoresist pattern. At this time, a computational method can be used to simulate the photoresist pattern to adjust the photoresist pattern according to the simulation results, thereby obtaining a more suitable structural feature.

[0073] like Figure 3d As shown, as the critical dimension decreases, the curvature radius corresponding to the end of the feature pattern in the photoresist pattern in the dry lithography also decreases accordingly (that is, the end becomes sharper). Accordingly, for the gate line gap formed after performing photolithography and etching using the mask pattern, the curvature radius of the end thereof also decreases as the critical dimension decreases. After the step of forming the gate stack structure, the end of the gate line gap is prone to residual conductive material, causing failure.

[0074] Furthermore, in order to keep the radius of curvature of the ends of the photoresist patterns of immersion lithography and dry lithography basically the same, the critical dimension of dry lithography in the vertical direction needs to be h4 to be equivalent to h1 of immersion lithography, but the critical dimension of h4 is basically not accepted in the process.

[0075] The challenge faced in the manufacturing method of 3D memory devices is to obtain the largest possible end curvature radius while reducing the critical dimension of the gate line gap.

[0076] In the present application, the characteristic structure of the 3D memory device includes, for example, a gate line gap, a top selection gate pattern, and at least one of other openings and stripes in the 3D memory.

[0077] Figure 4 FIG. 1 shows a gate line gap mask pattern used in a method for manufacturing a 3D memory device according to a first embodiment of the present invention. Figure 5 Shows the use of Figure 3a and Figure 4 The mask pattern shown exposes a photoresist pattern that varies with the shape of the critical dimension.

[0078] The exposure mask 30 includes a substrate 11 and a mask pattern 32 on the substrate 11. The substrate 11 and the mask pattern 32 are made of materials with different optical properties relative to the light source. Taking positive photoresist as an example, the substrate 11 is made of a light-transmitting material and the mask pattern 32 is made of a light-impermeable material.

[0079] like Figure 4 As shown, the mask pattern 32 includes an opening 33 corresponding to the structural features of the 3D memory. The opening 33 in the mask pattern 32 is a characteristic pattern with a shape roughly the same as the gate line gap. The characteristic pattern includes a middle portion 34 and an end portion 35, each of which is rectangular and connected to each other as a whole. The middle portion 34 and the end portion 35 respectively include two side edges extending along the length direction of the characteristic pattern. The two side edges of the middle portion 34 are connected to the corresponding side edges of the end portion 35. The side edges of the middle portion 34 are broken lines to obtain a width that gradually decreases toward the end portion 35. The width of the end portion 35 is greater than the width of the middle portion 34.

[0080] Furthermore, the mask pattern 32 further includes a first sub-resolution auxiliary pattern (i.e., SRAF) 36 adjacent to the corner of the end portion 35. The light transmission characteristics of the first sub-resolution auxiliary pattern 36 are the same as the light transmission characteristics of the feature pattern. In the case of using a positive photoresist as an etching exposure mask to form a gate line gap of a 3D memory device, both are opening patterns (i.e., light transmission patterns) in the mask pattern 32.

[0081] In the mask pattern of this embodiment, the first sub-resolution auxiliary pattern 36 is, for example, two L-shaped openings separated from each other, respectively including a first strip pattern extending along the side of the end 35 and a second strip pattern extending from the top of the end 35, the first strip pattern and the second strip pattern are connected to each other to form an L-shaped corner, and the second strip pattern extending along the top of the end 35 has a portion of a connection area with the top of the end 35. The pattern size of the first sub-resolution auxiliary pattern 36 is close to the imaging resolution of the lithography system. For example, the width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system. Therefore, the first sub-resolution auxiliary pattern 36 diffracts light to change the local light intensity distribution, but it will not be transferred to the photoresist under appropriate lithography conditions.

[0082] Figure 5 Shows the use of Figure 4 The photoresist pattern exposed by the mask pattern shown varies with the shape of the critical dimension. Figure 5 In the figure, the symbols H-Dry and H-IMM represent different widths of the opening end of the photoresist pattern when dry lithography and immersion lithography are used respectively with the same critical dimension.

[0083] In the photolithography process, the light source of the photolithography system emits a light beam for exposure, which is irradiated onto the photoresist layer on the surface of the film layer to be etched through the exposure mask 30. The portion of the photoresist layer corresponding to the opening of the exposure mask is removed in the developer to form a corresponding opening. Due to the diffraction effect of the optical system, there is a difference between the mask pattern and the photoresist pattern.

[0084] Computational methods are used to simulate photoresist patterns. Figure 5 As shown, in both methods, the ends of the feature patterns in the mask pattern are rectangular in shape, and the curvature radius of the end shapes of the feature patterns in the photoresist pattern are basically the same, and the curvature radius is greater than the width of the middle part of the feature pattern. Comparing the curves H-Dry and H-IMM, it can be found that under the same critical size, the width of the middle part of the opening of the photoresist pattern formed by dry lithography and immersion lithography is basically consistent, and the width of the end is also basically consistent, and the end still maintains a larger curvature radius, that is, the shape of the end changes from a semicircle to an arc, so, Figure 4 The mask pattern shown can achieve the same critical dimension, and keep the photoresist pattern formed by dry lithography and immersion lithography basically consistent. After the step of forming the gate stack structure, the shape of the opening end of the photoresist pattern is optimized and transferred to the structural features in the etching process, and the end shape of the gate line gap is also optimized accordingly, so that the conductive material can be easily removed from the gate line gap after the gate conductor is formed, so as to improve the yield and reliability of the 3D memory device.

[0085] Further, refer to Figure 5 In the photoresist layer pattern obtained by simulation according to the calculation method, the width of the end and the middle of the characteristic pattern are also substantially equal. Substantially equal in this application means, for example, that the width error between the end and the middle is within a set range.

[0086] Figure 6 The design process of the gate line gap mask pattern used in the 3D memory device manufacturing method according to the first embodiment of the present invention is shown.

[0087] like Figure 6 As shown, firstly, a first sub-resolution auxiliary pattern a and a characteristic pattern b are designed, and the two are combined to obtain a mask pattern c, a calculation method is used to simulate the photoresist pattern according to the mask pattern c, and the characteristic pattern b is adjusted according to the simulated photoresist pattern to obtain a characteristic pattern d, and the characteristic pattern d is combined with the first sub-resolution auxiliary pattern a to obtain a mask pattern e, and a calculation method is used to simulate the photoresist pattern f according to the mask pattern e. If the photoresist pattern f meets the design requirements, the mask pattern e is successful; if the photoresist pattern f does not meet the design requirements, the mask pattern e is unsuccessful and further adjustment of the mask pattern e is required.

[0088] exist Figure 6 In one embodiment shown, in the process of adjusting the mask pattern c, only the feature pattern b is adjusted, and the first sub-resolution auxiliary pattern a is not adjusted. In another embodiment, both the first sub-resolution auxiliary pattern a and the feature pattern b may be adjusted to obtain a suitable mask pattern e. In another embodiment, in order to obtain a more optimized photoresist pattern f, the first sub-resolution auxiliary pattern a and the feature pattern b may be adjusted multiple times. This embodiment only shows a possible situation, and those skilled in the art may make other suitable adjustments to the mask pattern c according to the design purpose.

[0089] Figure 7 The gate line gap mask pattern used in the 3D memory device manufacturing method according to the second embodiment of the present invention is shown. Compared with the mask pattern of the first embodiment, the mask pattern of the second embodiment is in the shape of a "→", which is roughly in the shape of an arrow.

[0090] The exposure mask 40 includes a substrate 11 and a mask pattern 42 on the substrate 11. The substrate 11 and the mask pattern 42 are made of materials with different optical properties relative to the light source. Taking positive photoresist as an example, the substrate 11 is made of a light-transmitting material and the mask pattern 42 is made of a light-impermeable material.

[0091] like Figure 7As shown, the mask pattern 42 includes an opening 43 corresponding to the structural features of the 3D memory. The opening 43 in the mask pattern 42 is a characteristic pattern with a shape roughly the same as the gate line gap. The characteristic pattern includes a middle portion 44 and an end portion 45 connected to each other as a whole. The middle portion 44 and the end portion 45 respectively include two side edges extending along the length direction of the characteristic pattern. The two side edges of the middle portion 44 are connected to the corresponding side edges of the end portion 45. The side edges of the middle portion 44 are broken lines to obtain a width that gradually decreases toward the end portion 45. The width of the end portion 45 is greater than the width of the middle portion 54.

[0092] Further, the mask pattern 42 also includes a first sub-resolution auxiliary pattern (i.e., SRAF) 46 adjacent to the corner of the end 45. The light transmission characteristics of the first sub-resolution auxiliary pattern 46 are the same as the light transmission characteristics of the feature pattern. In the case where a positive photoresist is used as an etching exposure mask to form the gate line gap of the 3D memory device, both are opening patterns (i.e., light transmission patterns) in the mask pattern 42. In the mask pattern of this embodiment, the first sub-resolution auxiliary pattern 46 is, for example, a C-shaped opening formed by connecting two L-shaped openings together, including a first strip pattern and a second strip pattern extending along the two side edges of the end 45, and a third strip pattern extending along the top edge of the end 45, the first strip pattern and the second strip pattern are respectively connected to the third strip pattern to form an L-shaped corner. Among them, the third strip pattern of the first sub-resolution auxiliary pattern 46 is connected to the top edge of the end 45 of the feature pattern.

[0093] The pattern size of the first sub-resolution auxiliary pattern 46 is close to the imaging resolution of the photolithography system. For example, the width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the photolithography system. Therefore, the first sub-resolution auxiliary pattern 46 diffracts light to change the local light intensity distribution, but will not be transferred to the photoresist under appropriate photolithography conditions.

[0094] The photoresist pattern is simulated by a computational method. The photoresist pattern includes an opening corresponding to the opening 43 in the mask pattern 42 and having a different shape. Although the end of the characteristic pattern of the mask pattern is rectangular, the end of the characteristic pattern of the photoresist pattern is a smooth semicircular shape. Under the same critical size, the width of the middle part of the opening of the photoresist pattern formed by dry lithography and immersion lithography is basically consistent, the end width is also basically consistent, and the end still maintains a large radius of curvature. After the step of forming the gate stack structure, the shape optimization of the opening end of the photoresist pattern is transferred to the structural feature in the etching process, and the end shape of the gate line gap is also optimized accordingly, so that it is easy to remove the conductive material from the gate line gap after the gate conductor is formed, so as to improve the yield and reliability of the 3D memory device.

[0095] Figure 8 The gate line gap mask pattern used in the 3D memory device manufacturing method according to the third embodiment of the present invention is shown. Compared with the mask patterns of the first and second embodiments, the mask pattern of the third embodiment is a hook type.

[0096] The exposure mask 50 includes a substrate 11 and a mask pattern 52 on the substrate 11. The substrate 11 and the mask pattern 52 are made of materials with different optical properties relative to the light source. Taking positive photoresist as an example, the substrate 11 is made of a light-transmitting material and the mask pattern 52 is made of a light-impermeable material.

[0097] like Figure 8 As shown, the mask pattern 52 includes an opening 53 corresponding to the structural features of the 3D memory. The opening 53 in the mask pattern 52 is a characteristic pattern with a shape roughly the same as the gate line gap. The characteristic pattern includes a middle portion 54 and an end portion 55 connected to each other as a whole. The middle portion 54 and the end portion 55 respectively include two side edges extending along the length direction of the characteristic pattern. The two side edges of the middle portion 54 are connected to the corresponding side edges of the end portion 55. The side edges of the middle portion 54 are broken lines to obtain a width that gradually decreases toward the end portion 55. The width of the end portion 55 is greater than or equal to the width of the middle portion 54.

[0098] Furthermore, the mask pattern 52 further includes a first sub-resolution auxiliary pattern 56. The first sub-resolution auxiliary pattern 56 is, for example, two L-shaped openings separated from each other, and includes a first strip pattern extending along the side of the end 55 and a second strip pattern extending along the top of the end 55, respectively, the first strip pattern and the second strip pattern are connected to each other to form an L-shaped corner, and the first strip pattern extending along the side of the end 55 has a portion of a connection area with the side of the end 55. The pattern size of the first sub-resolution auxiliary pattern 56 is close to the imaging resolution of the lithography system. For example, the width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system. Therefore, the first sub-resolution auxiliary pattern 56 diffracts light to change the local light intensity distribution, but it itself will not be transferred to the photoresist under suitable lithography conditions.

[0099] The photoresist pattern is simulated by a computational method. The photoresist pattern includes an opening corresponding to the opening 53 in the mask pattern 52 and having a different shape. Under the same critical dimension, the width of the middle part of the opening of the photoresist pattern formed by dry lithography and immersion lithography is basically consistent, the width of the end is also basically consistent, and the end still maintains a large radius of curvature. After the step of forming the gate stack structure, the shape optimization of the opening end of the photoresist pattern is transferred to the structural feature in the etching process, and the end shape of the gate line gap is also optimized accordingly, so that it is easy to remove the conductive material from the gate line gap after the gate conductor is formed, so as to improve the yield and reliability of the 3D memory device.

[0100] Fig. 9 A top selection gate mask pattern used in a method for manufacturing a 3D memory device according to a fourth embodiment of the present invention is shown. Fig.10 The simulated photoresist pattern of the top selection gate used in the 3D memory device manufacturing method of the fourth embodiment of the present invention is shown. In the manufacturing method of the 3D memory device, the above-mentioned optimization scheme of the mask pattern of the gate line gap can also be used in other etching steps. This embodiment shows the mask pattern of the top selection gate.

[0101] The exposure mask 60 includes a substrate 11 and a mask pattern 62 on the substrate 11. The substrate 11 and the mask pattern 62 are made of materials with different optical properties relative to the light source. Taking positive photoresist as an example, the substrate 11 is made of a light-transmitting material and the mask pattern 62 is made of a light-impermeable material.

[0102] like Fig. 9 As shown, the mask pattern 62 includes an opening 63 corresponding to the structural features of the 3D memory. The opening 63 in the mask pattern 62 is a feature pattern that is substantially the same shape as the top selection gate. The feature pattern includes a middle portion 64 and an end portion 65 that are connected to each other as a whole. The middle portion 64 is a strip-shaped pattern having two side edges extending along the length direction of the feature pattern, and the end portion 65 is a plurality of strip-shaped patterns isolated from each other, which are arranged at intervals along the two side edges of the middle portion 64 and overlap and connect with the side edges of the middle portion 64. The side edges of the opening 63 formed by the middle portion 64 and the end portion 65 extend in a regular fold line shape along the length direction of the feature pattern.

[0103] Further, the mask pattern 62 also includes a first sub-resolution auxiliary pattern 66. The first sub-resolution auxiliary pattern 66 is, for example, a plurality of U-shaped openings separated from each other, and includes a first pattern extending along the side of the end 65 and two second patterns extending along the two top edges of the end 65, respectively. The first pattern and the second pattern are connected to each other to form a U-shaped pattern, and the first sub-resolution auxiliary pattern 66 is in contact with and connected to the side and two top edges of the end 65, and the first sub-resolution auxiliary pattern 66 is connected to a part of the side of the middle part 64 adjacent to the end 65. The pattern size of the first sub-resolution auxiliary pattern 66 is close to the imaging resolution of the lithography system. For example, the width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system. Therefore, the first sub-resolution auxiliary pattern 66 diffracts light to change the local light intensity distribution, but it will not be transferred to the photoresist under suitable lithography conditions.

[0104] Further, refer to Fig.10 , using computational methods to simulate the photoresist pattern and perform actual photolithography and etching. The photoresist pattern is generally wavy and includes openings that correspond to the openings 63 in the mask pattern 62 and have different shapes. Fig.10 In the figure shown, the photoresist pattern formed by the mask pattern corresponding to the top selection gate and the characteristic structure in the device formed by lithography and etching also have a wavy shape, and the arc edge of the wave is relatively smooth, which is convenient for subsequent steps and can improve the yield and reliability of the 3D storage device.

[0105] Fig.11 The top selection gate mask pattern used in the 3D memory device manufacturing method of the fifth embodiment of the present invention is shown. Compared with the top selection gate mask pattern of the fourth embodiment, the second sub-resolution auxiliary pattern 77 and the third sub-resolution auxiliary pattern 78 are added, and the pattern of the photoresist layer formed by the mask pattern is further optimized.

[0106] The exposure mask 70 includes a substrate 11 and a mask pattern 72 on the substrate 11. The substrate 11 and the mask pattern 72 are made of materials with different optical properties relative to the light source. For example, using positive photoresist, the substrate 11 is made of a light-transmitting material, and the mask pattern 72 is made of a light-impermeable material.

[0107] like Fig.11 As shown, the mask pattern 72 includes an opening 73 corresponding to the structural features of the 3D memory. The opening 73 in the mask pattern 72 is, for example, Fig. 9 The combination of the opening 63 in the middle and the first sub-resolution auxiliary pattern 66 is wavy.

[0108] Furthermore, the mask pattern 72 further includes a second sub-resolution auxiliary pattern 77 and a third sub-resolution auxiliary pattern 78, which are used to adjust the smoothness of the wavy shape of the opening 73 in the mask pattern. The second sub-resolution auxiliary pattern 77 is, for example, a plurality of strip-shaped openings extending along the length direction of the opening, which are separated from each other and are respectively located between two adjacent protrusions of the wavy opening 73, and the second sub-resolution auxiliary pattern 7 is a certain distance away from the opening 73. The third sub-resolution auxiliary pattern 78 is, for example, two strip-shaped openings extending along the length direction of the opening, which are respectively located on both sides of the opening 73, and the second sub-resolution auxiliary pattern 77 is located between the third sub-resolution auxiliary pattern 78 and the opening 73. The pattern sizes of the second sub-resolution auxiliary pattern 77 and the third sub-resolution auxiliary pattern 78 are close to the imaging resolution of the lithography system. For example, the width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system. Therefore, the second sub-resolution auxiliary pattern 77 and the third sub-resolution auxiliary pattern 78 diffract the light to change the local light intensity distribution, but they themselves will not be transferred to the photoresist under suitable lithography conditions.

[0109] In the embodiments described above, it is described that a gate line gap and a top selection gate of a 3D memory device are formed by using a positive photoresist as an etching exposure mask. However, both the structural features in the 3D memory device and the development characteristics of the photoresist are not limited by a specific embodiment. The structural features of the 3D memory device can be an opening such as a gate line gap or a wavy opening of a top selection gate, a rectangular hole or an elliptical hole, or a strip such as a bit line, which can be collectively referred to as a "structural feature". For different structural features in a 3D memory device, if the line width is close to a critical dimension, the end shape of the structural feature can be optimized by the pattern design method of the present invention. For example, in the case of optimizing the end shape of the bit line, the parasitic capacitance can be reduced and the read and write speed of the memory can be increased.

[0110] In the above-described embodiment, it is described that the shape of the first sub-resolution auxiliary pattern in the exposure mask includes two L-shaped openings separated from each other connected to the ends of the opening, or a concave opening formed by connecting two L-shaped openings together. In an alternative embodiment, the first sub-resolution auxiliary pattern includes a plurality of patterns arranged in one-to-one correspondence with the side edges of the end of the characteristic pattern, and the plurality of patterns are connected together to be arranged around the end of the characteristic pattern. In another alternative embodiment, the first sub-resolution auxiliary pattern can be a pattern with a bent structure around the corner of the characteristic pattern. For example, each first sub-resolution auxiliary pattern includes two interconnected strip patterns, and the two strip patterns are parallel to the two sides of the corresponding corners. For example, the two interconnected strip patterns constitute an inner concave portion close to the characteristic pattern and an outer convex portion away from the characteristic pattern, and the inner concave portion and the outer convex portion respectively include at least two segments of fold lines connected together; or, the inner concave portion and the outer convex portion respectively include a segment of arc line. In another alternative embodiment, a second sub-resolution auxiliary pattern and a third sub-resolution auxiliary pattern can be further added to further optimize the characteristic pattern.

[0111] In the above description, the technical details of the patterning and etching of each layer are not described in detail. However, it should be understood by those skilled in the art that various technical means can be used to form layers, regions, etc. of the desired shape. In addition, in order to form the same structure, those skilled in the art can also design methods that are not completely the same as the methods described above. In addition, although the various embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage.

[0112] The embodiments of the present invention are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present invention. The scope of the present invention is defined by the appended claims and their equivalents. Without departing from the scope of the present invention, those skilled in the art may make various substitutions and modifications, which should all fall within the scope of the present invention.

Claims

1. An exposure mask for a memory device, characterized in that: include: substrate; as well as a mask pattern located on the substrate, the mask pattern comprising a feature pattern and a first sub-resolution auxiliary pattern in contact with the feature pattern, The characteristic pattern corresponds to a characteristic structure of a memory device to be prepared, and the first sub-resolution auxiliary pattern contacts at least a portion of at least one end of the characteristic pattern and is disposed around the end. The system further comprises: a plurality of second sub-resolution auxiliary graphics, wherein the second sub-resolution auxiliary graphics are respectively located between two adjacent first sub-resolution auxiliary graphics.

2. The exposure mask according to claim 1, characterized in that The characteristic pattern includes a middle portion and at least one end portion, wherein the end portion is connected to the middle portion and includes at least two corners.

3. The exposure mask according to claim 2, characterized in that: The first sub-resolution auxiliary patterns include at least two first sub-resolution auxiliary patterns, and the first sub-resolution auxiliary patterns are in contact with at least a portion of an end corner of the characteristic pattern.

4. The exposure mask according to claim 3, characterized in that The characteristic pattern includes an end portion, and the end portion includes two corners. Each of the corners is correspondingly provided with a first sub-resolution auxiliary pattern having a bent structure and arranged around the corner.

5. The exposure mask according to claim 4, characterized in that Each of the first sub-resolution auxiliary patterns includes two interconnected strip patterns, and the two strip patterns are respectively parallel to two sides of the corresponding corner.

6. The exposure mask according to claim 4, characterized in that: The first sub-resolution auxiliary pattern includes a plurality of strip patterns arranged in one-to-one correspondence with the sides of the end of the characteristic pattern, and the plurality of strip patterns are connected together to be arranged around the end of the characteristic pattern.

7. The exposure mask according to claim 6, characterized in that: The first sub-resolution auxiliary pattern includes a stripe pattern parallel to one side of two corners, and the stripe pattern is connected to the side corresponding to the end of the characteristic pattern.

8. The exposure mask according to claim 3, characterized in that: The characteristic pattern includes a plurality of end portions, which are distributed in an array-like manner at intervals on two sides of the middle portion in the length direction and are respectively connected to the middle portion.

9. The exposure mask according to claim 8, characterized in that: Corresponding to each of the end portions, a first sub-resolution auxiliary pattern is disposed which surrounds the end portion and is connected to the end portion.

10. The exposure mask according to claim 9, characterized in that: The first sub-resolution auxiliary pattern is connected to at least a portion of the middle portion adjacent to the end portion.

11. The exposure mask according to claim 10, characterized in that: Also includes: A plurality of third sub-resolution auxiliary patterns, wherein the third sub-resolution auxiliary patterns are respectively located at a side of the second sub-resolution auxiliary pattern away from the characteristic pattern.

12. The exposure mask according to claim 1, characterized in that: The width of the first sub-resolution auxiliary pattern is 1.5 to 2.5 times the imaging resolution of the lithography system.

13. The exposure mask according to claim 1, characterized in that The feature pattern includes at least one selected from an opening and a stripe in the mask layer.

14. The exposure mask according to claim 1, characterized in that The side edges of the middle portion of the characteristic pattern are fold lines to obtain a width that varies along the length direction of the characteristic pattern.

15. The exposure mask according to claim 1, characterized in that: The end shape of the feature pattern of the photoresist pattern corresponding to the mask pattern corresponds to the end shape of the feature structure.

16. The exposure mask according to claim 15, characterized in that: The shape of the end of the characteristic figure of the photoresist pattern is any one selected from a semicircle and an arc.

17. The exposure mask according to claim 15, characterized in that: The widths of the end portions and the middle portion of the characteristic pattern of the photoresist pattern are substantially equal.

18. A method for patterning structural features of a 3D memory device, comprising: forming a photoresist layer on a semiconductor structure, the semiconductor structure comprising a substrate, a sacrificial stack or a gate stack; Using the exposure mask according to any one of claims 1 to 17, exposing and developing the photoresist layer to form a photoresist pattern; etching the semiconductor structure through the photoresist pattern to form the structural features of the 3D memory device, The structural features include at least one of gate line gaps, top selection gate patterns, and other openings and stripes in the 3D memory.

19. A 3D memory device, comprising: A gate stack structure, the gate stack structure comprising alternately stacked interlayer insulating layers and gate conductor layers; A plurality of channel pillars, wherein the channel pillars penetrate the gate stack structure; A gate line gap penetrates the stacked structure and separates at least a portion of the stacked structure; Wherein, the gate stack structure is etched using a photoresist pattern formed by an exposure mask according to any one of claims 1 to 17 to form the gate line gap, the end of the gate line gap is located in the stack structure, and the end curvature radius of the gate line gap is greater than the width of the gate line gap, so that the end of the gate line gap is smoother.

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