Process for metal etching

Abstract

The application discloses a process method for metal etching, which comprises the following steps: step one, forming a metal layer; step two, forming a DARC layer; step three, forming a photoresist pattern; step four, performing aging treatment on an etching cavity of a dry etching machine, which comprises the following steps: providing a wafer dummy with a first dielectric layer, placing the wafer dummy into the etching cavity to perform first etching and thereby forming an aging film formed by etching by-products on the inner side surface of the etching cavity; step five, etching the DARC layer; and step six, placing a product wafer into the etching cavity to perform second etching and thereby forming a metal line. The application can improve the appearance of the metal line and improve the line width stability of the metal line.

Description

TECHNICAL FIELD

[0001] The present application relates to a semiconductor integrated circuit manufacturing method, in particular to a metal etching process method. BACKGROUND

[0002] Metallization is a process of depositing metal thin film on insulating medium layer and subsequent printing pattern to form metal line and integrated circuit hole plug filling in chip manufacturing process, in which metal interconnection is made of metal such as aluminum, copper and other metal lines to transmit electrical signals to different parts of the chip.

[0003] As a medium connecting the underlying device and current path, the stability of the metal line profile and electron line width is very important for the yield and reliability of the product. Unstable preparation process will cause unstable electron line width of the metal, device electrical parameter failure, or low yield, and in severe cases, it may also cause reliability problems.

[0004] In the existing metal etching process method, after the formation of the metal layer, a dielectric antireflection layer (DARC) is formed on the surface of the metal layer, and then a photolithography process is performed to form a photoresist pattern to define the formation area of the metal line.

[0005] Before the metal etching of the same batch of wafers, a wafer dummy coated with photoresist is used to perform seasoning treatment in the etching chamber of the dry etching machine. The seasoning treatment is achieved by etching the wafer dummy. After etching, the etching by-products of the photoresist are polymers, which will deposit on the inner surface of the etching chamber, thereby making the internal environment of the etching chamber conducive to subsequent metal etching.

[0006] After seasoning, the same batch of wafers is subjected to metal etching, and then cleaning.

[0007] In the existing metal line preparation process, due to the relationship of the metal line profile, it is difficult to monitor its physical profile and line width by online measurement, and generally the electron line width is detected by electrical parameter measurement. Therefore, the stability of the electron line width can truly reflect the physical profile of the metal line.

[0008] As shown in Figure 1 is the electron line width distribution diagram of the metal line of each wafer of one batch formed by the existing metal etching process method; the wafer number is shown in the abscissa, a total of 25 wafers, in the actual process, the wafers are transmitted to the etching chamber in the direction from the 25th to the 1st for metal etching. Figure 1The ordinate is the line width of the metal line, and the line width of the metal line is an electron line width detected by an electrical parameter measurement method, rather than a physical line width obtained by an electron photo such as a TEM or SEM photo. As can be seen, the line width of the metal line of the first several wafers shown by the dashed circle 101 is larger and deviates from the target value, and the line width of the metal line of the other wafers is close to the target value, so there is a first piece effect. USL represents the upper specification limit, and LSL represents the lower specification limit. When the line width of the metal line exceeds the USL, a short circuit risk between the metal lines occurs, and a reliability problem occurs.

[0009] As shown in FIG. 1, it is a photo of a metal line formed by a prior art metal etching process. Figure 2 As shown in FIG. 1, it is a photo of a metal line formed by a prior art metal etching process. Figure 2 The metal line 202 and the diffusion barrier layer 201 at the bottom of the metal line 202 and the DARC layer 203 at the top of the metal line 202 are shown in FIG. 2, and it can be seen that the width of the metal line 202 is reduced, that is, smaller than the width of the DARC layer 203 at the top and the diffusion barrier layer 201 at the bottom, so that the metal line 202 has a H-shaped morphology. Due to the influence of the H-shaped morphology, the morphology of aluminum copper cannot be detected, so that the metal line width deviation cannot be detected when it is small, which easily leads to line width deviation failure and electrical parameter failure and low yield caused by thin wire. SUMMARY

[0010] The technical problem to be solved by the present application is to provide a metal etching process, which can improve the morphology of the metal line and improve the line width stability of the metal line.

[0011] To solve the above technical problem, the metal etching process provided by the present application comprises the following steps:

[0012] Step one, providing a product wafer with a bottom layer structure, and forming a metal layer on the bottom layer structure.

[0013] Step two, forming a DARC layer on the top surface of the metal layer.

[0014] Step three, forming a photoresist pattern to define a metal line forming area.

[0015] Step four, seasoning treatment is performed on the etching cavity of a dry etching machine, comprising: providing a wafer wafer with a first dielectric layer, placing the wafer wafer into the etching cavity for the first time to form a seasoning film on the inner surface of the etching cavity formed by etching by-products.

[0016] Step five, using the photoresist pattern as a mask to etch the DARC layer to expose the surface of the metal layer.

[0017] Step six, the product wafer is placed into the etching chamber for a second etching, the second etching is to etch the metal layer to form the metal line with the photoresist pattern as a mask, in the second etching process, the photoresist pattern will be etched and the etching byproduct of the photoresist is polymer, the polymer will be deposited on the side of the metal line to adjust the width of the metal line, using the characteristics of the etching byproduct of the aging film as the first dielectric layer, the adverse effect of the widening of the metal line caused by eliminating the etching byproduct of the aging film including the photoresist is eliminated.

[0018] Further improvement is that in step five, the etching process of the DARC layer adopts dry etching and is carried out in the etching chamber.

[0019] Further improvement is that after step four is completed, the product wafer in a batch is sequentially subjected to step five and step six, and the first piece effect is eliminated by using the aging film.

[0020] Further improvement is that the number of the product wafers included in the batch is 1-25.

[0021] Further improvement is that in step six, the second etching is stopped by end point detection of the surface of the DARC layer, the photoresist pattern on the top surface of the DARC layer is completely consumed, and at the same time, the etching after the photoresist pattern is consumed is avoided, so that the line width of the metal line is avoided to be reduced and a H-shaped structure is formed.

[0022] Further improvement is that in step one, the substrate of the product wafer adopts a semiconductor substrate.

[0023] Further improvement is that the semiconductor substrate includes a silicon substrate.

[0024] Further improvement is that the bottom structure includes a semiconductor device formed on the semiconductor substrate, bottom interlayer films and bottom metal layers between the surface of the semiconductor substrate and the metal layer, and through holes passing through each of the bottom interlayer films.

[0025] Further improvement is that before the metal layer is formed, a step of forming a diffusion barrier layer on the surface of the bottom structure is further included, and the metal layer is formed on the surface of the diffusion barrier layer.

[0026] Further improvement is that the material of the metal layer includes Al or AlCu.

[0027] Further improvement is that the diffusion barrier layer is composed of a Ti layer and a TiN layer.

[0028] Further improvement is that the substrate of the wafer dummy is a semiconductor substrate.

[0029] Further improvement is that the material of the first dielectric layer is silicon oxide.

[0030] Further improvement is that after step six, a step of performing a post-etching cleaning of the metal is further included.

[0031] Further improvement is that after the post-etching cleaning of the metal, a step of forming an interlayer film is further included.

[0032] The present application sets the surface film layer of the wafer dummy in the aging process before the metal etching, i.e. the second etching, as the first dielectric layer, and the first dielectric layer does not contain photoresist, so that the etching by-products of the aging film only include the etching by-products of the first dielectric layer, but not the etching by-products of the photoresist, i.e. polymer, so that the second etching of the product wafer will not be adversely affected by the etching by-products of the photoresist in the environment of the etching chamber, thereby preventing the adverse effects of the etching by-products of the photoresist in the environment of the etching chamber on the line width of the metal line. Therefore, the present application can well control the line width of the metal line, improve the appearance of the metal line, and improve the line width stability of the metal line.

[0033] Generally, the etching chamber will sequentially perform the second etching on a batch of product wafers after the aging process, and the etching chamber will be aged again before the second etching of the next batch of product wafers. The aging film after the aging process will have a greater impact on the previous several product wafers. However, in the present application, since the aging film does not contain the etching by-products of the photoresist, it will not adversely affect the line width of the metal line of the previous several product wafers after the aging process, thereby eliminating the first piece effect, so that the line width of the metal line of the previous several product wafers is close to that of the subsequent product wafers, thereby improving the line width stability of the metal line.

[0034] The present application can also set the etching endpoint of the second etching by performing endpoint detection on the DARC layer, which can further eliminate the adverse effects of continuing etching after the photoresist pattern is completely consumed, thereby eliminating the adverse effects of reducing the line width of the metal line after the photoresist pattern is completely consumed, such as forming an I-shaped structure. Therefore, the present application can further improve the appearance of the metal line and improve the line width stability of the metal line, and can eliminate the problems of electrical parameter failure and low yield caused by the thin line width of the metal line. BRIEF DESCRIPTION OF DRAWINGS

[0035] The present application will be further described in detail below in combination with the drawings and specific embodiments:

[0036] Figure 1 is an electronic line width distribution diagram of the metal lines of each product wafer of the same batch formed by the prior art metal etching process;

[0037] Figure 2 is a photo of the metal lines formed by the prior art metal etching process;

[0038] Figure 3 is a flow chart of the metal etching process of the embodiment of the present application;

[0039] Figure 4 is an electronic line width distribution diagram of the metal lines of each product wafer of two batches formed by the metal etching process of the embodiment of the present application;

[0040] Figure 5 is a photo of the metal lines formed by the metal etching process of the embodiment of the present application. DETAILED DESCRIPTION

[0041] As shown in Figure 3 is a flow chart of the metal etching process of the embodiment of the present application; the metal etching process of the embodiment of the present application comprises the following steps:

[0042] Step one, providing a product wafer with a bottom layer structure, and forming a metal layer on the bottom layer structure.

[0043] In the embodiment of the present application, the substrate of the product wafer adopts a semiconductor substrate. The semiconductor substrate includes a silicon substrate.

[0044] The bottom layer structure includes semiconductor devices formed on the semiconductor substrate, bottom layer interlayer films and bottom layer metal layers between the surface of the semiconductor substrate and the metal layer, and through holes passing through each of the bottom layer interlayer films.

[0045] Before forming the metal layer, a step of forming a diffusion barrier layer on the surface of the bottom layer structure is further included, and the metal layer is formed on the surface of the diffusion barrier layer.

[0046] The material of the metal layer includes Al or AlCu.

[0047] The diffusion barrier layer is composed of a Ti layer and a TiN layer.

[0048] Step two, forming a DARC layer on the top surface of the metal layer.

[0049] Step three, performing a photoetching process to form a photoresist pattern to define a forming area of the metal line.

[0050] Step four, performing aging treatment on the etching cavity of the dry etching machine, comprising: providing a wafer dummy with a first dielectric layer, placing the wafer dummy into the etching cavity for first etching and thereby forming an aging film on the inner surface of the etching cavity, the aging film being formed by etching by-products.

[0051] In the embodiment of the present application, the substrate of the wafer dummy is a semiconductor substrate.

[0052] The material of the first dielectric layer is silicon oxide.

[0053] Step five, etching the DARC layer with the photoresist pattern as a mask to expose the surface of the metal layer.

[0054] In the embodiment of the present application, the etching process of the DARC layer is dry etching and is performed in the etching cavity.

[0055] Step six, placing the product wafer into the etching cavity for second etching, the second etching etching the metal layer with the photoresist pattern as a mask to form the metal line, during the second etching, the photoresist pattern will be etched and the etching by-products of the photoresist are polymers, the polymers will deposit on the side of the metal line to adjust the width of the metal line, by using the characteristics that the aging film is formed by the etching by-products of the first dielectric layer, the adverse effect of the widening of the metal line caused by eliminating the etching by-products of the photoresist in the aging film is eliminated.

[0056] In the embodiment of the present application, since step five is also performed in the etching cavity, after step five is completed, the product wafer does not need to be moved, and the second etching can be realized only by adjusting the etching process parameters such as etching gas and other process parameters.

[0057] In some embodiments, the second etching stops when the surface of the DARC layer is detected by end point detection, the photoresist pattern on the top surface of the DARC layer is completely consumed, and at the same time, continuing etching after the photoresist pattern is consumed is avoided, so that the line width of the metal line can be avoided to be reduced and a H-shaped structure is formed.

[0058] After step four is completed, step five and step six are sequentially performed on the product wafers in a batch, and the aging film is used to eliminate the first piece effect.

[0059] The number of the product wafers included in the batch is 1-25.

[0060] After step six is completed, a step of performing metal etching and post-cleaning is further included.

[0061] After the metal etching and post-cleaning, an interlayer film is further formed.

[0062] This invention specifically designs the aging process of the etching chamber before the second etching of the product wafer. The surface film of the wafer dummy during aging is set as the first dielectric layer. The first dielectric layer does not contain photoresist. Therefore, the aging film formed during aging only includes the etching by-products of the first dielectric layer and does not include the etching by-products of photoresist, i.e., polymers. This ensures that the second etching of the product wafer is not adversely affected by the etching by-products of photoresist in the etching chamber environment. This prevents the adverse effect of increased linewidth of metal lines due to the etching by-products of photoresist in the etching chamber environment. Therefore, this invention can effectively control the linewidth of metal lines, improve the morphology of metal lines, and enhance the linewidth stability of metal lines.

[0063] Typically, after aging, the etching chamber sequentially performs a second etching on a batch of product wafers. After the second etching of a batch of product wafers is completed, the etching chamber is aged again before the second etching of the next batch of product wafers. The aging film after aging usually has a significant impact on the preceding product wafers. However, in this invention, since the aging film does not contain etching byproducts of photoresist, it does not actually have an adverse effect on the linewidth of the metal lines on the preceding product wafers after aging. This eliminates the first-of-its-kind effect, making the linewidth of the metal lines on the preceding product wafers similar to that on subsequent product wafers, thereby improving the linewidth stability of the metal lines.

[0064] In this embodiment of the invention, the etching endpoint of the second etching can be set by endpoint detection of the DARC layer. This further eliminates the adverse effects of continuing etching after the photoresist pattern is completely exhausted, such as the formation of an I-shaped structure, which would cause the metal line width to shrink when the photoresist pattern is completely exhausted. Therefore, this embodiment of the invention can further improve the morphology of the metal line and enhance the line width stability of the metal line, and eliminate the problems of electrical parameter failure and low yield caused by the thin line width of the metal line.

[0065] like Figure 4 The diagram shows the electronic linewidth distribution of metal lines in two batches of product wafers formed by the metal etching process of this embodiment of the invention; the horizontal axis shows the wafer batch and number; the wafer batch includes two batches, Lot1 and Lot2. Lot1 and Lot2 each contain 25 wafers; Figure 4The ordinate is the line width of the metal line, and the line width of the metal line is the electronic line width detected by the electrical parameter measurement method, not the physical line width obtained by the electron photo such as TEM or SEM photo. It can be seen that the line width of the metal line of each product wafer in each batch and the line width of the metal line of each product wafer between batches are near the target value, the stability is good, and no reliability problem occurs.

[0066] As shown in Figure 5 , it is a photo of the metal line formed by the process method of the metal etching of the embodiment of the application. Figure 5 The metal line 302 and the diffusion barrier layer 301 at the bottom of the metal line 302 and the DARC layer 303 at the top of the metal line 302 are shown in FIG. 3B, and it can be seen that the appearance of the metal line 302 is good, and the situation that the width of the metal line 302 is reduced and thus presents an H-shaped type does not occur.

[0067] The above has carried out the detailed description to the application through the specific embodiment, but these do not constitute the limitation to the application. The person skilled in the art can also make many deformations and improvements without departing from the principle of the application, and these should be regarded as the protection scope of the application.

Claims

1. A metal etching process, characterized in that, Includes the following steps: Step 1: Provide a product wafer with an underlying structure, and form a metal layer on the underlying structure; Step 2: Form a DARC layer on the top surface of the metal layer; Step 3: Forming a photoresist pattern defines the area for forming the metal lines; Step 4: Aging treatment is performed on the etching chamber of the dry etching machine, including: providing a dummy wafer with a first dielectric layer, placing the dummy wafer into the etching chamber for the first etching, thereby forming an aging film formed by etching by-products on the inner surface of the etching chamber; the aging film includes only the etching by-products of the first dielectric layer, and does not include the etching by-products of the photoresist; Step 5: Using the photoresist pattern as a mask, etch the DARC layer to expose the surface of the metal layer; Step Six: Place the product wafer into the etching cavity for a second etching. The second etching uses the photoresist pattern as a mask to etch the metal layer to form the metal line. During the second etching process, the photoresist pattern will experience etching loss, and the etching byproduct of the photoresist is a polymer. The polymer will be deposited on the side of the metal line to adjust the width of the metal line. By utilizing the characteristic of the aging film as the etching byproduct of the first dielectric layer, the adverse effect of the aging film including the photoresist etching byproduct on the widening of the metal line is eliminated. The second etching stops when the surface of the DARC layer is detected at the endpoint. The photoresist pattern on the top surface of the DARC layer is completely exhausted. Etching is avoided after the photoresist pattern is exhausted, thereby preventing the linewidth of the metal line from shrinking and forming an I-shaped structure. After step four is completed, steps five and six are performed sequentially on the product wafers in a batch to eliminate the first-of-its-kind effect using the aging film.

2. The metal etching process method as described in claim 1, characterized in that: In step five, the etching process for the DARC layer is performed using dry etching within the etching cavity.

3. The metal etching process method as described in claim 1, characterized in that: The number of product wafers included in a batch is 1 to 25.

4. The metal etching process method as described in claim 1, characterized in that: In step one, the substrate of the product wafer is a semiconductor substrate.

5. The metal etching process method as described in claim 4, characterized in that: The semiconductor substrate includes a silicon substrate.

6. The metal etching process method as described in claim 4, characterized in that: The underlying structure includes a semiconductor device formed on the semiconductor substrate, an underlying interlayer film and an underlying metal layer between the surface of the semiconductor substrate and the metal layer, and vias through each of the underlying interlayer films.

7. The metal etching process method as described in claim 6, characterized in that: The step of forming a diffusion barrier layer on the surface of the underlying structure before forming the metal layer includes the metal layer being formed on the surface of the diffusion barrier layer.

8. The metal etching process method as described in claim 7, characterized in that: The material of the metal layer includes Al or AlCu.

9. The metal etching process method as described in claim 7, characterized in that: The diffusion barrier layer is composed of a Ti layer and a TiN layer stacked together.

10. The metal etching process method as described in claim 4, characterized in that: The substrate of the dummy wafer is a semiconductor substrate.

11. The metal etching process method as described in claim 1, characterized in that: The first dielectric layer is made of silicon oxide.

12. The metal etching process method as described in claim 1, characterized in that: After step six is ​​completed, a post-etching cleaning step is also included.

13. The metal etching process method as described in claim 12, characterized in that: The post-etching and cleaning process for the metal also includes: It forms an interlayer membrane.

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