Semiconductor device structure with multiple underfill and method of making same

Abstract

A semiconductor device structure having a silicon-on-insulator region is provided. The silicon-on-insulator region has a semiconductor substrate, a buried oxide layer disposed on the semiconductor substrate, and a silicon layer disposed on the buried oxide layer. The semiconductor device structure also has a first shallow trench isolation structure that extends through the silicon layer and the buried oxide layer and into the semiconductor substrate. The first shallow trench isolation structure has a first liner that contacts the semiconductor substrate and the silicon layer, a second liner that covers the first liner and contacts the buried oxide layer, and a third liner that covers the second liner. The first liner, the second liner, and the third liner comprise different materials. The first shallow trench isolation structure also has a first trench fill layer disposed on the third liner and separated from the second liner by the third liner.

Description

[0001] Cross-references

[0002] This application claims priority and benefits from U.S. Official Application No. 17 / 245,795, filed April 30, 2021, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] This disclosure relates to a semiconductor device structure and a method for fabricating the same. In particular, it relates to a semiconductor device structure with multiple pads and a method for fabricating the same. Background Technology

[0004] Semiconductor components are indispensable for many modern applications. With advancements in electronic technology, semiconductor components have become increasingly smaller, while simultaneously offering superior functionality and incorporating a greater number of integrated circuits. Due to the miniaturization of semiconductor components, different forms and sizes of semiconductor components realizing different functions are integrated and packaged into a single module. Furthermore, numerous manufacturing steps are performed on the integration of various types of semiconductor devices.

[0005] However, the manufacturing and integration of these semiconductor devices involves many complex steps and operations. Integration within these semiconductor devices becomes increasingly complex. This increased complexity in the manufacturing and integration of semiconductor devices can lead to several defects. Therefore, there is a need for continuous improvement of the manufacturing processes for these semiconductor devices to address these defects and enhance their performance.

[0006] The above description of "prior art" provides background information only and does not acknowledge that the above description of "prior art" discloses the subject matter of this disclosure. It does not constitute prior art of this disclosure, and no description of the above "prior art" should be considered part of this case. Summary of the Invention

[0007] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer, and a silicon layer, the buried oxide layer being disposed on the semiconductor substrate, and the silicon layer being disposed on the buried oxide layer. The semiconductor device structure also has a first shallow trench isolation structure that passes through the silicon layer and the buried oxide layer and extends into the semiconductor substrate. The first shallow trench isolation structure includes a first pad contacting the semiconductor substrate and the silicon layer; a second pad covering the first pad and contacting the buried oxide layer; and a third pad covering the second pad. The first pad, the second pad, and the third pad comprise different materials. The first shallow trench isolation structure also has a first trench filling layer disposed on the third pad and separated from the second pad by the third pad.

[0008] In some embodiments, the first pad completely separates the second pad from the semiconductor substrate and the silicon layer. In some embodiments, the first pad has a first portion, a second portion, and a third portion, the first portion and the second portion covering opposite sidewalls of the silicon layer, and the third portion disposed between the second pad and the semiconductor substrate, wherein the first portion, the second portion, and the third portion of the first pad are disconnected from each other. In some embodiments, the first pad comprises silicon oxide, the second pad comprises a nitride, and the third pad comprises silicon oxynitride. Furthermore, there is a first etch selectivity between the second pad and the first trench fill layer, and a second etch selectivity between the third pad and the first trench fill layer.

[0009] In some embodiments, the semiconductor device structure further includes a pad oxide layer disposed on the silicon layer of the silicon overlay region on the insulator; and a pad nitride layer disposed on the pad oxide layer, wherein the first shallow trench isolation structure passes through the pad oxide layer and the pad nitride layer, wherein each sidewall of the pad oxide layer and each sidewall of the pad nitride layer are covered by and contact the second pad of the first shallow trench isolation structure. In some embodiments, the semiconductor device structure further includes a second shallow trench isolation structure passing through the pad oxide layer and the pad nitride layer and extending into the semiconductor substrate. The second shallow trench isolation structure includes a second trench filling layer; and a fourth pad separating the second trench filling layer from the pad oxide layer, the pad nitride layer, and the semiconductor substrate. In some embodiments, the first shallow trench isolation structure is disposed in an array region, and the second shallow trench isolation structure is disposed in a surrounding circuit region.

[0010] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a pad oxide layer on a semiconductor substrate; and forming a pad nitride layer on the pad oxide layer. The method also includes forming a shallow trench passing through the pad nitride layer and the pad oxide layer, and extending into the semiconductor substrate; and forming a first pad on each sidewall and a lower surface of the semiconductor substrate in the shallow trench. The method further includes forming a second pad on the first pad; and forming a third pad on the second pad. Furthermore, the method includes filling a remaining portion of the shallow trench with a trench filling layer on the third pad; and planarizing the second pad, the third pad, and the trench filling layer to expose the pad nitride layer. The remaining portions of the first pad and the second pad, the third pad, and the trench filling layer together form a shallow trench isolation structure in an array region.

[0011] In some embodiments, the second pad is formed to directly contact each sidewall of the pad oxide layer and each sidewall of the pad nitride layer. In some embodiments, there is a first etch selectivity between the second pad and the trench fill layer, and a second etch selectivity between the third pad and the trench fill layer. In some embodiments, prior to forming the pad oxide layer, the fabrication method further includes forming a buried oxide layer on the semiconductor substrate; and forming a silicon layer on the buried oxide layer, wherein the shallow trench passes through the buried oxide layer and the silicon layer, wherein the fabrication technique of the first pad includes performing an oxidation process on the silicon layer and the semiconductor substrate.

[0012] In some embodiments, the fabrication technique for the second pad includes a rapid thermal nitridation (RTN) process, while the fabrication technique for the third pad includes an in-situ steam generation (ISSG) process. In some embodiments, prior to forming the pad oxide layer, the fabrication method further includes forming a well region in the semiconductor substrate, wherein the well region is p-type, and a region of the semiconductor substrate below the well region is n-type, wherein after forming the shallow trench, the lower surface of the shallow trench is higher than the lower surface of the well region.

[0013] This disclosure provides some embodiments of a semiconductor device structure and its fabrication method. In some embodiments, the semiconductor device structure has a shallow trench isolation structure disposed in a semiconductor substrate (or in a silicon-on-insulator (SOI) region). The shallow trench isolation structure has a first pad, a second pad, a third pad, and a trench filling layer. The first pad contacts the semiconductor substrate, the second pad covers the first pad, the third pad covers the second pad, and the trench filling layer is disposed on the third pad. Because multiple pads are disposed between the trench filling layer and the semiconductor substrate, the sidewalls of the semiconductor substrate with the shallow trench isolation structure as the interface are protected from exposure during subsequent etching processes. This avoids electrical short circuits in the semiconductor device during subsequent processing steps, thereby enhancing device performance.

[0014] The foregoing has provided a fairly broad overview of the technical features and advantages of this disclosure, thereby enabling a better understanding of the detailed description of this disclosure that follows. Other technical features and advantages constituting the subject matter of the claims will be described below. Those skilled in the art to which this disclosure pertains will understand that the concepts and specific embodiments disclosed below can be readily utilized to achieve the same purpose as this disclosure through modifications or design of other structures or processes. Those skilled in the art will also understand that such equivalent constructions cannot depart from the concept and scope of this disclosure as defined by the claims. Attached Figure Description

[0015] A more comprehensive understanding of the disclosure of this application can be obtained by referring to the accompanying drawings in conjunction with the embodiments and claims. The same element symbols in the drawings refer to the same elements.

[0016] Figure 1 This is a partial structural diagram illustrating an exemplary integrated circuit of some embodiments of the present disclosure, including an array region and a surrounding circuit region.

[0017] Figure 2 This is a cross-sectional schematic diagram illustrating a cell area of ​​a semiconductor device structure according to some embodiments of the present disclosure.

[0018] Figure 3 This is a cross-sectional schematic diagram illustrating a peripheral circuit area of ​​a semiconductor element structure according to some embodiments of the present disclosure.

[0019] Figure 4 This is a cross-sectional schematic diagram illustrating a unit cell region of a semiconductor device structure according to some embodiments of the present disclosure.

[0020] Figure 5 This is a cross-sectional schematic diagram illustrating a surrounding circuit region of a semiconductor element structure according to some embodiments of the present disclosure.

[0021] Figure 6 This is a flowchart illustrating a method for fabricating a unit cell region of a semiconductor device structure according to some embodiments of this disclosure.

[0022] Figure 7 This is a cross-sectional schematic diagram illustrating an intermediate stage in some embodiments of the present disclosure during the formation of a unit cell region of a semiconductor device structure, in which a buried oxide layer and a silicon layer are formed on a semiconductor substrate.

[0023] Figure 8 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a pad oxide layer and a pad nitride layer during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0024] Figure 9 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a shallow trench during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0025] Figure 10 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a first pad during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0026] Figure 11 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a second pad during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0027] Figure 12 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a third pad during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0028] Figure 13 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a shallow trench filling layer during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0029] Figure 14 This is a cross-sectional schematic diagram illustrating an intermediate stage in which a well region is formed in a semiconductor substrate during the formation of a unit cell region of a semiconductor element structure, according to some embodiments of the present disclosure.

[0030] Figure 15 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a pad oxide layer and a pad nitride layer during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0031] Figure 16 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a shallow trench during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0032] Figure 17This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a first pad during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0033] Figure 18 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a second pad during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0034] Figure 19 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a third pad during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0035] Figure 20 This is a cross-sectional schematic diagram illustrating an intermediate stage in the formation of a trench filling layer during the formation of a unit cell region of a semiconductor device structure, according to some embodiments of the present disclosure.

[0036] Explanation of reference numerals in the attached figures:

[0037] 10: Preparation method

[0038] 100: Semiconductor Component Structure

[0039] 1000: Memory element

[0040] 101: Semiconductor substrate

[0041] 103: Embedded oxide layer

[0042] 105: Silicon layer

[0043] 107: Silicon region on insulator

[0044] 109: Pad oxide layer

[0045] 111: Nitride layer

[0046] 120: Shallow trench

[0047] 123: First pad

[0048] 123a: Part

[0049] 123b: Part

[0050] 123c: Part

[0051] 125: Second pad

[0052] 127: Third pad

[0053] 129: Trench filling layer

[0054] 133: Padding

[0055] 139: Trench filling layer

[0056] 150a: Shallow trench isolation structure

[0057] 150b: Shallow trench isolation structure

[0058] 200: Semiconductor Component Structure

[0059] 207: Well Area

[0060] 209: Pad oxide layer

[0061] 211: Nitride layer

[0062] 220: Shallow trench

[0063] 223: First pad

[0064] 225: Second pad

[0065] 227: Third Pad

[0066] 229: Trench filling layer

[0067] 233: Padding

[0068] 239: Trench filling layer

[0069] 250a: Shallow trench isolation structure

[0070] 250b: Shallow trench isolation structure

[0071] 50: Memory cell

[0072] 51: Field-Effect Transistor

[0073] 53: Capacitor

[0074] 55: Drain

[0075] 57: Source Extreme

[0076] 59: Gate

[0077] A: Array area

[0078] B: Surrounding circuit area

[0079] B1: Lower surface

[0080] B2: Lower surface

[0081] B3: Lower surface

[0082] B4: Lower surface

[0083] B5: Lower surface

[0084] B6: Lower surface

[0085] BL: Bitline

[0086] S11: Steps

[0087] S13: Steps

[0088] S15: Steps

[0089] S17: Steps

[0090] S19: Steps

[0091] S21: Steps

[0092] S23: Steps

[0093] S25: Steps

[0094] SW3: Sidewall

[0095] SW4: Sidewall

[0096] SW5: Sidewall

[0097] SW6: Sidewall

[0098] SW7: Sidewall

[0099] SW8: Sidewall

[0100] SW11: Sidewall

[0101] SW12: Sidewall

[0102] SW13: Sidewall

[0103] SW14: Sidewall

[0104] T1: top surface

[0105] T2: Top surface

[0106] T3: Top surface

[0107] T4: Top surface

[0108] WL: Character Line Detailed Implementation

[0109] The following describes specific examples of components and configurations to simplify embodiments of this disclosure. Of course, these embodiments are merely illustrative and are not intended to limit the scope of this disclosure. For example, in the description, a first component is formed on top of a second component, which may include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in many examples of embodiments of this disclosure. These repetitions are for simplicity and clarity and, unless specifically stated herein, do not in themselves represent a specific relationship between the various embodiments and / or the configurations discussed.

[0110] Furthermore, for ease of explanation, spatial relative terms such as "beneath," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another element or feature. These spatial relative terms are intended to encompass different orientations of the elements in use or operation, in addition to those shown in the figures. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatial relative descriptions used herein can be interpreted accordingly.

[0111] Figure 1 This is a partial structural schematic diagram illustrating an exemplary integrated circuit, such as a memory element 1000, of some embodiments of the present disclosure, including an array region A and a surrounding circuit region B. In some embodiments, the memory element 1000 includes a dynamic random access memory (DRAM). In some embodiments, the array region A of the memory element 1000 has a plurality of memory cells 50 configured in a grid pattern and having a plurality of rows and columns. The plurality of memory cells 50 in the array region A may be varied according to system requirements and fabrication technology.

[0112] In some embodiments, each memory cell 50 in array region A has an access element and a storage element. The access element is configured to provide control access to the storage element. In some embodiments, according to some examples, the access element is a field-effect transistor (FET) 51, and the storage element is a capacitor 53. In each memory cell 50, the FET 51 has a drain 55, a source 57, and a gate 59. One terminal of the capacitor 53 is electrically connected to the source 57 of the FET 51, and the other terminal of the capacitor 53 may be electrically connected to ground. Furthermore, in each memory cell 50, the gate 59 of the FET 51 is electrically connected to a word line WL, and the drain 55 of the FET 51 is electrically connected to a word line BL.

[0113] The above description states that the terminal of the field-effect transistor 51 electrically connected to the capacitor 53 is the source 57, and the terminal of the field-effect transistor 51 electrically connected to the bit line BL is the drain 55. However, during read and write operations, the terminal of the field-effect transistor 51 electrically connected to the capacitor 53 can be the drain, and the terminal of the field-effect transistor 51 electrically connected to the bit line BL can be the source. That is, either terminal of the field-effect transistor 51 can be a source or a drain, depending on how the field-effect transistor 51 is controlled by the voltages applied to its source, drain, and gate.

[0114] By controlling the voltage at the gate 59 via the word line WL, a voltage potential can be generated across the field-effect transistor 51, allowing electrical charge to flow from the source 55 to the capacitor 53. Therefore, the charge stored in the capacitor 53 can be represented as a two-bit data value in the memory cell 50. For example, a positive charge stored at a threshold voltage in the capacitor 53 is represented as a two-bit "1". If the charge in the capacitor 53 is below the threshold value, a two-bit "0" can be said to be stored in the memory cell 50.

[0115] The bit lines BL are configured to read or write data from and to the memory cells 50. The word lines WL are configured to activate field-effect transistors 51 to access a specific column of the memory cells 50 in array region A. Accordingly, the memory element 1000 also has a surrounding circuit region B, which may include an address buffer, a row decoder, and a column decoder. The row and column decoders selectively access the memory cells 50 in response to multiple address signals provided to the address buffer during read, write, and refresh operations. These address signals are typically provided by an external controller, such as a microprocessor or other type of memory controller.

[0116] Figure 2 This is a cross-sectional schematic diagram illustrating a unit cell region of a semiconductor element structure 100 according to some embodiments of the present disclosure, for example in... Figure 1 The unit cell region A of memory element 1000 in the memory. Figure 3 This is a cross-sectional schematic diagram illustrating a surrounding circuit region of a semiconductor element structure 100 according to some embodiments of the present disclosure, for example in Figure 1 The surrounding circuit area B of the memory element 1000 in the memory.

[0117] like Figure 2 As shown, the unit cell region of the semiconductor device structure 100 has a silicon-on-insulator (SOI) region 107. According to some embodiments, the SOI region 107 includes a semiconductor substrate 101; a buried oxide layer 103 disposed on the semiconductor substrate 101; and a silicon layer 105 disposed on the buried oxide layer 103. Furthermore, a pad oxide layer 109 is disposed on the SOI region 107, and a pad nitride layer 111 is disposed on the pad oxide layer 109.

[0118] According to some embodiments, the unit cell region of the semiconductor device structure 100 also includes a shallow trench isolation (STI) structure 150a that passes through the pad nitride layer 111 and the pad oxide layer 109 and extends into the insulator overlay silicon region 107. In some embodiments, the shallow trench isolation structure 150a passes through the silicon layer 105 and the buried oxide layer 103 and extends into the semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 is not penetrated by the shallow trench isolation structure 150a.

[0119] In some embodiments, the shallow trench isolation structure 150a in the unit cell region of the semiconductor device structure 100 has a first pad 123; a second pad 125 disposed on the first pad 123; a third pad 127 disposed on the second pad 125; and a trench filling layer 129 disposed on the third pad 127. In some embodiments, the trench filling layer 129 is surrounded by the third pad 127, the third pad 127 is surrounded by the second pad 125, and the second pad 125 is separated from the silicon layer 105 and the semiconductor substrate 101 by the first pad 123. In some embodiments, according to some examples, the first pad 113 has portions 123a and 123c covering opposite sidewalls of the silicon layer 105, and a portion 123b separating the second pad 125 from the semiconductor substrate 101.

[0120] It should be understood that the portions 123a, 123b, and 123c of the first pad 123 are disconnected from each other. In some embodiments, the sidewalls of the pad nitride layer 111 and the sidewalls of the pad oxide layer 109 are covered by and in contact with the second pad 125. In some embodiments, the uppermost surface T2 of the second pad 125 is higher than the uppermost surface T1 of the first pad 123 (e.g., the upper surface of portion 123a or the upper surface of portion 123c). In some embodiments, the upper surfaces of the second pad 125, the third pad 127, and the trench filling layer 129 are substantially coplanar. In this disclosure, the term "substantially" means preferably at least 90%, more preferably 95%, even more preferably 98%, and most preferably 99%.

[0121] Furthermore, the first pad 123, the second pad 125, and the third pad 127 of the shallow trench isolation structure 150a in the array region of the semiconductor device structure 100 may comprise different materials. For example, the first pad 123 comprises silicon oxide, the second pad 125 comprises a nitride, and the third pad 127 comprises silicon oxynitride. Moreover, there is a first etch selectivity between the second pad 125 and the trench fill layer 129, and a second etch selectivity between the third pad 127 and the trench fill layer 129.

[0122] like Figure 3 As shown, according to some embodiments, the peripheral circuit region of the semiconductor element structure 100 includes a semiconductor substrate 101, a pad oxide layer 109, a pad nitride layer 111, and a shallow trench isolation structure 150b, which passes through the pad nitride layer 111 and the pad oxide layer 109 and extends into the semiconductor substrate 101. In some embodiments, the semiconductor substrate 101 is not penetrated by the shallow trench isolation structure 150b in the peripheral circuit region.

[0123] Compared to the shallow trench isolation structure 150a in the unit cell region of the semiconductor device structure 100, the shallow trench isolation structure 150b in the surrounding circuit region of the semiconductor device structure 100 has a single pad instead of multiple pads. In some embodiments, the shallow trench isolation structure 150b has a pad 133 (also considered as a fourth pad) and a trench filling layer 139, wherein the trench filling layer 139 is disposed on the pad 133. In some embodiments, the trench filling layer 139 is surrounded by the pad 133.

[0124] Furthermore, in some embodiments, the trench filling layer 139 is separated from the pad nitride layer 111, the pad oxide layer 109, and the semiconductor substrate 101 by a pad 133. In some embodiments, the upper surfaces of the pad 133 and the trench filling layer 139 are substantially coplanar. In some embodiments, the pad 133 comprises silicon oxide, and its fabrication technique includes an oxidation process or a deposition process, such as chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0125] Figure 4 This is a cross-sectional schematic diagram illustrating a unit cell region of a semiconductor element structure 200 according to some embodiments of the present disclosure, for example in... Figure 1 The memory element 1000 has a unit cell region A. Figure 5 This is a cross-sectional schematic diagram illustrating a surrounding circuit region of a semiconductor element structure 200 according to some embodiments of the present disclosure, for example in Figure 1 The surrounding circuit area B of the memory element 1000.

[0126] like Figure 4 As shown, according to some embodiments, the unit cell region of the semiconductor device structure 200 has a well region 207 disposed in a semiconductor substrate 201; a pad oxide layer 209 disposed on the well region 207; and a pad nitride layer 211 disposed on the pad oxide layer 209. In some embodiments, a region of the semiconductor substrate 201 below the well region 207 has a first conductivity type, while the well region 207 has a second conductivity type, the second conductivity type being the opposite of the first conductivity type. For example, the region of the semiconductor substrate 201 below the well region 207 is n-type, while the well region 207 is p-type.

[0127] According to some embodiments, the unit cell region of the semiconductor device structure 200 also includes a shallow trench isolation structure 250a that penetrates the pad nitride layer 211 and the pad oxide layer 209 and extends into the well region 207. In some embodiments, the well region 207 is not penetrated by the shallow trench isolation structure 250a. Figure 4 As shown, according to some embodiments, the lower surface B2 of the shallow trench isolation structure 250a is higher than the lower surface B1 of the well area 207.

[0128] In some embodiments, the shallow trench isolation structure 250a in the unit cell region of the semiconductor device structure 200 has a first pad 223; a second pad 225 disposed on the first pad 223; a third pad 227 disposed on the second pad 225; and a trench filling layer 229 disposed on the third pad 227. In some embodiments, the trench filling layer 229 is surrounded by the third pad 227, the third pad 227 is surrounded by the second pad 225, and the second pad 225 is separated from the well region 207 by the first pad 223.

[0129] In some embodiments, the sidewalls of the pad nitride layer 211 and the sidewalls of the pad oxide layer 209 are covered by and in direct contact with the second pad 225. In some embodiments, the uppermost surface T4 of the second pad 225 is higher than the uppermost surface T3 of the first pad 223. In some embodiments, the upper surfaces of the second pad 225, the third pad 229, and the trench filling layer 229 are substantially coplanar.

[0130] Furthermore, the first pad 223, the second pad 225, and the third pad 227 of the shallow trench isolation structure 250a in the unit cell region of the semiconductor device structure 200 comprise different materials. For example, the first pad 223 comprises silicon oxide, the second pad 223 comprises a nitride, and the third pad 227 comprises silicon oxynitride. Moreover, there is a first etch selectivity between the second pad 225 and the trench fill layer 229, and a second etch selectivity between the third pad 227 and the trench fill layer 229.

[0131] like Figure 5 As shown, according to some embodiments, the peripheral circuit region of the semiconductor element structure 200 includes a semiconductor substrate 201; a well region 207 disposed in the semiconductor substrate 201; a pad oxide layer 209; a pad nitride layer 211; and a shallow trench isolation structure 250b passing through the pad nitride layer 211 and the pad oxide layer 209 and extending into the well region 207. In some embodiments, the well region 207 is not penetrated by the shallow trench isolation structure 250b in the peripheral circuit region. In some embodiments, the lower surface B3 of the shallow trench isolation structure 250b is higher than the lower surface B1 of the well region 207.

[0132] Compared to the shallow trench isolation structure 250a in the unit cell region of the semiconductor device structure 200, the shallow trench isolation structure 250b in the surrounding circuit region of the semiconductor device structure 200 has a single pad instead of multiple pads. In some embodiments, the shallow trench isolation structure 250b has a pad 233 (also considered as a fourth pad) and a trench filling layer 239 disposed on the pad 233. In some embodiments, the trench filling layer 239 is surrounded by the pad 233.

[0133] Furthermore, in some embodiments, the trench filling layer 239 is separated from the pad nitride layer 211, the pad oxide layer 209, and the well region 207 by a liner 233. In some embodiments, the liner 233 and the upper surfaces of the trench filling layer 239 are substantially coplanar. In some embodiments, the liner 233 comprises silicon oxide, and its fabrication technique includes an oxidation process or a deposition process, such as a CVD process or an ALD process.

[0134] Figure 6 This is a flowchart illustrating a method 10 for fabricating a unit cell region of a semiconductor device structure (e.g., semiconductor device structure 100 or 200) according to some embodiments of the present disclosure. The fabrication method 10 includes steps S11, S13, S15, S17, S19, S21, S23 and S25. Figure 6 Steps S11 to S25 are described in detail with reference to the following figures.

[0135] Figures 7 to 13 This is a cross-sectional schematic diagram illustrating various intermediate stages during the formation of the unit cell region of the semiconductor device structure 100 according to some embodiments of the present disclosure. For example... Figure 7 A semiconductor substrate 101 is provided. The semiconductor substrate 101 may be a semiconductor wafer, such as a silicon wafer.

[0136] Additionally, the semiconductor substrate 101 may comprise elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Examples of elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Examples of compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Examples of alloy semiconductor materials may include, but are not limited to, germanium silicon (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and gallium arsenide phosphide (GaInAsP).

[0137] In some embodiments, a buried oxide layer 103 and a silicon layer 105 are formed on a semiconductor substrate 101 to form an insulator-on-silicon region 107. The fabrication technique for the insulator-on-silicon region 107 may include separation by implanted oxygen (SIMOX), where oxygen is implanted beneath the silicon surface and an annealing process is performed. However, alternative processes such as wafer bonding, oxidation, or deposition may be used to form the insulator-on-silicon region 107.

[0138] Next, as Figure 8 As shown, according to some embodiments, a pad oxide layer 109 and a pad nitride layer 111 are sequentially formed on the silicon-on-insulator region 107. The corresponding steps are shown in... Figure 6 Steps S11 and S13 in the fabrication method 10 shown. In some embodiments, the pad oxide layer 109 comprises silicon oxide, such as SiO2, and the pad nitride layer 111 comprises silicon nitride, such as Si3N4. The fabrication techniques for the pad oxide layer 109 and the pad nitride layer 111 may include thermal oxidation, CVD, ALD, and / or other applicable methods.

[0139] like Figure 9 As shown, according to some embodiments, after the pad nitride layer 111 is formed, a shallow trench 120 is formed to pass through the pad nitride layer 111, the pad oxide layer 109, the silicon layer 105, the buried oxide layer 103, and extend into the semiconductor substrate 101. In some embodiments, the lower surface B4 of the shallow trench 120 is disposed in the semiconductor substrate 101. The corresponding steps are shown in... Figure 6 Step S15 in the preparation method 10 shown.

[0140] In some embodiments, the fabrication of the shallow trench 120 includes forming a patterned mask (not shown) on the pad nitride layer 111; and using the patterned mask as a mask to etch the underlying structure. A wet etching process, a dry etching process, or a combination thereof can be used to perform the etching process. After the shallow trench 120 is formed, for example, an ashing process can be used to remove the patterned mask after continuing a wet etching process.

[0141] Next, as Figure 10 As shown, according to some embodiments, a first gasket 123 is formed on each sidewall and lower surface B4 of the shallow trench 120. The corresponding steps are shown in... Figure 6Step S17 of the fabrication method 10 shown. In some embodiments, the opposite sidewalls of the silicon layer 105 (e.g., the sidewalls of the silicon layer 105 exposed in the shallow trench 120) are covered and directly contacted by portions 123a and 123c of the first pad 123, and the exposed sidewalls of the semiconductor substrate 101 in the shallow trench 120 and the exposed surface (e.g., the lower surface B4 of the shallow trench 120) are covered and directly contacted by portions 123b of the first pad 123.

[0142] In some embodiments, the first pad 123 comprises silicon oxide, such as SiO2, and its fabrication technique includes an oxidation process. In some embodiments, the oxidation process for forming the first pad 123 is a selective oxidation due to the different compositions of the layers in the silicon-on-insulator region 107. In some embodiments, the silicon layer 105 of the silicon-on-insulator region 107 and the exposed sidewalls and / or surfaces of the semiconductor substrate 101 are completely covered by the first pad 123, while the sidewalls of the pad nitride layer 111, the pad oxide layer 109, and the buried oxide layer 103 in the shallow trench 120 are at least partially exposed.

[0143] Next, as Figure 11 As shown, according to some embodiments, the second pad 125 is formed on the first pad 123. The corresponding steps are shown in... Figure 6 Step S19 in the preparation method 10 shown. In some embodiments, a second liner 125 is conformally formed on the upper surface of the nitride layer 111 and lined with the remaining portion of the shallow groove 120.

[0144] In some embodiments, the first pad 123 is completely covered by the second pad 125, and the exposed sidewalls SW7 and SW8 of the pad nitride layer 111, the exposed sidewalls SW5 and SW6 of the pad oxide layer 109, and the sidewalls SW3 and SW4 of the buried oxide layer 103 are covered by the second pad 125 and directly contact the second pad 125. In some embodiments, the second pad 125 comprises a nitride, such as silicon nitride, and its fabrication technology includes a nitriding process, such as a rapid thermal nitridation (RTN) process.

[0145] Then, as Figure 12 As shown, according to some embodiments, a third gasket 127 is formed on the second gasket 125. The corresponding steps are shown in... Figure 6Step S21 of the preparation method 10 shown. In some embodiments, a third pad 1127 is conformally formed on the upper surface of the pad nitride layer 111 and lined with the remainder of the shallow trench 120. In some embodiments, the third pad 127 comprises silicon oxynitride and its fabrication technique includes an in-situ steam generation (ISSG) process.

[0146] Next, as Figure 13 As shown, according to some embodiments, a trench filling layer 129 is formed on the third gasket 127 and fills the remaining portion of the shallow trench 120. The corresponding steps are shown in... Figure 6 Step S23 in preparation method 10 shown.

[0147] In some embodiments, the trench fill layer 129 comprises a dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon oxide carbonitride, or a combination thereof. It should be understood that the material of the trench fill layer 129 differs from the materials of the second pad 125 and the third pad 127 to ensure sufficient etch selectivity between the second pad 125 and the trench fill layer 129, and between the third pad 127 and the trench fill layer 129. Furthermore, the fabrication technique of the trench fill layer 129 may include a deposition process, such as a CVD process or an ALD process.

[0148] Next, please refer back to the previous section. Figure 2 According to some embodiments, a planarization process is performed on the trench filler layer 129, the third gasket 127, and the second gasket 25 to expose the upper surface of the pad nitride layer 111, so that the trench filler layer 129, the third gasket 127, and the second gasket 125 are substantially coplanar with each other. The corresponding steps are shown in... Figure 6 Step S25 of the fabrication method 10 shown. In some embodiments, the planarization process is a chemical mechanical polishing (CMP) process. After the planarization process, a shallow trench isolation structure 150a in the array region of the semiconductor device structure 100 is obtained.

[0149] Because there are multiple pads surrounding the trench fill layer 129 in the shallow isolation structure 150a, and multiple etch selectivity exists between these pads and the trench fill layer 129, the insulator-overlapping silicon region 107 is protected from exposure during etching (for example, the recessed trench fill layer 129). Therefore, an electrical short circuit between the semiconductor substrate 101 and the silicon layer 105 is avoided.

[0150] Figures 14 to 20 This is a cross-sectional schematic diagram illustrating various intermediate stages during the formation of the unit cell region of the semiconductor device structure 200 according to some embodiments of the present disclosure. For example... Figure 14 As shown, a semiconductor substrate 201 is provided. The semiconductor substrate 201 may be similar to the semiconductor substrate 101 described above, and its description will not be repeated herein.

[0151] In some embodiments, well region 207 is formed in semiconductor substrate 201. The fabrication technique of well region 207 may include an ion implantation process, and may implant p-type or n-type dopants to form well region 207 depending on the conductivity type of the region of semiconductor substrate 201 below the well region. Examples of p-type dopants include boron, gallium, or indium, while examples of n-type dopants include phosphorus or arsenic. As mentioned above, the conductivity type of well region 207 is opposite to the conductivity type of the region of semiconductor substrate 201 below well region 207. For example, in some embodiments, well region 207 is p-type, while the region of semiconductor substrate 201 below well region 207 is n-type.

[0152] Next, as Figure 15 As shown, according to some embodiments, a pad oxide layer 209 and a pad nitride layer 211 are sequentially formed on a semiconductor substrate 201 and cover the well region 207. The corresponding steps are shown in... Figure 6 Step S11 in the preparation method 10 shown. Some materials and processes used to form the pad oxide layer 209 and the pad nitride layer 211 are similar to or the same as those used to form the pad oxide layer 109 and the pad nitride layer 111, and will not be described in detail again in this document.

[0153] like Figure 16 As shown, according to some embodiments, after the pad nitride layer 211 is formed, a shallow trench 220 is formed to pass through the pad nitride layer 211 and the pad oxide layer 209, and extend into the well region 207. In some embodiments, the lower surface B5 of the shallow trench 220 is disposed in the well region 207 and is higher than the lower surface B6 of the well region 207. The corresponding steps are shown in... Figure 6 Step S15 in the preparation method 10 shown. Some processes for forming the shallow trench 220 are similar to or the same as those for forming the shallow trench 120, and their detailed descriptions will not be repeated herein.

[0154] Next, as Figure 17 As shown, according to some embodiments, a first gasket 223 is formed on each sidewall and lower surface B5 of the shallow trench 220. The corresponding steps are shown in... Figure 6 Step S17 in the preparation method 10 shown. In some embodiments, the exposed sidewalls SW9, SW10 of the well area 207 and the exposed surfaces (e.g., the lower surface B5 of the shallow trench 220) are covered by and in direct contact with the first liner 223.

[0155] Some of the materials and processes used to form the first pad 223 are similar to or the same as those used to form the first pad 123 of the semiconductor device structure 100, and their detailed description will not be repeated herein. It should be understood that the oxidation process for forming the first pad 223 is a selective oxidation due to the different compositions of the well region 207, the pad oxide layer 209, and the pad nitride layer 211. In some embodiments, the exposed sidewalls and / or surfaces of the well region 207 are completely covered by the first pad 223, while the sidewalls of the pad nitride layer 211 and the pad oxide layer 209 in the shallow trench 220 are at least partially exposed.

[0156] Next, as Figure 18 As shown, according to some embodiments, the second pad 225 is formed on the first pad 223. The corresponding steps are shown in... Figure 6 Step S19 in the fabrication method 10 shown. Similar to the second pad 125 of the semiconductor element structure 100, the second pad 225 is conformally formed on the upper surface of the pad nitride layer 211 and lined with the remaining portion of the shallow trench 220.

[0157] In some embodiments, the first pad 223 is completely covered by the second pad 225, while the exposed sidewalls SW13 and SW14 of the pad nitride layer 211 and the exposed sidewalls SW11 and SW12 of the pad oxide layer 209 are covered by the second pad 225 and directly contact the second pad 225. Some materials and processes used to form the second pad 225 are similar to or the same as those used to form the second pad 125 of the semiconductor device structure 100, and their detailed descriptions will not be repeated herein.

[0158] Then, as Figure 19 As shown, according to some embodiments, a third pad 227 is formed on the second pad 225. The corresponding steps are shown in... Figure 6 Step S21 of the fabrication method 10 shown. In some embodiments, the third pad 227 is conformally formed on the upper surface of the pad nitride layer 211, and the remaining portion of the shallow trench 220 is added. Some materials and processes used to form the third pad 227 are similar to or the same as those used to form the third pad 127 of the semiconductor device structure 100, and their detailed description will not be repeated herein.

[0159] Next, as Figure 20 As shown, according to some embodiments, the trench filling layer 229 is formed on the third liner 227 and fills the remaining portion of the shallow trench 220. The corresponding steps are shown in... Figure 6Step S23 of the fabrication method 10 shown. Some materials and processes used to form the trench fill layer 229 are similar to or the same as those used to form the trench fill layer 129 of the semiconductor device structure 100, and their detailed description will not be repeated herein. It should be understood that the material of the trench fill layer 229 is different from the materials of the second pad 225 and the third pad 227, so that there is sufficient etch selectivity between the second pad 225 and the trench fill layer 229 and between the third pad 227 and the trench fill layer 229.

[0160] Next, please refer back to the previous section. Figure 4 According to some embodiments, a planarization process is performed on the trench filler layer 229, the third gasket 227, and the second gasket 225 to expose the upper surface of the pad nitride layer 211, so that the upper surfaces of the trench filler layer 229, the third gasket 227, and the second gasket 225 are substantially coplanar. The corresponding steps are shown in... Figure 6 Step S25 of the fabrication method 10 shown. In some embodiments, the planarization process is a CMP process. After the planarization process, a shallow trench isolation structure 250a is obtained in the array region of the semiconductor device structure 200.

[0161] Because there are multiple gaskets surrounding the trench fill layer 229 in the shallow isolation structure 250a, and multiple etch selectivity exists between these gaskets and the trench fill layer 229, the well area 207 is protected from exposure during etching (for example, the recessed trench fill layer 229). Therefore, electrical short circuits are avoided.

[0162] This disclosure provides some embodiments of semiconductor device structures 100, 200 and methods for fabricating the same. In some embodiments, semiconductor device structure 100 has a shallow trench isolation structure 150a disposed in an insulator-on-silicon region 107. The shallow trench isolation structure 150a has a first pad 123, a second pad 125, a third pad 127, and a trench filling layer 129. The first pad 123 contacts the semiconductor substrate 101 and silicon layer 105 in the insulator-on-silicon region 107. The second pad 125 covers the first pad 123, and the third pad 127 covers the second pad 125. The trench filling layer 129 is disposed on the third pad 127 and separated from the second pad 125 by the third pad 127. Because multiple pads are disposed between the trench filling layer 129 and the insulator-on-silicon region 107, the sidewalls of the insulator-on-silicon region 107 can be protected from exposure during subsequent etching processes (e.g., recessing the trench filling layer 129). This avoids electrical short circuits between the semiconductor substrate 101 and the silicon layer 105.

[0163] In some embodiments, the semiconductor device structure 200 includes a shallow trench isolation structure 250a disposed in a well region 207 of the semiconductor substrate 201. The shallow trench isolation structure 250a has a first pad 223, a second pad 225, a third pad 227, and a trench fill layer 229. The first pad 223 contacts the well region 207, the second pad 225 covers the first pad 223, the third pad 227 covers the second pad 225, and the trench fill layer 229 is disposed on the third pad 227 and separated from the second pad 225 by the third pad 227. Because multiple pads are disposed between the trench fill layer 229 and the well region 207, the well region 207 is protected from exposure during subsequent etching processes (e.g., recessing the trench fill layer 229). This prevents electrical short circuits in the semiconductor device structure 200 during subsequent processing steps (e.g., forming a conductive element on the well region 207).

[0164] One embodiment of this disclosure provides a semiconductor device structure. The semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer, and a silicon layer, the buried oxide layer being disposed on the semiconductor substrate, and the silicon layer being disposed on the buried oxide layer. The semiconductor device structure also has a first shallow trench isolation structure that passes through the silicon layer and the buried oxide layer and extends into the semiconductor substrate. The first shallow trench isolation structure includes a first pad contacting the semiconductor substrate and the silicon layer; a second pad covering the first pad and contacting the buried oxide layer; and a third pad covering the second pad. The first pad, the second pad, and the third pad comprise different materials. The first shallow trench isolation structure also has a first trench filling layer disposed on the third pad and separated from the second pad by the third pad.

[0165] Another embodiment of this disclosure provides a method for fabricating a semiconductor device structure. The method includes forming a pad oxide layer on a semiconductor substrate; and forming a pad nitride layer on the pad oxide layer. The method also includes forming a shallow trench passing through the pad nitride layer and the pad oxide layer, and extending into the semiconductor substrate; and forming a first pad on each sidewall and a lower surface of the semiconductor substrate in the shallow trench. The method further includes forming a second pad on the first pad; and forming a third pad on the second pad. Furthermore, the method includes filling a remaining portion of the shallow trench with a trench filling layer on the third pad; and planarizing the second pad, the third pad, and the trench filling layer to expose the pad nitride layer. The remaining portions of the first pad and the second pad, the third pad, and the trench filling layer together form a shallow trench isolation structure in an array region.

[0166] The embodiments disclosed herein have several advantageous features. By forming multiple pads in the shallow trench isolation structure and between the trench filling layer and the semiconductor substrate, the sidewalls of the semiconductor substrate having the shallow trench isolation structure as an interface can be protected from exposure during subsequent etching processes, thus preventing electrical short circuits. Therefore, device performance can be enhanced.

[0167] While this disclosure and its advantages have been described in detail, it should be understood that various changes, substitutions, and alternatives can be made without departing from the concept and scope of this disclosure as defined in the claims. For example, many of the processes described above can be implemented using different methods, and other processes or combinations thereof can be substituted for many of the processes described above.

[0168] Furthermore, the scope of this application is not limited to the specific embodiments of the processes, machinery, manufacturing, material compositions, means, methods, and steps described in the specification. Those skilled in the art will understand from the disclosure of this publication that existing or future processes, machinery, manufacturing, material compositions, means, methods, or steps that have the same function or achieve substantially the same results as the corresponding embodiments described herein can be used based on this disclosure. Accordingly, such processes, machinery, manufacturing, material compositions, means, methods, or steps are included within the scope of the claims of this application.

Claims

1. A semiconductor device structure, comprising: An insulator-coated silicon region includes a semiconductor substrate, a buried oxide layer and a silicon layer, wherein the buried oxide layer is disposed on the semiconductor substrate and the silicon layer is disposed on the buried oxide layer. A first shallow trench isolation structure passes through the silicon layer and the buried oxide layer, and extends into the semiconductor substrate, wherein the first shallow trench isolation structure includes: A first pad contacts the semiconductor substrate and the silicon layer; A second liner covers the first liner and contacts the embedded oxide layer; A third pad covers the second pad, wherein the first pad, the second pad, and the third pad comprise different materials; and A first groove filling layer is disposed on the third liner and separated from the second liner by the third liner. The first pad comprises silicon oxide, the second pad comprises a nitride, and the third pad comprises silicon oxynitride; and There is a first etch selectivity between the second liner and the first trench fill layer, and a second etch selectivity between the third liner and the first trench fill layer. An oxide layer is disposed on the silicon layer of the silicon-coated region on the insulator; and A nitride layer is disposed on the oxide layer, wherein the first shallow trench isolation structure passes through the oxide layer and the nitride layer, and each sidewall of the oxide layer and each sidewall of the nitride layer are covered and contacted by the second pad of the first shallow trench isolation structure. The first shallow trench isolation structure is disposed in an array region of a memory element.

2. The semiconductor device structure of claim 1, wherein the first pad completely separates the second pad from the semiconductor substrate and the silicon layer.

3. The semiconductor device structure of claim 1, wherein the first pad has a first portion, a second portion and a third portion, the first portion and the second portion covering opposite sidewalls of the silicon layer, the third portion being disposed between the second pad and the semiconductor substrate, wherein the first portion, the second portion and the third portion of the first pad are disconnected from each other.

4. The semiconductor device structure as described in claim 1, further comprising: A second shallow trench isolation structure passes through the pad oxide layer and the pad nitride layer and extends into the semiconductor substrate, wherein the second shallow trench isolation structure includes: A second trench filling layer; and A fourth pad separates the second trench filling layer from the pad oxide layer, the pad nitride layer, and the semiconductor substrate.

5. The semiconductor device structure of claim 4, wherein the second shallow trench isolation structure is disposed in a surrounding circuit region.

6. A method for fabricating a semiconductor device structure, comprising: An oxide layer is formed on a silicon-on-insulator region, the silicon-on-insulator region including a semiconductor substrate, a buried oxide layer and a silicon layer, the buried oxide layer being formed on the semiconductor substrate and the silicon layer being formed on the buried oxide layer; A pad nitride layer is formed on the pad oxide layer; A shallow trench is formed to pass through the pad nitride layer, the pad oxide layer, the silicon layer and the buried oxide layer, and extend into the semiconductor substrate; A first pad is formed on each sidewall of the silicon layer and on a lower surface of the semiconductor substrate in the shallow trench; A second liner is formed on the first liner, wherein the second liner directly contacts each sidewall of the pad oxide layer and each sidewall of the pad nitride layer; A third pad is formed on the second pad; A groove filling layer on the third liner fills the remaining portion of the shallow groove; as well as The second pad, the third pad, and the trench fill layer are planarized to expose the pad nitride layer, wherein the remaining portion of the first pad and the second pad, the third pad, and the trench fill layer together form a shallow trench isolation structure in an array region of a memory element. The first pad comprises silicon oxide, the second pad comprises a nitride, and the third pad comprises silicon oxynitride; and There is a first etch selectivity between the second liner and the trench fill layer, and a second etch selectivity between the third liner and the trench fill layer.

7. The method for fabricating a semiconductor device structure as described in claim 6, wherein before forming the pad oxide layer, the method further comprises: An oxide layer is formed on the semiconductor substrate; as well as A silicon layer is formed on the buried oxide layer, wherein the shallow trench passes through the buried oxide layer and the silicon layer, wherein the fabrication technique of the first pad includes performing an oxide process on the silicon layer and the semiconductor substrate.

8. The method for fabricating a semiconductor device structure as described in claim 7, wherein the fabrication technique of the second pad includes a rapid thermal nitriding process, and the fabrication technique of the third pad includes an in-situ vapor generation process.

9. The method for fabricating a semiconductor device structure as claimed in claim 6, wherein before forming the pad oxide layer, it further includes forming a well region in the semiconductor substrate, wherein the well region is p-type, and a region of the semiconductor substrate below the well region is n-type, wherein after forming the shallow trench, a lower surface of the shallow trench is higher than a lower surface of the well region.

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