Method of manufacturing a semiconductor structure, semiconductor structure and semiconductor memory

Abstract

The embodiment of the present disclosure provides a preparation method of a semiconductor structure, a semiconductor structure and a semiconductor memory. The method comprises the following steps: providing a substrate, a plurality of silicon columns are formed in the substrate, and the plurality of silicon columns all extend along a first direction; in the first direction, the silicon columns comprise a first part and a second part; forming an insulating layer on the second part of the silicon column; forming a conductive layer on the first part of the silicon column; and forming a capacitive layer on the surface of the insulating layer and the conductive layer of the silicon column. In this way, in the capacitive structure, the second part of the silicon column is processed to form an insulating layer, and only the first part is formed with a conductive layer, so that the conductive area between the capacitive layer and the silicon column is reduced, so that the current can only flow through the silicon column through the conductive layer part, thereby reducing the leakage of the capacitor and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, and a semiconductor memory. Background Technology

[0002] With the development of semiconductor technology, Gate All Around (GAA), as the next-generation technology of FinField-Effect Transistor (FinFET), can further save space. Building on this, the use of three-dimensional (3D) structures has further expanded the spatial structure of semiconductor memories, greatly contributing to the development of memories such as Dynamic Random Access Memory (DRAM). Among these components, capacitors are used to store data in semiconductor memories. The data value of a memory cell is determined by the charge on its capacitor, and capacitor leakage can affect the performance of the semiconductor memory. Summary of the Invention

[0003] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor memory:

[0004] In a first aspect, embodiments of this disclosure provide a method for fabricating a semiconductor structure, comprising:

[0005] A substrate is provided in which a plurality of silicon pillars are formed, and the plurality of silicon pillars extend along a first direction; wherein, in the first direction, the silicon pillars include a first portion and a second portion;

[0006] An insulating layer is formed on the second portion of the silicon pillar;

[0007] A conductive layer is formed on the first portion of the silicon pillar;

[0008] A capacitor layer is formed on the surface of the insulating layer and the conductive layer of the silicon pillar.

[0009] In some embodiments, providing the substrate includes:

[0010] Provide an initial substrate;

[0011] A stacked structure is formed on top of the initial substrate;

[0012] The plurality of silicon pillars are formed in the stacked structure; wherein, a spacer structure is formed between the first portions of the plurality of silicon pillars.

[0013] In some embodiments, the initial substrate includes a bit line region, a transistor region, a capacitor region, and a word line region;

[0014] The formation of the plurality of silicon pillars in the stacked structure includes:

[0015] The plurality of silicon pillars are formed in the stacked structure located above the capacitor region;

[0016] When forming the plurality of silicon pillars in the stacked structure, the method further includes:

[0017] Multiple transistors are formed in the stacked structure located above the transistor region;

[0018] Multiple word line structures are formed in the stacked structure located above the word line area;

[0019] Multiple bit line structures are formed in the stacked structure located above the bit line region;

[0020] In the first direction, the plurality of bit lines, the plurality of transistors, and the plurality of silicon pillars are arranged in sequence, and in the second direction, the plurality of transistors and the plurality of word lines are arranged in sequence.

[0021] In some embodiments, a first portion of the silicon pillar is located at the connection between the silicon pillar and the corresponding adjacent transistor.

[0022] In some embodiments, the stacked structure includes at least one stacked layer, the stacked layer including a sacrificial layer and a silicon layer;

[0023] The formation of a stacked structure over the initial substrate includes:

[0024] The sacrificial layer is formed over the initial substrate, and the silicon layer is formed over the sacrificial layer;

[0025] The steps of forming the sacrificial layer and the silicon layer are repeated until the stacked structure is formed.

[0026] In some embodiments, forming the plurality of silicon pillars in the stacked structure located above the capacitor region includes:

[0027] The stacked structure is subjected to a first patterning process to form a plurality of first trenches in the stacked structure; and,

[0028] In the stacked structure located above the capacitor region, the silicon layer between the first trenches is retained to form the plurality of silicon pillars;

[0029] The first groove extends along the first direction.

[0030] In some embodiments, the method further includes:

[0031] An oxide structure is formed in the plurality of first trenches and above the stacked structure;

[0032] The oxide structure is subjected to a second patterning process to form a plurality of second trenches in the oxide structure located above the capacitor region; and,

[0033] The sacrificial layer located below the second trench is removed to form at least one support gap in the stacked structure located above the capacitor region; wherein the at least one support gap is spaced apart in the first direction and the second trench extends along the second direction;

[0034] At least one capacitor support structure is formed in the at least one support gap; wherein the silicon pillar penetrates the at least one capacitor support structure.

[0035] In some embodiments, forming an insulating layer on the second portion of the silicon pillar includes:

[0036] An isolation oxide layer is formed above the plane containing the top surface of the oxide structure;

[0037] Remove the isolation oxide layer located above the capacitor region but not above the capacitor support structure to expose the oxide structure at the corresponding location;

[0038] The oxide structure below the exposed location is removed, and the sacrificial layer above the capacitor region is removed to expose the second portion of the silicon pillar;

[0039] The surface of the second portion of the silicon pillar is oxidized to form the insulating layer.

[0040] In some embodiments, forming a conductive layer on the surface of the first portion of the silicon pillar includes:

[0041] Remove the spacer structure located on the surface of the silicon pillar to expose a first portion of the silicon pillar;

[0042] The first portion of the silicon pillar is metallized using a metallic material to form the conductive layer.

[0043] In some embodiments, the metallic material includes at least one of the following: titanium, cobalt, or nickel.

[0044] In some embodiments, when forming a plurality of second trenches in the oxide structure located above the capacitor region, the method further includes:

[0045] At least one pair of third trenches are formed in the oxide structure located above the transistor region;

[0046] In the stacked structure located above the transistor region, silicon layers are retained between the first trenches to form a plurality of active pillars; wherein the third trench extends along the second direction;

[0047] The formation of a plurality of transistors in the stacked structure located above the transistor region includes:

[0048] Remove the sacrificial layer located below the at least one pair of third trenches to form at least one pair of transistor gaps in the stacked structure located above the transistor region;

[0049] A pair of spacer structures are formed on both sides of the transistor gap;

[0050] The active pillars between the pair of spacer structures are doped to form the source and drain of the transistor;

[0051] A transistor support structure is formed between the pair of spacers;

[0052] Remove the spacer structure, sacrificial layer, and oxide structure located between the transistor support structures to expose the active pillars in the stacked structure located above the transistor region, the exposed active pillars forming the channel of the transistor;

[0053] The gate of the transistor is formed on the surface of the channel of the transistor.

[0054] In some embodiments, forming a capacitor layer on the surfaces of the insulating layer and the conductive layer of the silicon pillar includes:

[0055] A lower electrode layer is formed on the surface of the insulating layer and the conductive layer;

[0056] A dielectric layer is formed on the surface of the lower electrode layer;

[0057] An upper electrode layer is formed on the surface of the dielectric layer.

[0058] In some embodiments, after forming a capacitor layer on the surfaces of the insulating layer and the conductive layer of the silicon pillar, the method further includes:

[0059] An electrode filling structure is formed in the gap of the upper electrode layer, and the electrode filling structure completely fills the gap of the upper electrode layer.

[0060] Secondly, embodiments of this disclosure provide a semiconductor structure, including:

[0061] A substrate; a plurality of silicon pillars are formed therein, and the plurality of silicon pillars all extend along a first direction; wherein, in the first direction, the silicon pillars include a first portion and a second portion;

[0062] An insulating layer is formed in the second portion of the silicon pillar;

[0063] A conductive layer is formed in the first portion of the silicon pillar;

[0064] A capacitor layer is formed on the surface of the insulating layer and the conductive layer of the silicon pillar.

[0065] In some embodiments, the substrate includes an initial substrate and a stacked structure formed over the initial substrate; wherein the plurality of silicon pillars are formed in the stacked structure.

[0066] In some embodiments, the initial substrate includes a bit line region, a transistor region, a capacitor region, and a word line region; wherein,

[0067] The plurality of silicon pillars are formed in the stacked structure located above the capacitor region;

[0068] Multiple transistors are formed in the stacked structure located above the transistor region;

[0069] Multiple word lines are formed in the stacked structure located above the word line area;

[0070] Multiple bit lines are formed in the stacked structure located above the bit line region;

[0071] In the first direction, the plurality of bit lines, the plurality of transistors, and the plurality of silicon pillars are arranged in sequence, and in the second direction, the plurality of transistors and the plurality of word lines are arranged in sequence.

[0072] In some embodiments, a first portion of the silicon pillar is located at the connection between the silicon pillar and the corresponding adjacent transistor.

[0073] In some embodiments, at least one capacitor support structure is further formed in the stacked structure located above the capacitor region, and the silicon pillar penetrates the at least one capacitor support structure.

[0074] In some embodiments, at least one pair of transistor support structures are further formed in the stacked structure above the transistor region, the at least one pair of transistor support structures enclosing the source and drain of the transistor, a channel of the transistor is formed between the transistor support structures, and the gate of the transistor is formed on the surface of the channel.

[0075] In some embodiments, the capacitor layer includes a lower electrode layer, a dielectric layer, and an upper electrode layer; wherein,

[0076] The lower electrode layer is formed on the surface of the insulating layer and the conductive layer;

[0077] The dielectric layer is formed on the surface of the lower electrode layer;

[0078] The upper electrode layer is formed on the surface of the dielectric layer.

[0079] In some embodiments, the semiconductor structure further includes an electrode filling structure; wherein the electrode filling structure completely fills the gaps in the upper electrode layer.

[0080] In some embodiments, the conductive layer is obtained by metallizing a first portion of the silicon pillar with a metallic material; wherein the metallic material includes at least one of the following: titanium, cobalt, or nickel.

[0081] Thirdly, embodiments of this disclosure provide a semiconductor memory, including the semiconductor structure described in any of the second aspects.

[0082] This disclosure provides a method for fabricating a semiconductor structure, a semiconductor structure, and a semiconductor memory. A substrate is provided, in which a plurality of silicon pillars are formed, each extending along a first direction. Each silicon pillar includes a first portion and a second portion along the first direction. An insulating layer is formed on the second portion of the silicon pillar; a conductive layer is formed on the first portion of the silicon pillar; and a capacitor layer is formed on the surfaces of the insulating layer and the conductive layer of the silicon pillar. Thus, in the capacitor structure, by oxidizing the second portion of the silicon pillar to form the insulating layer, and retaining only the first portion of the silicon pillar to form the conductive layer, the conductive area between the capacitor layer and the silicon pillar is reduced. This allows current to flow only through the conductive layer portion of the silicon pillar, thereby reducing capacitor leakage and improving the performance of the semiconductor structure. Attached Figure Description

[0083] Figure 1 This is a schematic diagram of the composition of a semiconductor structure;

[0084] Figure 2 A schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of this disclosure;

[0085] Figure 3 A schematic diagram of the composition structure of a silicon pillar provided in an embodiment of this disclosure;

[0086] Figures 4 to 29 A schematic diagram of the structure obtained during the fabrication process of the semiconductor structure provided in the embodiments of this disclosure;

[0087] Figure 30 This is a schematic diagram of the composition of a semiconductor structure provided in an embodiment of the present disclosure;

[0088] Figure 31 This is a schematic diagram illustrating the fabrication process of a semiconductor structure according to an embodiment of the present disclosure;

[0089] Figure 32 These are schematic diagrams of two different types of capacitor structures provided in embodiments of this disclosure;

[0090] Figure 33 This is a schematic diagram of the composition structure of a semiconductor memory provided in an embodiment of this disclosure. Detailed Implementation

[0091] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the disclosure. Furthermore, it should be noted that, for ease of description, only the parts relevant to the disclosure are shown in the accompanying drawings.

[0092] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0093] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0094] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0095] The history of semiconductor technology is essentially a history of transistor size reduction. Starting with the 10-micron node in the 1970s, Moore's Law has guided us step by step to today's 5-nanometer scale. Throughout this process, whenever Moore's Law encountered difficulties, new technologies emerged to propel it forward. Specifically, GAA, as the next-generation technology of FinFET, can further save space. At the same time, the use of a 3D structure further expands the space required, greatly contributing to the development of DRAM. However, the structural design of 3D DRAM is still largely undefined, making the ingenious design of 3D DRAM extremely important.

[0096] See Figure 1 This illustrates a schematic diagram of the composition of a semiconductor structure. For example... Figure 1As shown, the semiconductor structure includes a bit line 01, a word line 02, a capacitor 03, and a transistor (not shown in the figure). The gate of the transistor is connected to the word line 02, and the source and drain of the transistor are connected to the capacitor 03 and the bit line 01, respectively. The capacitor 03 includes a silicon pillar 031 and a capacitor layer composed of a lower electrode plate 032, a dielectric layer 033, and an upper electrode plate 034. The lower electrode plate 032 is formed on the surface of the silicon pillar 031, and the silicon pillar 031 is directly connected to the lower electrode plate 032. The dielectric layer 033 is formed on the surface of the lower electrode plate 032, and the upper electrode plate 034 is formed on the surface of the dielectric layer 033. In this configuration, even if no voltage is applied to the word line 02, the capacitor 03 continuously leaks current. Figure 1 As shown, the lower electrode plate 032 continuously leaks current through the silicon pillar 031 (as indicated by the arrow in the silicon pillar), generating leakage current and affecting the performance of the semiconductor structure.

[0097] Based on this, the present disclosure provides a method for fabricating a semiconductor structure. The basic idea of ​​this method is as follows: a substrate is provided, in which a plurality of silicon pillars are formed, and the plurality of silicon pillars extend along a first direction; in the first direction, each silicon pillar includes a first portion and a second portion; an insulating layer is formed on the second portion of the silicon pillar; a conductive layer is formed on the first portion of the silicon pillar; and a capacitor layer is formed on the surfaces of the insulating layer and the conductive layer of the silicon pillar. In this way, in the capacitor structure, since the second portion of the silicon pillar is oxidized to form an insulating layer, and only the first portion of the silicon pillar is retained to form a conductive layer, the conductive area between the capacitor layer and the silicon pillar is reduced, so that the current can only flow through the conductive layer portion through the silicon pillar, thereby reducing the leakage current of the capacitor and improving the performance of the semiconductor structure.

[0098] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0099] In one embodiment of this disclosure, see [link to embodiment]. Figure 2 This illustrates a flowchart of a method for fabricating a semiconductor structure according to an embodiment of this disclosure. Figure 2 As shown, the method may include:

[0100] S101. A substrate is provided, in which a plurality of silicon pillars are formed, and the plurality of silicon pillars extend along a first direction; wherein, in the first direction, the silicon pillars include a first portion and a second portion.

[0101] It should be noted that the fabrication method provided in this disclosure is applied to the fabrication of semiconductor structures, specifically a method for reducing leakage current in 3D DRAM lateral capacitance. That is, the semiconductor structure can be a 3D semiconductor structure, mainly used in semiconductor memories such as DRAM. In fabricating this semiconductor structure, a substrate is first provided, in which multiple silicon pillars have already been formed.

[0102] See Figure 3 The diagram illustrates a schematic representation of the structure of a silicon pillar according to an embodiment of this disclosure. In diagram (a), a silicon pillar is shown, extending along a first direction and divided into a first portion and a second portion along that direction. The first direction can represent a horizontal direction, meaning that the multiple silicon pillars are all lateral silicon pillars used to form multiple lateral capacitors. In the substrate, the multiple silicon pillars can be arranged in a spatial array, specifically as shown in the diagram. Figure 3 As shown in (b) above. In this way, multiple silicon pillars arranged in this spatial array can improve the integration density of the semiconductor structure and enhance memory performance.

[0103] In some embodiments, the substrate provided for forming the substrate may include:

[0104] Provide an initial substrate;

[0105] A stacked structure is formed on top of the initial substrate;

[0106] Multiple silicon pillars are formed in a stacked structure, wherein a spacer structure is formed between the first portions of the multiple silicon pillars.

[0107] It should be noted that during substrate formation, an initial substrate is first provided, and then a stacked structure is formed on top of the initial substrate. Further, multiple silicon pillars are formed within the stacked structure, with spacer structures formed between the first portions of the multiple silicon pillars. In other words, spacer structures are formed simultaneously with or after the formation of the multiple silicon pillars to enclose the first portions of the multiple silicon pillars.

[0108] Furthermore, in this semiconductor structure, in addition to forming capacitors in the silicon pillar portion, transistors, word lines, and bit lines are also formed. Therefore, in some embodiments, the initial substrate may include bit line regions, transistor regions, capacitor regions, and word line regions;

[0109] Multiple silicon pillars may be formed in a stacked structure, including:

[0110] Multiple silicon pillars are formed in the stacked structure located above the capacitor region;

[0111] When forming multiple silicon pillars in a stacked structure, the method may further include:

[0112] Multiple transistors are formed in a stacked structure located above the transistor region;

[0113] Multiple word line structures are formed in the stacked structure located above the word line area;

[0114] Multiple bitline structures are formed in the stacked structure located above the bitline region;

[0115] In the first direction, multiple bit lines, multiple transistors, and multiple silicon pillars are arranged sequentially; in the second direction, multiple transistors and multiple word lines are arranged sequentially.

[0116] It should be noted that, Figure 4 The diagram shows the structure obtained after forming the stacked structure, where (f) is a top view of the initial substrate 10, (a) is a cross-sectional view in the AA' direction, (b) is a cross-sectional view in the FF' direction, (c) is a cross-sectional view in the CC' direction, (d) is a cross-sectional view in the DD' direction, and (e) is a cross-sectional view in the EE' direction. Additionally, in Figures 5 to 30 In the diagram, the cross-sections represented by (a), (b), (c), (d), and (e) are all related to... Figure 4 The same applies, and will not be repeated hereafter.

[0117] exist Figure 4 As shown in (f), the initial substrate 10 can be divided into bit line region 101, transistor region 102, capacitor region 103, and word line region 104. Along a first direction, bit line region 101, transistor region 102, and capacitor region 103 are arranged sequentially; along a second direction, transistor region 102 and word line region 104 are arranged sequentially. The area above bit line region 101 is used to form multiple bit lines in subsequent steps; the area above transistor region 102 is used to form multiple transistors in subsequent steps; the area above capacitor region 103 is used to form multiple capacitors in subsequent steps; and the area above word line region 104 is used to form multiple word lines in subsequent steps. Accordingly, in the final semiconductor structure, in the first direction, multiple bit lines, multiple transistors, and multiple silicon pillars are arranged sequentially; and in the second direction, multiple transistors and multiple word lines are arranged sequentially.

[0118] It should also be noted that the initial substrate 10 can be a silicon substrate or other suitable substrate materials such as silicon, germanium, silicon-germanium compounds, etc., such as doped or undoped single-crystal silicon substrates, polycrystalline silicon substrates, etc. The embodiments disclosed herein do not specifically limit this.

[0119] like Figure 4 As shown, after providing the initial substrate 10, the initial substrate 10 can be pre-cleaned first, and then a stacked structure 11 can be formed on the initial substrate 10.

[0120] In some embodiments, stacked structure 11 may include at least one stacked layer, which may include a sacrificial layer 111 and a silicon layer 112.

[0121] The stacked structure 11 formed over the initial substrate 10 may include:

[0122] A sacrificial layer 111 is formed above the initial substrate 10, and a silicon layer 112 is formed above the sacrificial layer 111;

[0123] Repeat the steps of forming the sacrificial layer 111 and the silicon layer 112 until the stacked structure 11 is formed.

[0124] It should be noted that, as Figure 4 As shown, the stacked structure 11 can be composed of alternating sacrificial layers 111 and silicon layers 112. An adjacent set of sacrificial layers 111 and silicon layers 112 is referred to as a stacked layer, in which the silicon layer 112 is formed above the sacrificial layer 111. The steps of forming one sacrificial layer 111 and one silicon layer 112 above the initial substrate 10 are repeated until the desired number of stacked layers is obtained. Exemplarily, in Figure 4 In this embodiment, the number of stacked layers is four. In practical applications, the number of stacked layers can be any number as required, and this disclosure does not impose a specific limitation on this.

[0125] It should also be noted that the material of the sacrificial layer 111 can be silicon germanide (SiGe), and the sacrificial layer 111 can be formed by epitaxy; the material of the silicon layer 112 can be silicon (Si), and the silicon layer 112 can also be formed by epitaxy; wherein, when forming the silicon layer 112, the silicon layer 112 can also be doped, and the doping method can be N doping or N+ doping.

[0126] After forming the stacked structure 11, the stacked structure 11 is subjected to processes such as patterning to form multiple silicon pillars, multiple transistors, multiple word lines, and multiple bit lines within the stacked structure 11. Specifically, the multiple silicon pillars are formed in the stacked structure 11 above the capacitor region 103, the multiple transistors are formed in the stacked structure 11 above the transistor region 102, the multiple word lines are formed in the stacked structure 11 above the word line region 104, and the multiple bit lines are formed in the stacked structure 11 above the bit line region 101.

[0127] For the formation of multiple silicon pillars, in some embodiments, multiple silicon pillars are formed in a stacked structure located above the capacitor region, which may include:

[0128] The stacked structure is first patterned to form a plurality of first trenches in the stacked structure; and,

[0129] In the stacked structure located above the capacitor region, the silicon layer between the first trenches is retained to form multiple silicon pillars;

[0130] The first groove extends along the first direction.

[0131] It should be noted that, Figure 5This is a schematic diagram of the structure obtained after forming multiple silicon pillars 13. The first patterning process for the stacked structure 11 can be performed as follows: First, a first mask layer is formed above the stacked structure 11; then, a first photoresist layer is formed above the first mask layer. The first photoresist layer has a first pattern required to form the first trenches 12. The first pattern extends along a first direction. The first pattern is transferred to the first mask layer, and the first photoresist layer is removed. Then, using the first mask layer as a mask, the first pattern is transferred to the stacked structure 11 again, and the first mask layer is removed, forming multiple first trenches 12. Additionally, as... Figure 5 As shown, the first trench 12 may also be partially formed in the substrate 10. The first mask layer can be a single-layer mask layer or a composite mask layer; for example, the first mask layer can be a composite mask layer composed of a layer of silicon oxide and a layer of silicon nitride. The first mask layer can be formed by deposition, and the first patterning process can be self-aligned double patterning (SADP) to form a first pattern extending along a first direction in the first mask layer. The first photoresist layer and the first mask layer can be removed by etching.

[0132] The method for transferring the pattern to the stacked structure 11 can be etching. Figure 5 In the stacked structure 11, the portion located directly below the first pattern is completely etched, and the portion of the initial substrate 10 located directly below the first pattern is partially etched, forming a plurality of first trenches 12 with a high aspect ratio (HAR), and the first trenches 12 extend along a first direction.

[0133] like Figure 5 As shown, after the first patterning process, a plurality of first trenches 12 are formed in the stacked structure 11. Among them, a plurality of first trenches 12 are formed above the bit line region 101, the transistor region 102 and the capacitor region 103, while above the word line region 104, first trenches 12 are formed only in a portion of the region for subsequent formation of stepped word lines.

[0134] Thus, the first trench 12 separates the sacrificial layer 111 and the silicon layer 112 in the stacked structure 11 along the second direction. In this embodiment, the first direction, the second direction, and the third direction can be mutually perpendicular directions, and the three directions form a spatial rectangular coordinate system. In this spatial rectangular coordinate system, the first direction is the horizontal x-direction, the second direction is the horizontal y-direction, and the third direction is the vertical z-direction.

[0135] In the stacked structure 11 located above the capacitor region 103, the silicon layers 112 separated by the first trench 12 form a plurality of silicon pillars 13. That is, in the stacked structure 11 located above the capacitor region 103, the silicon layers 112 remaining between the first trenches 12 form a plurality of silicon pillars 13.

[0136] It should also be noted that, while forming multiple silicon pillars 13, multiple active pillars 14 are formed in the silicon layer 112 separated by the first trench 12 in the stacked structure 11 located above the transistor region 102. That is, in the stacked structure 11 located above the transistor region 102, multiple active pillars 14 are formed in the silicon layer 112 remaining between the first trenches 12 for subsequent formation of multiple transistors. Figure 4 (b) includes the cross-section corresponding to the region where transistor region 102 is located and a partial cross-section corresponding to the region where capacitor region 103 is located. For example... Figure 4 As shown in (b), in the silicon layer 112 divided by the first trench 12, an active pillar 14 is formed in the middle of the silicon layer 112. The left side shows the part that connects the active pillar 14 to the bit line, and the right side shows a part of the silicon pillar 13.

[0137] Furthermore, the plurality of silicon pillars 13 in this embodiment can be lateral silicon pillars for forming a lateral capacitor structure. To make the capacitor structure more stable, a capacitor support structure can also be formed in the stacked structure 11. Therefore, in some embodiments, the method may further include:

[0138] An oxide structure is formed in multiple first trenches and above the stacked structure;

[0139] The oxide structure is subjected to a second patterning process to form a plurality of second trenches in the oxide structure located above the capacitor region; and,

[0140] The sacrificial layer located below the second trench is removed to form at least one support gap in the stacked structure located above the capacitor region; wherein the at least one support gap is spaced apart in a first direction and the second trench extends along a second direction;

[0141] At least one capacitor support structure is formed in at least one support gap; wherein, the silicon pillar penetrates at least one capacitor support structure.

[0142] It should be noted that multiple transistor support structures are formed simultaneously with the capacitor support structure. Therefore, in some embodiments, when forming multiple second trenches in the oxide structure located above the capacitor region, the method may further include:

[0143] At least one pair of third trenches are formed in an oxide structure located above the transistor region; in a stacked structure located above the transistor region, silicon layers between the first trenches are retained to form a plurality of active pillars; wherein the third trenches extend along a second direction;

[0144] Multiple transistors may be formed in a stacked structure located above the transistor region, including:

[0145] Remove the sacrificial layer located below at least one pair of third trenches to form at least one pair of transistor gaps in the stacked structure located above the transistor region;

[0146] A pair of spacer structures are formed on both sides of the transistor gap;

[0147] The active pillars between a pair of spacer structures are doped to form the source and drain of a transistor.

[0148] A transistor support structure is formed between a pair of spacers;

[0149] Remove the spacer structure, sacrificial layer and oxide structure located between the transistor support structures to expose the active pillars in the stacked structure above the transistor region. The exposed active pillars form the channel of the transistor.

[0150] The gate of the transistor is formed on the surface of the transistor channel.

[0151] It should be noted that, Figure 6 This is a schematic diagram of the structure obtained after forming oxide structure 15. (See diagram below.) Figure 6 As shown, the oxide structure 15 is formed in the first trench and is higher than the first trench, that is, the oxide structure 15 is also formed above the stacked structure 11. The material of the oxide structure 15 can be silicon oxide, and the oxide structure 15 can be formed by deposition or oxidation growth. After the silicon oxide is deposited, chemical mechanical polishing (CMP) can be performed to make the top surface of the oxide structure 15 flat.

[0152] After forming the oxide structure 15, the oxide structure 15 is subjected to a second patterning process to form a plurality of second trenches in the oxide structure 15. At the same time as forming the plurality of second trenches, at least one pair of third trenches are also formed in the oxide structure 15. That is, the second patterning process of the oxide structure 15 can simultaneously form a plurality of second trenches and at least one pair of third trenches in the oxide structure 15.

[0153] In this embodiment, a plurality of second trenches are formed in the oxide structure 15 located above the capacitor region 103, and at least one pair of third trenches are formed in the oxide structure 15 located above the transistor region 102, and both the second trenches and the third trenches extend along the second direction.

[0154] Multiple second trenches can be formed by first forming a second photoresist layer 16 above the oxide structure 15. Figure 7 This is a schematic diagram of the structure obtained after forming the second photoresist layer 16. Figure 7 As shown, the second photoresist layer 16 has a second pattern. Above the capacitor region 103, the second pattern includes a pattern required to form a second trench, corresponding to the region where a support gap needs to be formed. Above the transistor region 102, the second pattern includes a pattern required to form a third trench, corresponding to the region where a transistor gap needs to be formed. The second pattern extends along a second direction.

[0155] The second pattern is transferred to the oxide structure 15, and the second photoresist layer 16 is removed, forming a plurality of second trenches and at least one pair of third trenches in the oxide structure 15. The number of second trenches is the same as the number of capacitor support structures to be formed, and the number of third trenches is related to the number of transistor support structures to be formed. In this embodiment, a 1-transistor-1-capacitor (1T1C) memory cell is used as an example, where the number of transistors is the same as the number of capacitors, which is the number of silicon pillars 13. Each capacitor is connected to one transistor. The active pillars 14 at the corresponding positions of the transistor support structures are used to form the source and drain of the transistors. Therefore, a pair of transistor support structures can be formed, respectively enclosing the active pillars at the corresponding positions of the source and drain of the transistors.

[0156] like Figure 7 As shown, taking the formation of two capacitor support structures and a pair of transistor support structures as an example, above the capacitor region 103, the position corresponding to the capacitor support structure is shown as P, and the position corresponding to the transistor support structure is shown as Q.

[0157] Figure 8 This is a schematic diagram of the structure obtained after forming the second trench 17 and the third trench 18 and removing the second photoresist layer 16. The second trench 17 and the third trench 18 are formed in the oxide structure 15. The second trench 17 and the third trench 18 can be formed by etching away a portion of the oxide structure 15.

[0158] It should also be noted that, during the formation of the second trench 17 and the third trench 18, the oxide structure 15 located below the second trench 17 and the third trench 18 can be further removed, thereby exposing the sacrificial layer 111, silicon pillar 13, and active pillar 14 located below the second trench 17 and the third trench 18. Next, the sacrificial layer 111 located below the second trench 17 and the third trench 18 is also removed, thereby forming at least one support gap 19 in the stacked structure 11 above the capacitor region 103, and simultaneously forming a pair of transistor gaps 20 in the stacked structure 11 above the transistor region 102.

[0159] Figure 9 This is a schematic diagram of the structure obtained after forming the support gap 19 and the transistor gap 20. (See diagram below.) Figure 9 As shown, below the second trench 17, the silicon pillar 13 is fully exposed, and the gap around this exposed silicon pillar 13 is the support gap 19; below the third trench 18, the active pillar 14 is fully exposed, and the gap around this exposed active pillar 14 is the transistor gap 20.

[0160] A capacitor support structure is formed in the support gap 19, and a transistor support structure is formed in the transistor gap 20. These two transistor support structures are referred to as the first transistor support structure and the second transistor support structure, respectively. Both the capacitor support structure and the transistor support structure can be made of silicon nitride (SiN), and can be formed by deposition.

[0161] After forming the transistor support structure, the structure above the transistor region 102 is further processed to obtain multiple transistors. The multiple transistors can be formed by first forming a pair of spacer structures on both sides of the transistor support structure. Specifically, a third photoresist layer 23 is first formed above the isolation structure 15. The third photoresist layer 23 has a third pattern that extends along a second direction, exposing the area where the spacer structure needs to be formed. Simultaneously, the capacitor support structure and the transistor support structure can also be exposed.

[0162] Figure 10 This is a schematic diagram of the structure obtained after forming the third photoresist layer 23. It should be noted that this step is one of the steps in forming the transistor; therefore, as shown... Figure 10 As shown, the third pattern of the third photoresist layer 23 is mainly formed above the transistor region 102. Furthermore, during pattern transfer via etching, an appropriate etching selectivity can be selected to etch away only the oxide structure 15 below the exposed location, while the capacitor support structure 21 and the transistor support structures (first transistor support structure 221 and second transistor support structure 222) remain unetched. Therefore, the third photoresist layer 23 does not need to cover the capacitor support structure 21 and the transistor support structure.

[0163] The oxide structure 15 exposed by the third pattern is removed, and the sacrificial layer 111 below is further removed to form two pairs of spacers 24. Figure 11 This is a schematic diagram of the structure obtained after forming the gap 24. (See diagram below.) Figure 11 As shown, a pair of gaps 24 are formed on both sides of the first transistor support structure 221 and the second transistor support structure 222.

[0164] After the gaps 24 are formed, two pairs of spacer structures 25 are formed in the two pairs of gaps 24. The material of the spacer structure 25 can be a spin-on hard mask (SOH), and the spacer structure 25 can be formed by deposition. Figure 12 A schematic diagram of the structure obtained after forming the spacer structure 25 is shown below. Figure 12 As shown, the gap 24 is completely filled by the spacer structure 25.

[0165] Next, the transistor support structure is removed, and the transistor gap 20 is obtained again. Figure 13 This is a schematic diagram of the structure obtained after removing the transistor support structure. (See diagram below.) Figure 13 As shown, the active pillars 14 exposed by the transistor gap 20 are the parts that need to be doped to form the source and drain of the transistor.

[0166] like Figure 13 As indicated by the arrow, the active pillar 14 exposed by the transistor gap 20 is doped to form the source and drain of the transistor. The portion between the source and drain forms the transistor channel. The portion connected to the silicon pillar 13 can be either the drain or the source of the transistor. As can be seen from the preceding steps, the channel has been N-doped, and the source and drain can then be P-doped, resulting in a PMOS transistor. Alternatively, the channel can be P-doped, and the source and drain can be N-doped, resulting in an NMOS transistor. The specific type of transistor is determined based on actual conditions, and this embodiment does not impose specific limitations on this.

[0167] After the source and drain are formed, a transistor support structure is formed again in the transistor gap 20, which can be formed by depositing silicon nitride. Figure 14 This is a schematic diagram of the structure obtained after the transistor support structure is re-formed. It can be seen that... Figure 14 and Figure 12 They are basically the same, the difference is that Figure 14 The source and drain of the transistor have already been formed.

[0168] It should also be noted that, during the formation of transistors, it is also possible to... Figure 9 After forming the transistor gap 20, the active pillars 14 exposed by the transistor gap 20 are first doped to form the source and drain. Then, a transistor support structure is formed in the transistor gap 20, followed by the formation of the spacer structure as described above. In this case, it is not necessary to first form the transistor support structure, then remove the transistor support structure, and finally regenerate the transistor support structure, thus simplifying the process.

[0169] Next, the gate of the transistor is formed. In this embodiment, the gate can be a surrounding gate. The gate can be formed by first forming a fourth photoresist layer. Figure 15 A schematic diagram of the structure obtained after forming the fourth photoresist layer 26 is shown below. Figure 15 As shown. The fourth photoresist layer 26 has a fourth pattern, which exposes the spacer structure 25 and oxide structure 15 located between the first transistor support structure 221 and the second transistor support structure 222. The spacer structure 25 exposed by the fourth pattern is removed, and the fourth photoresist layer 26 is also removed, resulting in the structure shown. Figure 16 As shown. The method for removing the spacer structure 25 can be selective etching, that is, only the spacer structure 25 is removed, while the oxide structure 15 is not removed.

[0170] Next, the sacrificial layer 111 above both transistor region 102 and word line region 104 is removed. The sacrificial layer 111 can be removed using selective etching. Further, the oxide structure 15 above transistor region 102 is removed, as are the oxide structures between silicon layers 112 above word line region 104 and the oxide structure 15 above word line region 104, thereby exposing the silicon layer 112 above word line region 104. The resulting structure is as follows: Figure 17 As shown, at this point, the transistor's channel is exposed.

[0171] A first oxide layer 27 is formed on the surface of the exposed active pillar 14 (i.e., the channel), and a first oxide layer 27 is also formed between the silicon layer 112 and the oxide structure 15 retained above the word line region 104, resulting in the structure shown below. Figure 18 As shown. The first oxide layer 27 can be made of silicon oxide, and can be formed by oxidation. The first oxide layer 27 can serve as the gate dielectric layer of a transistor. Furthermore, the first oxide layer 27 and the oxide structure 15 can be made of the same material, and are therefore shown with the same fill in the figures. However, for ease of distinction, lines are added at their connection points. In this embodiment, adjacent structures made of the same material are distinguished by lines at their connection points.

[0172] Next, a first metal layer 28 is formed on the surface of the first oxide layer 27, and the resulting structure after forming the first metal layer 28 is as follows. Figure 19 As shown. The first metal layer 28 formed above the transistor region 102 (that is, the first metal layer 28 formed on the channel surface of the transistor) forms the gate of the transistor. The first metal layer 28 for forming the gate surrounds the channel portion in the source pillar 14, forming a surrounding gate; the first metal layer 28 formed above the word line region 104 forms the word line. Additionally, as... Figure 19 As shown, a second oxide layer 29 is formed above the topmost metal layer.

[0173] The specific method for forming the first metal layer can be: first, as shown in the figure... Figure 16The structure shown undergoes metal deposition, with the deposited material selectively deposited only on the surfaces of the oxide structure 15 and the first oxide layer 27. That is, the metal layer is deposited only on the surface of silicon oxide, thus forming an initial first metal layer in the structure. The deposited material can be a conductive material such as titanium nitride. Next, an initial second oxide layer is formed in the gaps and on the surface of the initial first metal layer, as well as on the entire upper surface of the structure. At this point, the entire upper surface of the structure is covered with the initial second oxide layer, and the gaps between the initial first metal layers are also completely filled with the second oxide layer. Then, the initial first metal layer and the initial second oxide layer located above the plane containing the top surface of the capacitor support structure 21 are removed, for example, by etching or CMP, resulting in the structure shown. Figure 19 The structure shown.

[0174] Next, bit lines are formed above bit line region 101. The bit lines can be formed by first removing all oxide structures 15 above bit line region 101, and then removing all sacrificial layers 111 above bit line region 101. It can be understood that during the formation of silicon pillars 13, the silicon layer 112 above bit line region 101 is actually divided into multiple silicon pillar shapes, but to distinguish it from the silicon pillars forming capacitors, the silicon pillars above bit line region 10 are still referred to as silicon layers. After the oxide structures 15 and sacrificial layers 111 are removed, all silicon layers above bit line region 10 are exposed, and a third oxide layer 30 is formed in the gaps between these exposed silicon layers. The resulting structure is as follows: Figure 20 As shown. The third oxide layer 30 is formed only above the bit line region 101. Figure 20 In the structure shown, except for the portion located above bit line region 101, the rest are all related to... Figure 19 Consistent.

[0175] exist Figure 20 A fifth photoresist layer 31 is formed on top of the structure shown. Figure 21 A schematic diagram of the structure obtained after forming the fifth photoresist layer 31 is shown below. Figure 21 As shown, above the bit line region 101, the fifth photoresist layer 31 has a fifth pattern extending along the second direction.

[0176] It should be noted that only the area above the bit line region 101 is patterned here, while the rest remains unchanged. Therefore, the fifth pattern is mainly formed above the third oxide layer 30. Specifically, directly below the fifth pattern is the segmented silicon layer 112 above the bit line region 101. Furthermore, for the same reason as above, during pattern transfer, based on the etching selectivity of different materials, only a certain fixed component of the material can be removed. Therefore, the fifth photoresist layer 31 may not be formed above the capacitor support structure 21. Above the bit line region 101, the fifth pattern is transferred, and the fifth photoresist layer 31 is removed. Thus, the third oxide layer 30 directly below the fifth pattern and the silicon layer 112 enclosed by the third oxide layer 30 are removed, forming multiple bit line trenches. A second metal layer 32 is formed in these multiple bit line trenches, and this second metal layer 32 forms multiple bit lines. The structure obtained after forming the bit lines is as follows... Figure 22 As shown. The second metal layer 32 can be formed by deposition, and the material of the second metal layer 32 can be a conductive material such as tungsten (W) or titanium nitride.

[0177] It should be noted that, at this point, a substrate comprising multiple bit lines, multiple transistors, multiple silicon pillars, and multiple word lines is obtained. Furthermore, in the embodiments of this disclosure, the formation of the multiple bit lines, multiple transistors, multiple silicon pillars, and multiple word lines can be implemented using any feasible method in the art, and no specific limitation is made thereto.

[0178] In this embodiment, a transistor is formed above the transistor region by a doped active pillar (including a channel portion, a source portion, and a drain portion), a gate dielectric layer formed on the channel portion of the active pillar, and a surrounding gate formed on the surface of the gate dielectric layer. A first portion of the silicon pillar is located at the connection point between the silicon pillar and the corresponding adjacent transistor. Thus, the conductive portion of the silicon pillar is connected to the corresponding transistor, thereby ensuring the normal electrical connection and operation of the capacitor and the transistor.

[0179] S102, An insulating layer is formed on the second part of the silicon pillar.

[0180] S103, A conductive layer is formed on the first part of the silicon pillar.

[0181] It should be noted that, in the embodiments of this disclosure, for each silicon pillar, the first part may represent the part located at the connection between the silicon pillar and the adjacent transistor, the first part is the part of the silicon pillar that needs to be conductive, and the second part represents the part of the silicon pillar that needs to be insulated.

[0182] like Figure 22As shown, in this structure, the first part of the silicon pillar is covered by the spacer structure 25 on one side of the second transistor support structure 222, and the second part of the silicon pillar is covered by the sacrificial layer 111 and the oxide structure 15 (excluding the part of the silicon pillar located inside the capacitor support structure 21). At this time, it is necessary to expose the second part of the silicon pillar to process it to form an insulating layer.

[0183] Regarding the method of forming the insulating layer, in some embodiments, forming the insulating layer on the second portion of the silicon pillar may include:

[0184] An isolation oxide layer is formed above the plane containing the top surface of the oxide structure;

[0185] Remove the isolation oxide layer located above the capacitor area but not above the support structure to expose the oxide structure at the corresponding location;

[0186] The oxide structure below the exposed location is removed, and the sacrificial layer above the capacitor region is removed to expose the second part of the silicon pillar;

[0187] The surface of the second part of the silicon pillar is oxidized to form an insulating layer.

[0188] It should be noted that when exposing the second part of the silicon pillar, firstly... Figure 22 An isolation oxide layer 33 is formed on top of the structure shown, and then a sixth photoresist layer 34 is formed on top of the isolation oxide layer 33. Figure 23 A schematic diagram of the structure obtained after forming the sixth photoresist layer 34 is shown below. Figure 23 As shown, the sixth photoresist layer 34 has a sixth pattern, which exposes the isolation oxide layer 33 located above the capacitor region 103 (excluding the isolation oxide layer 33 located above the capacitor support structure 21). Specifically, the sixth pattern is located in the region above the second portion of the plurality of silicon pillars 13. The top surfaces of the oxide structure 15 and the capacitor support structure 21 are on the same plane, and the isolation oxide layer 33 is formed above the plane containing the top surface of the oxide structure 15. Furthermore, the material of the isolation oxide layer 33 can be the same as that of the aforementioned oxide structure and oxide layer, such as silicon oxide or silicon dioxide, and it can be formed by deposition.

[0189] The sixth pattern is transferred to the isolation oxide layer 33, and the sixth photoresist layer 34 is removed. After the sixth pattern is transferred to the isolation oxide layer 33, the isolation oxide layer 33 below the sixth pattern is removed, exposing the oxide structure 15 at the corresponding position. All oxide structures 15 located below the sixth pattern are removed, and the sacrificial layer 111 is also completely removed, thereby exposing the second part of the silicon pillar, resulting in... Figure 24 The structure shown.

[0190] like Figure 24As shown, at the connection point between silicon pillar 13 and transistor (e.g.) Figure 24 As shown in the dashed box 131, the silicon pillar 13 is covered by the spacer structure 25, and this covered part is the first part of the silicon pillar 13. The part not covered by the spacer structure 25 is the second part of the silicon pillar 13. The second part is oxidized to form an insulating layer 35, and the resulting structure is as shown in the figure. Figure 25 As shown.

[0191] It should also be noted that, in the embodiments of this disclosure, the insulating layer can be formed by oxidizing the surface of the second portion of the silicon pillar to form silicon oxide as an insulating layer, or by oxidizing the entire second portion of the silicon pillar to form insulating silicon oxide. Alternatively, silicon oxide can be deposited to form an insulating layer on the surface of the second portion. Furthermore, in the embodiments of this disclosure, the oxide structure or oxide layer involved can be either silicon oxide or silicon dioxide, depending on the specific requirements and process.

[0192] After forming the insulating layer, a conductive layer is formed on the first portion of the silicon pillar. In some embodiments, forming a conductive layer on the surface of the second portion of the silicon pillar may include:

[0193] Remove the spacer structure to expose the first part of the silicon pillar;

[0194] The first part of the silicon pillar is metallized using a metallic material to form a conductive layer.

[0195] It should be noted that before forming the conductive layer, the spacer structure enclosing the first part of the silicon pillar is first removed, thereby exposing the first part of the silicon pillar. The structure obtained after removing the spacer structure is as follows. Figure 26 As shown, the dashed box indicates the first part 131 of the silicon pillar 13.

[0196] After the first part of the silicon pillar is exposed, the first part is processed to form a conductive layer on the first part of the silicon pillar. Figure 27 The diagram shows the structure obtained after forming conductive layer 36. The conductive layer can be formed by reacting a metal material with a silicon pillar to perform metal silicide treatment. The material of the resulting conductive layer is a metal silicide.

[0197] The metallic material includes at least one of the following: titanium, cobalt, or nickel.

[0198] It should be noted that when using metal materials to process the first part of the silicon pillar to obtain a conductive layer, metal materials with low resistance and good conductivity, such as titanium (Ti), cobalt (Co), or nickel (Ni), can be selected. In this way, by using these highly conductive metal materials to react with the silicon pillar, the first part of the silicon pillar is treated into a metal silicide, thus reducing the conductive area without affecting the normal performance of the semiconductor structure.

[0199] S104. A capacitor layer is formed on the surface of the insulating layer and the conductive material of the silicon pillar.

[0200] It should be noted that, in the embodiments disclosed herein, the capacitor layer refers to the electrode layer and dielectric layer of the capacitor.

[0201] Specifically, forming a capacitor layer on the surface of the insulating and conductive layers of the silicon pillar can include:

[0202] A lower electrode layer is formed on the surface of the insulating layer and the conductive layer;

[0203] A dielectric layer is formed on the surface of the lower electrode layer;

[0204] An upper electrode layer is formed on the surface of the dielectric layer.

[0205] It should be noted that, in this embodiment, the capacitor consists of a silicon pillar, an insulating layer and a conductive layer formed on the surface of the silicon pillar, and a capacitor layer, wherein the capacitor layer serves as the capacitor portion for storing data. The conductive layer, fabricated in the first portion and connected to the transistor, is used to achieve the electrical connection between the capacitor and the transistor. Due to the good conductivity of metal silicides, it does not affect the normal conductive function of the capacitor. The insulating layer, fabricated in the second portion, is non-conductive, thereby reducing capacitor leakage.

[0206] The capacitor layer consists of a lower electrode layer, a dielectric layer, and a top electrode layer. Figure 28 This is a schematic diagram of the process of forming a capacitor layer, showing a silicon pillar in the DD' direction.

[0207] like Figure 28 As shown, (1) shows that in Figure 27The silicon pillar 13 and insulating layer 35 have already been formed. (If the cross-section is the first part, then the outer edge of the silicon pillar 13 is the conductive layer 36.) (2) shows the cross-section of the silicon pillar after the formation of the lower electrode layer 37. The lower electrode layer 37 is formed on the surface of the insulating layer 35 and the conductive layer 36. A dielectric layer 38 is formed on the surface of the lower electrode layer 37, resulting in the cross-section shown in (3). The upper electrode layer 39 is then formed on the surface of the dielectric layer 38, resulting in the cross-section shown in (4). The lower electrode layer 37, the dielectric layer 38 and the upper electrode layer 39 can all be formed by deposition. The materials of the upper electrode layer 39 and the lower electrode layer 37 can all be conductive materials such as titanium nitride. The material of the dielectric layer can be a high dielectric constant (High k) material, such as hafnium oxide, zirconium oxide, lanthanum oxide, aluminum oxide, hafnium silicon oxide, hafnium nitride, etc. In the silicon pillar, the length of the second part can be greater than the length of the first part, so that the conductive part of the silicon pillar in contact with the lower electrode layer of the capacitor is smaller, reducing leakage current.

[0208] Figure 29 The schematic diagram shows the structure after the capacitor layer is formed. It can be seen that a conductive layer 36 is formed in the first part of each silicon pillar 13, and an insulating layer 35 is formed in the second part of each silicon pillar 13. A lower electrode layer 37 is formed on the surface of the conductive layer 36 and the insulating layer 35 of the silicon pillar 13. A dielectric layer 38 is formed on the surface of the lower electrode layer, and an upper electrode layer 39 is formed on the surface of the dielectric layer. A silicon pillar 13, the conductive layer 36 formed in the first part of the silicon pillar 13, the insulating layer 35 formed in the second part of the silicon pillar 13, and the lower electrode layer 37 (also called the lower electrode plate), the dielectric layer 38, and the upper electrode layer 39 (also called the upper electrode plate) sequentially formed on the surfaces of the insulating layer 35 and the conductive layer 36 constitute a capacitor (also called a capacitor structure).

[0209] In this way, in the capacitor structure, leakage current will only occur in a small area between the silicon pillar and the lower electrode layer, where the conductive layer is located. The rest of the area is insulated, which effectively reduces the leakage current of the capacitor.

[0210] Furthermore, after forming a capacitor layer on the surface of the insulating and conductive layers of the silicon pillar, the method may further include:

[0211] An electrode filling structure is formed in the gap of the upper electrode layer, and the electrode filling structure completely fills the gap of the upper electrode layer.

[0212] It should be noted that, finally, an electrode filling structure 40 is formed in the gaps of the upper electrode layer 39. Figure 30 The structure obtained after forming the electrode filling structure 40. For example... Figure 30As shown, the electrode filling structure 40 completely fills the gaps between the upper electrode layers 39. The electrode filling structure 40 can be made of polycrystalline silicon, and can be formed by deposition.

[0213] This disclosure provides a method for fabricating a semiconductor structure, comprising: providing a substrate in which a plurality of silicon pillars are formed, each silicon pillar extending along a first direction; each silicon pillar in the first direction comprising a first portion and a second portion; forming an insulating layer on the second portion of the silicon pillar; forming a conductive layer on the first portion of the silicon pillar; and forming a capacitor layer on the surfaces of the insulating layer and the conductive layer of the silicon pillar. In this capacitor structure, by forming an insulating layer on the second portion of the silicon pillar and only forming a conductive layer on the first portion, the conductive area between the capacitor layer and the silicon pillar is reduced. This allows current to flow only through the conductive layer portion of the silicon pillar, thereby reducing capacitor leakage and improving the performance of the semiconductor structure. Furthermore, the material used to form the conductive layer on the silicon pillar is a material with low resistance and good conductivity, such as titanium, cobalt, or nickel, thus maintaining good conductivity despite the reduced conductive contact area between the silicon pillar and the lower electrode layer.

[0214] In another embodiment of this disclosure, another method for fabricating a semiconductor structure is also provided. Taking a 1T1C structure as an example, the process of fabricating the semiconductor structure according to this embodiment can be simplified as follows:

[0215] See Figure 31 This illustration shows a schematic diagram of the fabrication process of a semiconductor structure provided in an embodiment of this disclosure. Figure 31 As shown:

[0216] In step 1, after the silicon pillar 13 is fabricated, the silicon pillar 13 and the transistor 41 are connected together. The connection point between the transistor 41 and the silicon pillar 13 can be the drain of the transistor 41.

[0217] In step 2, the portion of the silicon pillar 13 near the transistor 41 is covered by the wrapping structure 42, and the covered portion is the first part 131 of the silicon pillar 13. Here, the wrapping structure 42 can be entirely made of silicon oxide (or silicon dioxide). In the aforementioned embodiment, the first part of the silicon pillar 13 is covered by a spacer structure. The method of covering the first part 131 of the silicon pillar 13 can be selected according to the actual process and is not limited to the covering method provided in the embodiments of this disclosure, as long as the first part 131 of the silicon pillar 13 can be wrapped.

[0218] In step 3, the second exposed portion 122 of the silicon pillar 13 is oxidized to form an insulating layer 35.

[0219] In step 4, the wrapping structure 42 of the first part 131 of the silicon pillar 13 is removed to expose the first part 131 of the silicon pillar 13. In the aforementioned embodiment, the spacer structure of the first part 131 of the silicon pillar 13 is removed.

[0220] In step 5, the first portion 121 of the silicon pillar 13 is metallized using a metal to form a conductive layer 36.

[0221] In step 6, a capacitor layer 43 is formed on the surface of the insulating layer and the conductive layer. The capacitor layer 43 includes the aforementioned lower electrode layer, dielectric layer and upper electrode layer, thus obtaining a capacitor structure.

[0222] In addition, in the embodiments disclosed herein, when forming the capacitor layer, the capacitor layer may completely cover the capacitor head, or it may not cover the capacitor head. Figure 32 Two different types of capacitor structures are shown in the schematic diagram, such as Figure 32 As shown, when forming the upper electrode layer 39, the upper electrode layer 39 can be as follows: Figure 32 As shown in (1), the capacitor head can be wrapped, or it can be done as follows: Figure 32 As shown in (2) above, the capacitor head is not wrapped. This disclosure does not specifically limit this aspect.

[0223] This disclosure provides a method for fabricating a semiconductor structure. The specific implementation of the aforementioned embodiments has been described in detail through the above embodiments. It can be seen that in a lateral capacitor, by oxidizing a portion of the silicon pillars and metallizing the portion of the silicon pillars near the transistor drain, conductivity is increased and resistance is reduced. In this way, the lower electrode layer of the capacitor (also called the lower electrode plate) can only have charge flowing through and stored in the conductive layer portion after metallization, reducing the conductive contact area between the lower electrode plate and the silicon pillars, and reducing leakage current.

[0224] In another embodiment of this disclosure, a semiconductor structure is provided. This semiconductor structure can be prepared according to the aforementioned semiconductor structure preparation method, and the semiconductor structure can refer to... Figure 30 .like Figure 30 As shown, the semiconductor structure may include:

[0225] A substrate; a plurality of silicon pillars 13 are formed in the substrate, and the plurality of silicon pillars 13 extend along a first direction; wherein, in the first direction, the silicon pillar 13 includes a first portion and a second portion;

[0226] An insulating layer 35 is formed in the second part of the silicon pillar 13;

[0227] A conductive layer 36 is formed in the first part of the silicon pillar 13;

[0228] A capacitor layer is formed on the surface of the insulating layer 35 and the conductive layer 36 of the silicon pillar 13.

[0229] It should be noted that this semiconductor structure can be prepared according to the preparation method described in the foregoing embodiments. Figure 30 For serial numbers and structures not explicitly marked in the text, please refer to the aforementioned... Figures 3 to 29 Understand the relevant descriptions.

[0230] In some embodiments, such as Figure 30 As shown, the substrate includes an initial substrate 10 and a stacked structure 11 formed on the initial substrate 10; wherein a plurality of silicon pillars 13 are formed in the stacked structure 11.

[0231] In some embodiments, such as Figure 30 As shown, please refer to the following: Figure 4 The initial substrate 10 may include a bit line region 101, a transistor region 102, a capacitor region 103, and a word line region 104; wherein,

[0232] Multiple silicon pillars 13 are formed in a stacked structure 11 located above the capacitor region 103;

[0233] Multiple transistors are formed in a stacked structure 11 located above the transistor region 102;

[0234] Multiple character lines are formed in a stacked structure 11 located above the character line area 104;

[0235] Multiple bit lines are formed in a stacked structure 11 located above the bit line region 101;

[0236] In the first direction, multiple bit lines, multiple transistors, and multiple silicon pillars 13 are arranged sequentially, and in the second direction, multiple transistors and multiple word lines are arranged sequentially.

[0237] In some embodiments, a first portion of the silicon pillar is located at the connection between the silicon pillar and the corresponding adjacent transistor.

[0238] In some embodiments, such as Figure 30 As shown, at least one capacitor support structure 21 is also formed in the stacked structure above the capacitor region 103, and the silicon pillar 13 penetrates at least one capacitor support structure 21.

[0239] In some embodiments, at least one pair of transistor support structures are further formed in the stacked structure located above the transistor region, the source and drain of the transistor are enclosed by the at least one pair of transistor support structures, a transistor channel is formed between the transistor support structures, and the surface of the channel forms the gate of the transistor.

[0240] like Figure 30As shown, taking the formation of a pair of transistor support structures as an example, the transistor support structure includes a first transistor support structure 221 and a second transistor support structure 222. The cross-section of the transistor support structure in the second direction can be referred to the capacitor support structure 21 shown in (d).

[0241] In some embodiments, the capacitor layer may include a lower electrode layer, a dielectric layer, and an upper electrode layer; wherein...

[0242] The lower electrode layer is formed on the surface of the insulating layer and the conductive layer;

[0243] The dielectric layer is formed on the surface of the lower electrode layer;

[0244] The upper electrode layer is formed on the surface of the dielectric layer.

[0245] It should be noted that for the specific structure of the capacitor layer, please refer to... Figure 28 (4) in the middle.

[0246] In some embodiments, such as Figure 30 As shown, the semiconductor structure may further include an electrode filling structure 40; wherein the electrode filling structure 40 completely fills the gaps in the upper electrode layer.

[0247] In some embodiments, the conductive layer is obtained by metallizing a first portion of a silicon pillar with a metallic material; wherein the metallic material may include at least one of the following: titanium, cobalt, or nickel.

[0248] For details not disclosed in this embodiment, please refer to the description of the foregoing embodiments for understanding, and will not be repeated here.

[0249] This disclosure provides a semiconductor structure including a substrate; a plurality of silicon pillars formed in the substrate, all extending along a first direction; in the first direction, each silicon pillar includes a first portion and a second portion; an insulating layer formed on the second portion of the silicon pillar; a conductive layer formed on the first portion of the silicon pillar; and a capacitor layer formed on the surfaces of the insulating layer and the conductive layer of the silicon pillar. In this way, the silicon pillar used to form the capacitor is divided into a first portion and a second portion. Because the second portion of the silicon pillar is treated to form an insulating layer, and the conductive layer is formed only on the first portion, the conductive area between the capacitor layer and the silicon pillar is reduced. This allows current to flow only through the conductive layer portion of the silicon pillar, while the remaining portion is insulated, thereby reducing capacitor leakage and giving the semiconductor structure better storage performance.

[0250] In another embodiment of this disclosure, see Figure 33 This illustrates a schematic diagram of the structural composition of a semiconductor memory 200 provided in an embodiment of this disclosure. For example... Figure 33 As shown, the semiconductor memory 200 includes the semiconductor structure 100 described in any of the foregoing embodiments.

[0251] In some embodiments, the semiconductor memory 200 may be 3D DRAM.

[0252] Since the semiconductor memory 200 includes the semiconductor structure described in the foregoing embodiments, it is possible to reduce capacitor leakage and improve the performance of the semiconductor memory 200.

[0253] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure.

[0254] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0255] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0256] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0257] The features disclosed in the several product embodiments provided in this disclosure can be combined arbitrarily without conflict to obtain new product embodiments.

[0258] The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method or device embodiments.

[0259] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The method includes: A substrate is provided in which a plurality of silicon pillars are formed, and the plurality of silicon pillars extend along a first direction; wherein, in the first direction, the silicon pillars include a first portion and a second portion; An insulating layer is formed on the second portion of the silicon pillar; A conductive layer is formed on the first portion of the silicon pillar; A capacitor layer is formed on the surface of the insulating layer and the conductive layer of the silicon pillar; The provision of the substrate includes: An initial substrate is provided; the initial substrate includes a bit line region, a transistor region, a capacitor region, and a word line region; A stacked structure is formed over the initial substrate; the stacked structure includes at least one stacked layer, the stacked layer including a sacrificial layer and a silicon layer; The formation of a stacked structure over the initial substrate includes: The sacrificial layer is formed over the initial substrate, and the silicon layer is formed over the sacrificial layer; Repeat the steps of forming the sacrificial layer and the silicon layer until the stacked structure is formed; The plurality of silicon pillars are formed in the stacked structure; wherein, a spacer structure is formed between the first portions of the plurality of silicon pillars.

2. The method according to claim 1, characterized in that, The formation of the plurality of silicon pillars in the stacked structure includes: The plurality of silicon pillars are formed in the stacked structure located above the capacitor region; When forming the plurality of silicon pillars in the stacked structure, the method further includes: Multiple transistors are formed in the stacked structure located above the transistor region; Multiple word line structures are formed in the stacked structure located above the word line area; Multiple bit line structures are formed in the stacked structure located above the bit line region; In the first direction, the plurality of bit lines, the plurality of transistors, and the plurality of silicon pillars are arranged in sequence, and in the second direction, the plurality of transistors and the plurality of word lines are arranged in sequence.

3. The method according to claim 2, characterized in that, The first portion of the silicon pillar is located at the connection point between the silicon pillar and the corresponding adjacent transistor.

4. The method according to claim 2, characterized in that, The formation of the plurality of silicon pillars in the stacked structure located above the capacitor region includes: The stacked structure is subjected to a first patterning process to form a plurality of first trenches in the stacked structure; and, In the stacked structure located above the capacitor region, the silicon layer between the first trenches is retained to form the plurality of silicon pillars; The first groove extends along the first direction.

5. The method according to claim 4, characterized in that, The method further includes: An oxide structure is formed in the plurality of first trenches and above the stacked structure; The oxide structure is subjected to a second patterning process to form a plurality of second trenches in the oxide structure located above the capacitor region; and, The sacrificial layer located below the second trench is removed to form at least one support gap in the stacked structure located above the capacitor region; wherein the at least one support gap is spaced apart in the first direction and the second trench extends along the second direction; At least one capacitor support structure is formed in the at least one support gap; wherein the silicon pillar penetrates the at least one capacitor support structure.

6. The method according to claim 5, characterized in that, The formation of an insulating layer on the second portion of the silicon pillar includes: An isolation oxide layer is formed above the plane containing the top surface of the oxide structure; Remove the isolation oxide layer located above the capacitor region but not above the capacitor support structure to expose the oxide structure at the corresponding location; The oxide structure below the exposed location is removed, and the sacrificial layer above the capacitor region is removed to expose the second portion of the silicon pillar; The surface of the second portion of the silicon pillar is oxidized to form the insulating layer.

7. The method according to any one of claims 1 to 6, characterized in that, The formation of a conductive layer on the surface of the first portion of the silicon pillar includes: Remove the spacer structure located on the surface of the silicon pillar to expose a first portion of the silicon pillar; The first portion of the silicon pillar is metallized using a metallic material to form the conductive layer.

8. The method according to claim 7, characterized in that, The metallic material includes at least one of the following: titanium, cobalt, or nickel.

9. The method according to claim 5, characterized in that, When forming a plurality of second trenches in the oxide structure located above the capacitor region, the method further includes: At least one pair of third trenches are formed in the oxide structure located above the transistor region; In the stacked structure located above the transistor region, silicon layers are retained between the first trenches to form a plurality of active pillars; wherein the third trench extends along the second direction; The formation of a plurality of transistors in the stacked structure located above the transistor region includes: Remove the sacrificial layer located below the at least one pair of third trenches to form at least one pair of transistor gaps in the stacked structure located above the transistor region; A pair of spacer structures are formed on both sides of the transistor gap; The active pillars between the pair of spacer structures are doped to form the source and drain of the transistor; A transistor support structure is formed between the pair of spacers; Remove the spacer structure, sacrificial layer, and oxide structure located between the transistor support structures to expose the active pillars in the stacked structure located above the transistor region, the exposed active pillars forming the channel of the transistor; The gate of the transistor is formed on the surface of the channel of the transistor.

10. The method according to claim 1, characterized in that, The formation of a capacitor layer on the surfaces of the insulating layer and the conductive layer of the silicon pillar includes: A lower electrode layer is formed on the surface of the insulating layer and the conductive layer; A dielectric layer is formed on the surface of the lower electrode layer; An upper electrode layer is formed on the surface of the dielectric layer.

11. The method according to claim 10, characterized in that, After forming a capacitor layer on the surfaces of the insulating layer and the conductive layer of the silicon pillar, the method further includes: An electrode filling structure is formed in the gap of the upper electrode layer, and the electrode filling structure completely fills the gap of the upper electrode layer.

12. A semiconductor structure, characterized in that, The semiconductor structure includes: A substrate; the substrate includes an initial substrate and a stacked structure formed on the initial substrate; a plurality of silicon pillars are formed in the substrate, the plurality of silicon pillars are formed in the stacked structure and the plurality of silicon pillars extend along a first direction; wherein, in the first direction, the silicon pillar includes a first portion and a second portion; An insulating layer is formed in the second portion of the silicon pillar; A conductive layer is formed in the first portion of the silicon pillar; A capacitor layer formed on the surface of the insulating layer and the conductive layer of the silicon pillar; The initial substrate includes a bit line region, a transistor region, a capacitor region, and a word line region; At least one pair of transistor support structures are also formed in the stacked structure located above the transistor region. The at least one pair of transistor support structures enclose the source and drain of the transistor. A channel of the transistor is formed between the transistor support structures, and the gate of the transistor is formed on the surface of the channel.

13. The semiconductor structure according to claim 12, characterized in that, The plurality of silicon pillars are formed in the stacked structure located above the capacitor region; Multiple transistors are formed in the stacked structure located above the transistor region; Multiple word lines are formed in the stacked structure located above the word line area; Multiple bit lines are formed in the stacked structure located above the bit line region; In the first direction, the plurality of bit lines, the plurality of transistors, and the plurality of silicon pillars are arranged in sequence, and in the second direction, the plurality of transistors and the plurality of word lines are arranged in sequence.

14. The semiconductor structure according to claim 13, characterized in that, The first portion of the silicon pillar is located at the connection point between the silicon pillar and the corresponding adjacent transistor.

15. The semiconductor structure according to claim 13, characterized in that, At least one capacitor support structure is also formed in the stacked structure located above the capacitor region, and the silicon pillar penetrates the at least one capacitor support structure.

16. The semiconductor structure according to claim 12, characterized in that, The capacitor layer includes a lower electrode layer, a dielectric layer, and an upper electrode layer; wherein... The lower electrode layer is formed on the surface of the insulating layer and the conductive layer; The dielectric layer is formed on the surface of the lower electrode layer; The upper electrode layer is formed on the surface of the dielectric layer.

17. The semiconductor structure according to claim 16, characterized in that, The semiconductor structure further includes an electrode filling structure; wherein the electrode filling structure completely fills the gaps in the upper electrode layer.

18. The semiconductor structure according to any one of claims 12 to 17, characterized in that, The conductive layer is obtained by metallizing the first portion of the silicon pillar with a metallic material; wherein the metallic material includes at least one of the following: titanium, cobalt, or nickel.

19. A semiconductor memory, characterized in that, Includes the semiconductor structure as described in any one of claims 12 to 18.

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