Display panel and method for manufacturing display panel

Abstract

The present invention provides a display panel and a method for manufacturing the display panel, comprising an opening area and a non-opening area, including a substrate; an isolation flat layer located on the substrate; a TFT structural layer located on the substrate, including a TFT located in the non-opening area and provided with an opening; an anode layer located on the isolation flat layer, including an anode located in the opening area, the anode being exposed to the opening and electrically connected to the TFT; a light-emitting layer including a light-emitting portion, the light-emitting portion being located on the anode and in the opening area, and electrically connected to the anode. By directly forming the isolation flat layer on the substrate and forming the anode on the isolation flat layer, the anode is avoided from being integrated on the flat layer, thereby solving the problem that bubbles and poor flatness of the flat layer cause bulging of the anode, resulting in poor flatness of the anode, thereby affecting the display effect of the display panel, and saving a photomask of the flat layer, thereby reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a method for manufacturing the display panel. Background Art

[0002] At present, the preparation method of LED display panels usually involves making the anode after making the TFT and passivation layer. However, due to the flatness problem of the passivation layer, it is usually necessary to make another flat layer on the passivation layer to meet the flatness requirements of the anode layer. However, the flat layer still has problems with bubbles and poor flatness, resulting in bulging of the anode and other phenomena that make the anode flat, thereby affecting the display effect of the display panel. At the same time, the preparation method of the display panel uses more process steps and is more expensive. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a method for manufacturing the display panel to solve the problem that bubbles and poor flatness of a planar layer cause bulging of the anode, resulting in poor flatness of the anode, thereby affecting the display effect of the display panel.

[0004] To solve the above problems, an embodiment of the present invention provides a display panel, including an opening area and a non-opening area, including:

[0005] substrate;

[0006] an isolation flat layer, located on the substrate;

[0007] a TFT structural layer, located on the substrate, including TFTs located in the non-opening area and provided with openings;

[0008] an anode layer, located on the isolation flat layer, comprising an anode located in the opening area, the anode being exposed to the opening and electrically connected to the TFT;

[0009] The light-emitting layer includes a light-emitting portion, wherein the light-emitting portion is located on the anode and in the opening area and is electrically connected to the anode.

[0010] According to a preferred embodiment of the present invention, the material of the isolation layer includes at least one of A-Si, SiN and SiO.

[0011] According to a preferred embodiment of the present invention, it also includes a light-shielding layer located between the substrate and the TFT structure layer, the light-shielding layer includes a first light-shielding portion, the first light-shielding portion is located below the TFT and blocks at least a portion of the TFT, and the TFT is electrically connected to the anode through the first light-shielding portion.

[0012] According to a preferred embodiment of the present invention, the light shielding layer is located on the isolation flat layer, and the light shielding portion is provided in the same layer as the anode.

[0013] According to a preferred embodiment of the present invention, the light shielding layer further includes a second light shielding portion, and the second light shielding portion is provided with a through hole to expose the anode.

[0014] According to a preferred embodiment of the present invention, it also includes a buffer layer located between the light-shielding layer and the TFT structure layer, the buffer layer is provided with a first via hole and a second via hole, the anode layer also includes a connecting portion, at least part of the connecting portion is located in the first via hole, the anode is electrically connected to the first light-shielding portion through the connecting portion, and the second via hole exposes the anode.

[0015] According to a preferred embodiment of the present invention, it further includes a pixel definition layer located on the TFT structure layer, the pixel definition layer is provided with a step hole, the step hole includes a first sub-hole and a second sub-hole connected to each other, the first sub-hole is located on the second sub-hole, the aperture of the first sub-hole is larger than the aperture of the second sub-hole to form a step surface at the connection between the first sub-hole and the second sub-hole, and the second sub-hole exposes the anode and accommodates the light-emitting portion.

[0016] According to a preferred embodiment of the present invention, the pixel definition layer includes a first sublayer and a second sublayer, the first sublayer is provided with the first subpore, the second sublayer is provided with the second subpore, the material of the first sublayer is hydrophilic, and the material of the second sublayer is hydrophobic.

[0017] An embodiment of the present invention further provides a method for manufacturing a display panel, wherein the display panel includes an opening area and a non-opening area. The method includes:

[0018] forming the isolation flat layer on the substrate;

[0019] forming a light-shielding layer on the substrate, wherein the light-shielding layer includes a light-shielding portion;

[0020] forming a buffer layer on the light shielding layer, wherein the buffer layer is provided with a first via hole and a second via hole;

[0021] forming a TFT structure layer on the buffer layer, wherein the TFT structure layer includes a TFT located in the non-opening area and is provided with an opening to expose the first via hole and the second via hole, and the light shielding portion is electrically connected to the TFT and shields at least a portion of the TFT;

[0022] forming an anode layer on the substrate, wherein the anode layer includes an anode located in the opening area, the anode is exposed to the second via hole, and the light shielding portion is electrically connected to the anode through the first via hole;

[0023] The light-emitting layer is formed on the anode layer, wherein the light-emitting layer includes a light-emitting portion located on the anode.

[0024] According to a preferred embodiment of the present invention, between the step of forming an anode layer on the substrate and the step of forming the light-emitting layer on the anode layer, the method further comprises:

[0025] forming a pixel definition layer on the TFT structure layer;

[0026] The pixel definition layer is processed by a half-tone mask process so that the pixel definition layer is provided with a step hole, the step hole including a first sub-hole and a second sub-hole connected to each other, the first sub-hole is located on the second sub-hole, the aperture of the first sub-hole is larger than the aperture of the second sub-hole to form a step surface at the connection between the first sub-hole and the second sub-hole, and the second sub-hole exposes the anode.

[0027] The beneficial effects of the present invention are: by directly forming the isolation flat layer on the substrate and forming the anode on the isolation flat layer, the anode is avoided from being integrated on the flat layer, which solves the problem of poor flatness of the anode such as bulging due to bubbles and poor flatness of the flat layer, thereby affecting the display effect of the display panel, and can save a flat layer mask, thereby optimizing costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0029] Attachment Figure 1 is a schematic structural diagram of a display panel of the present invention;

[0030] Attachment Figure 2 is a partial structural schematic diagram of a display panel of the present invention;

[0031] Attachment Figure 3 is a partial structural schematic diagram of a display panel of the present invention;

[0032] Attachment Figure 4 is a schematic top view of a partial structure of a display panel of the present invention;

[0033] Attachment Figure 5 Flowchart of the method for manufacturing a display panel of the present invention. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0035] In order to solve the problem that the anode is bulging due to bubbles and poor flatness of the flat layer, which in turn affects the display effect of the display panel. Figure 1 、 2 As shown, an embodiment of the present invention provides a display panel, which can be divided into a display area and a non-display area arranged around the display area. The display area further includes an opening area K and a non-opening area NK.

[0036] The display panel includes a substrate 1, on which a TFT structure layer and an isolation flattening layer 2 are formed, wherein the TFT structure layer includes an active layer, a gate layer, and a source-drain layer in sequence in a direction away from the substrate 1, the active layer includes an active pattern 5, the gate layer includes a gate 7, the source-drain layer includes a source electrode 82 and a drain electrode 81, the active pattern 5, the gate 7, the source electrode 82, and the drain electrode 81 together constitute a TFT, the TFT is located in the non-opening area NK, and the TFT structure layer is further provided with an opening K1, the range of the opening K1 is larger than the range of the opening area K.

[0037] The display panel also includes an anode layer and a light-emitting layer. The anode layer is located on the isolation flat layer 2 and within the range of the opening K1. The anode layer includes an anode 101, and the anode 101 is located within the opening area K. The light-emitting layer includes a light-emitting portion 12, and the light-emitting portion 12 is located on the anode 101. The TFT is electrically connected to the anode 101 and the data line in the display panel, respectively, to transmit the signal of the data line to the anode 101, thereby controlling the light-emitting portion 12 to emit light.

[0038] It is known that metal ions may be contained in the manufacturing process of the substrate 1 , and the metal ions may affect the stability of the anode 101 . The isolation and flattening layer 2 can prevent the metal ions on the substrate 1 from invading the anode 101 .

[0039] In this embodiment, the isolation flat layer 2 is directly formed on the substrate 1, and the anode 101 is formed on the isolation flat layer 2. Compared with the prior art, in which a flat layer is formed on the buffer layer 4 and then the anode 101 is formed on the flat layer, the anode 101 is avoided from being formed on the flat layer, thereby solving the problem of poor flatness of the anode 101, such as bulging, caused by bubbles and poor flatness of the flat layer, which in turn affects the display effect of the display panel. At the same time, it can also save the mask for making the flat layer.

[0040] In some embodiments of the present invention, the material of the isolation flat layer 2 may include one of A-si, SiN and SiO, or a mixture of the above materials. Compared with the material of the flat layer, it can achieve better flatness and prevent the metal ions on the substrate 1 from invading the anode 101. The thickness of the isolation flat layer 2 in this embodiment is 50nm-1000nm, preferably, it can be one of 50nm, 200nm, and 1000nm, and the embodiment of the present invention does not impose specific restrictions.

[0041] In some embodiments of the present invention, Figure 1 As shown, before the TFT structure layer is formed, a light shielding layer 3 is further formed between the substrate 1 and the TFT structure layer. The light shielding layer 3 is provided on the same layer as the isolation flat layer 2 (not shown). The light shielding layer 3 includes a first light shielding portion 31. The first light shielding portion 31 is located below the TFT and is provided on the same layer as the isolation flat layer 2. Specifically, since the active layer is generally made of a photosensitive material such as IGZO, the first light shielding portion 31 is provided below the active layer to improve the stability of the TFT. To block the light coming from the direction of the substrate 1. At the same time, in some embodiments, the first light shielding portion 31 can also be electrically connected to the source 82 or the drain 81, so that the source 82 or the drain 81 can be electrically connected to the anode 101 through the first light shielding portion 31. Specifically, the first light shielding portion 31 is electrically connected to the source 82 and the anode 101 respectively, and the drain 81 is electrically connected to the data line in the display panel to transmit the signal of the data line to the anode 101, so that the light-emitting portion 12 emits light.

[0042] In some embodiments of the present invention, the metal ions on the substrate 1 not only affect the anode layer, but also affect other film layers on the substrate 1. Therefore, unlike the above embodiment in which the isolation flat layer 2 is only provided below the anode 101, this embodiment also covers the entire upper side of the substrate 1 with the isolation flat layer 2 to prevent the metal ions on the substrate 1 from affecting the stability of other film layers on the substrate 1. At this time, the shading layer 3 is provided on the isolation flat layer 2, and the first shading portion 31 is provided on the same layer as the anode 101.

[0043] In some embodiments of the present invention, Figure 4 As shown, since the anode 101 is made on the isolation flat layer 2 only after the isolation flat layer 2 is made on the substrate 1, there are no longer many film layers in the prior art between the anode 101 and the substrate 1. Therefore, the light from the substrate 1 will not be blocked, and after mixing with the light emitted by the light-emitting portion 12, it will seriously affect the display effect of the display panel. Therefore, when forming the shading layer 3, in addition to forming the first shading portion 31, a second shading portion 32 will also be formed. The second shading portion 32 is provided with a perforation to expose the anode 101, that is, the second shading portion 32 is arranged around the anode 101 to block the light from the substrate 1 around the anode 101. It can be known that the second shading portion 32 may be insulated from the first shading portion 31, or may not be insulated from the first shading portion 31, and the specific details can be determined by those skilled in the art according to needs.

[0044] In some embodiments of the present invention, Figure 2 、 3As shown, it also includes a buffer layer 4 located between the light-shielding layer 3 and the TFT structure layer, the buffer layer 4 is provided with a first via hole K2 and a second via hole K3, the first via hole K2 and the second via hole K3 are both located within the range of the opening K1 provided in the TFT structure layer, the first via hole K2 is used to expose the first light-shielding portion 31, the second via hole K3 accommodates and exposes the anode 101, the anode layer further includes a connecting portion 102, part of the connecting portion 102 is located in the first via hole K2 and is electrically connected to the first light-shielding portion 31, and part of the connecting portion 102 is located in the second via hole K3 and is electrically connected to the anode 101. It can be known that , and part of the connecting portion 102 is located on the buffer layer 4 between the first via hole K2 and the second via hole K3 to connect the connecting portion 102 located in the first via hole K2 and the second via hole K3. Through the above arrangement, the anode 101 is electrically connected to the first light shielding portion 31 through the connecting portion 102, and since the connecting portion 102 is distributed in the first via hole K2, the second via hole K3 and the buffer layer 4 between the first via hole K2 and the second via hole K3, the connecting portion 102 can fix the anode 101, prevent the anode 101 from shifting, and improve the stability of the display panel.

[0045] In some embodiments of the present invention, Figure 1 As shown, it also includes a pixel definition layer 11 located on the TFT structure layer, and the pixel definition layer 11 includes a first sublayer and a second sublayer, and the first sublayer is located on the second sublayer, wherein the first sublayer is provided with the first subhole K4, and the second sublayer is provided with the second subhole K5, the second subhole K5 exposes the anode 101 and accommodates the light-emitting portion 12, and the aperture of the first subhole K4 is larger than the aperture of the second subhole K5, therefore, a step surface will be formed at the connection between the first subhole K4 and the second subhole K5. By forming a step surface at the connection between the first subhole K4 and the second subhole K5, the ink droplets printed on the light-emitting portion 12 can leak into the second subhole K5 even if they are offset.

[0046] In some embodiments of the present invention, in order to further improve the printing effect of the ink droplets, the first sub-layer is made of a hydrophobic material, and the second sub-layer is made of a hydrophilic material.

[0047] like Figure 5 As shown, an embodiment of the present invention further provides a method for manufacturing a display panel, for manufacturing the display panel, wherein the display panel includes an opening area K and a non-opening area NK, and the method includes:

[0048] S100, forming an isolation flat layer 2 on a substrate 1. Specifically, a layer of A-Si material may be coated on the substrate 1 by a chemical vapor deposition process to form the isolation flat layer 2. In addition to A-Si, SiN and SiO may also be coated.

[0049] S200. Form a light shielding layer 3 on the substrate 1. Specifically, form the light shielding layer 3 on the isolation flat layer 2 using a physical vapor sputtering deposition method. The light shielding layer 3 may include one or more metals selected from molybdenum (Mo), aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The light shielding layer 3 may be a single-layer film or a multi-layer film. The light shielding layer 3 includes a light shielding portion. The light shielding portion includes a first light shielding portion 31. The first light shielding portion 31 is used to shield the active layer in subsequent processes. In view of the above embodiment, the light shielding portion may also include a second light shielding portion 32 for shielding the light-emitting portion 12. The second light shielding portion 32 is formed with a perforation to surround the anode 101.

[0050] S300, forming a buffer layer 4 on the light shielding layer 3. Specifically, the buffer layer 4 is formed on the light shielding layer 3 by chemical vapor deposition. The buffer layer 4 may include silicon nitride (SiN x ) and silicon oxide (SiO x ), the buffer layer 4 can prevent the penetration of unnecessary components such as impurities or moisture.

[0051] S301. After forming the buffer layer 4 on the light-shielding layer 3, patterning the buffer layer 4 so that the buffer layer 4 forms a first via hole K2 and a second via hole K3. Specifically, a dry etching process can be used to form the first via hole K2 and the second via hole K3. There is a step-shaped buffer layer 4 between the first via hole K2 and the second via hole K3. The second via hole K3 is located in the opening area K. The position of the first via hole K2 is not limited. In order to avoid excessive difficulty in making the connecting portion 102 in the subsequent process, the first via hole K2 can be set in the non-opening area NK and adjacent to the opening area K.

[0052] S400, forming a TFT structure layer on the buffer layer 4, specifically comprising the following steps:

[0053] S401. Form an active layer on the buffer layer 4 in the non-opening region NK by physical vapor sputtering deposition. The active layer includes polycrystalline silicon or an oxide semiconductor, such as any one of an oxide based on titanium (Ti), hafnium (Hf), zirconium (Zr), aluminum (Al), tantalum (Ta), germanium (Ge), zinc (Zn), gallium (Ga), tin (Sn), or indium (In), or a composite oxide thereof. Pattern the active layer to form an active pattern 5. The active pattern 5 is located above the first light shielding portion 31. The active pattern 5 may include a channel region (not shown), a source electrode 82, and a drain region. The channel region overlaps with the gate electrode 7 in a subsequent process in the thickness direction, and the orthographic projection of the channel region on the substrate 1 is located within the orthographic projection of the first light shielding portion 31 on the substrate 1. The source region and the drain region are located on one side and the other side of the channel region, respectively, corresponding to the source electrode 82 and the drain electrode 81 in a subsequent process.

[0054] S402 , forming a gate insulating layer 6 on the buffer layer 4 in the non-opening area NK by chemical vapor deposition. The gate insulating layer 6 is located on the active layer and can insulate the active pattern 5 from the gate 7 .

[0055] The gate insulating layer 6 may include silicon compounds, metal oxides, etc. For example, the gate insulating layer 6 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc. These substances may be used alone or in combination.

[0056] S403. Form a gate layer on the gate insulating layer 6, the gate layer including a gate 7. The gate 7 is located above the gate insulating layer 6 and corresponds to the channel region of the active pattern 5. The gate 7 can be made of a low-resistance material, such as one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu), but is not limited thereto.

[0057] S404: Form an interlayer insulating layer 13 on the buffer layer 4 in the non-opening region NK. The interlayer insulating layer 13 may cover not only the upper surface of the gate 7 but also the side surfaces of the gate 7. The interlayer insulating layer 13 may include a silicon compound, a metal oxide, etc. For example, the interlayer insulating layer 13 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, tantalum oxide, hafnium oxide, zirconium oxide, titanium oxide, etc.

[0058] S405: Forming a source and drain layer. A plurality of openings are formed by opening holes K1 in the interlayer insulating layer 13 and the buffer layer 4 through a photolithography process. Then, a source electrode 82 and a drain electrode 81 are formed on the interlayer insulating layer 13 through physical vapor deposition. The source electrode 82 and the drain electrode 81 are connected to the corresponding source and drain regions of the active layer through the openings. The source electrode 82 or the drain electrode 81 is also electrically connected to the first light shielding portion 31 through the openings. The source and drain side layers may include one or more metals selected from molybdenum (Mo), aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), calcium (Ca), titanium (Ti), tantalum (Ta), tungsten (W), and copper (Cu). The gate 7, source electrode 82, drain electrode 81, and active pattern 5 form a TFT located within the non-opening region NK.

[0059] S406 , forming a passivation layer 9 on the source and drain electrode layers. The passivation layer 9 may include inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, hafnium oxide, aluminum oxide, titanium oxide, tantalum oxide, and zinc oxide.

[0060] In the above steps, the interlayer insulating layer 13 is further etched after the interlayer insulating layer 13 is formed, and the passivation layer 9 is etched after the passivation layer 9 is formed, so as to form an opening K1 in the TFT structure layer, wherein the opening K1 exposes the first via hole K2 and the second via hole K3, and the range of the opening K1 may be larger than the range of the opening area K.

[0061] S500. An anode layer is formed on the substrate 1. Specifically, an anode 101 is formed in the second via hole K3, and a connecting portion 102 is formed in both the first via hole K2 and the second via hole K3 for connecting the first light shielding portion 31 and the anode 101. The anode 101 may have a laminated film structure of a material layer having a high work function, such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), or a mixture thereof, but is not limited thereto. In this embodiment, the anode 101 is made of a metal process having a light shielding effect, such as Ag.

[0062] S600: Form a pixel definition layer 11 on the passivation layer 9. The pixel definition layer may include resins such as polyacrylates or polyimides and inorganic materials such as silica. The pixel definition layer may absorb external light by including black pigments and / or dyes, thereby reducing the reflectivity of external light and improving the contrast of the display device. The pixel definition layer 11 is processed by a half-tone mask process so that the pixel definition layer 11 is provided with a step hole. The step hole includes a first sub-hole K4 and a second sub-hole K5 that are interconnected. The first sub-hole K4 is located above the second sub-hole K5. The aperture of the first sub-hole K4 is larger than the aperture of the second sub-hole K5 to form a step surface at the connection between the first sub-hole K4 and the second sub-hole K5. The second sub-hole K5 exposes the anode 101.

[0063] S700, forming the light-emitting layer on the anode layer, wherein the light-emitting layer includes a light-emitting portion 12 located on the anode 101, and the light-emitting layer may include an organic light-emitting layer, and may also include a hole injection / transport layer and / or an electron injection / transport layer.

[0064] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A display panel comprising an opening area and a non-opening area, characterized in that: include: substrate; an isolation flat layer, located on the substrate; a TFT structural layer, located on the substrate, including TFTs located in the non-opening area and provided with openings; an anode layer, located on the isolation flat layer, comprising an anode located in the opening area, the anode being exposed to the opening and electrically connected to the TFT; a light-emitting layer, comprising a light-emitting portion, the light-emitting portion being located on the anode and within the opening region and electrically connected to the anode; a light shielding layer located between the substrate and the TFT structure layer, the light shielding layer comprising a first light shielding portion, the first light shielding portion shielding at least a portion of the TFT, the TFT structure layer being electrically connected to the anode via the first light shielding portion; a buffer layer, located between the light shielding layer and the TFT structure layer, the buffer layer being provided with a first via hole and a second via hole, wherein the second via hole exposes the anode; In which, the anode layer also includes a connecting portion, and the anode is electrically connected to the first shading portion through the connecting portion; at least part of the connecting portion is located in the first via hole, at least part of the connecting portion is located in the second via hole, and at least part of the connecting portion is located on the buffer layer between the first via hole and the second via hole to connect the connecting portions located in the first via hole and the second via hole.

2. The display panel according to claim 1, wherein: The material of the isolation planarization layer includes at least one of A-Si, SiN and SiO.

3. The display panel according to claim 1, wherein: The light shielding layer is located on the isolation flat layer, and the light shielding portion is provided on the same layer as the anode.

4. The display panel according to claim 1, wherein: The light shielding layer further includes a second light shielding portion, wherein the second light shielding portion is provided with a through hole to expose the anode.

5. The display panel according to claim 1, wherein: It also includes a pixel definition layer located on the TFT structure layer, the pixel definition layer is provided with a step hole, the step hole includes a first sub-hole and a second sub-hole connected to each other, the first sub-hole is located on the second sub-hole, the aperture of the first sub-hole is larger than the aperture of the second sub-hole to form a step surface at the connection between the first sub-hole and the second sub-hole, and the second sub-hole exposes the anode and accommodates the light-emitting portion.

6. The display panel according to claim 5, wherein: The pixel definition layer includes a first sublayer and a second sublayer. The first sublayer is provided with the first subhole, and the second sublayer is provided with the second subhole. The material of the first sublayer is hydrophilic, and the material of the second sublayer is hydrophobic.

7. A method for manufacturing a display panel, for manufacturing a display panel, wherein the display panel includes an opening area and a non-opening area, characterized in that: The method comprises: forming an isolation planarization layer on the substrate; forming a light-shielding layer on the substrate, wherein the light-shielding layer includes a light-shielding portion; forming a buffer layer on the light shielding layer, wherein the buffer layer is provided with a first via hole and a second via hole; forming a TFT structure layer on the buffer layer, wherein the TFT structure layer includes a TFT located in the non-opening area and is provided with an opening to expose the first via hole and the second via hole, and the light shielding portion is electrically connected to the TFT and shields at least a portion of the TFT; forming an anode layer on the substrate, wherein the anode layer includes an anode located in the opening area, the anode is exposed to the second via hole, and the light shielding portion is electrically connected to the anode through the first via hole; forming a light-emitting layer on the anode layer, wherein the light-emitting layer includes a light-emitting portion located on the anode; In which, the anode layer also includes a connecting portion, and the anode is electrically connected to the shading portion through the connecting portion; at least part of the connecting portion is located in the first via hole, at least part of the connecting portion is located in the second via hole, and at least part of the connecting portion is located on the buffer layer between the first via hole and the second via hole to connect the connecting portions located in the first via hole and the second via hole.

8. The method for manufacturing a display panel according to claim 7, wherein: Between the step of forming an anode layer on the substrate and the step of forming the light-emitting layer on the anode layer, the method further includes: forming a pixel definition layer on the TFT structure layer; The pixel definition layer is processed by a half-tone mask process so that the pixel definition layer is provided with a step hole, the step hole including a first sub-hole and a second sub-hole connected to each other, the first sub-hole is located on the second sub-hole, the aperture of the first sub-hole is larger than the aperture of the second sub-hole to form a step surface at the connection between the first sub-hole and the second sub-hole, and the second sub-hole exposes the anode.

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