A breakdown voltage measurement circuit and a breakdown voltage measurement device

Abstract

The present invention discloses a breakdown voltage measurement circuit and a breakdown voltage measurement device. In the circuit, when a transistor is connected to the breakdown voltage measurement circuit, a current measurement circuit is connected to the first electrode of the transistor, and a high-voltage power supply circuit and a voltage measurement circuit are connected to the second electrode of the transistor; a current detection circuit is respectively connected to the high-voltage power supply circuit, the current measurement circuit, and the voltage measurement circuit; the high-voltage power supply circuit is adapted to output a step-by-step increasing pulse voltage signal to the transistor; the current measurement circuit is adapted to measure the current signal of the transistor and send it to the current detection circuit; the voltage measurement circuit is adapted to measure the breakdown voltage of the transistor; and the current detection circuit is adapted to send a breakdown voltage measurement signal to the voltage measurement circuit and a stop-operation signal to the high-voltage power supply circuit when the value of the received current signal of the transistor is greater than a preset rated current value. The circuit implementation logic is simple, reduces cost, is conducive to miniaturization, and achieves accurate and effective measurement of the breakdown voltage.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and in particular to a breakdown voltage measurement circuit and a breakdown voltage measurement device. Background Art

[0002] With the development of transistors, various semiconductor devices including optocouplers are being used in large quantities, making the application of integrated circuits in various fields more and more extensive. When producing optocouplers, it is necessary to ensure the reliability of various components and it is necessary to test its transistor elements including diodes and triodes to ensure their normal performance. During testing, a transistor tracer is usually used to measure the breakdown voltage of the diode. When testing the output of the optocoupler with an open collector, it is often necessary to test the breakdown voltage between the collector and emitter of the triode. When measuring the breakdown voltage of the diode, the anode and cathode of the diode are respectively connected to the transistor tracer. When testing the breakdown voltage of the triode, the base of the triode is open, and the collector and emitter of the triode are connected to the transistor tracer. In the embodiment of the present invention, for the convenience of description, the anode of the diode and the emitter of the triode can be referred to as the first electrode of the transistor, and the cathode of the diode and the collector of the triode can be referred to as the second electrode of the transistor. Summary of the Invention

[0003] The inventors have discovered that conventional transistor tracers require complex circuit designs, large size, and high cost to ensure accurate measurements. In light of these issues, the present invention provides a breakdown voltage measurement circuit and device that overcome or at least partially address these issues.

[0004] In a first aspect, an embodiment of the present invention provides a breakdown voltage measurement circuit, comprising: a high-voltage power supply circuit, a current measurement circuit, a voltage measurement circuit, and a current detection circuit;

[0005] When the transistor is connected to the breakdown voltage measurement circuit, the current measurement circuit is connected to a first electrode of the transistor, and the high-voltage power supply circuit and the voltage measurement circuit are connected to a second electrode of the transistor;

[0006] The current detection circuit is respectively connected to the high-voltage power supply circuit, the current measurement circuit and the voltage measurement circuit;

[0007] The high-voltage power supply circuit is suitable for outputting a step-by-step increasing pulse voltage signal to the transistor;

[0008] The current measurement circuit is adapted to measure the current signal of the transistor and send the current signal to the current detection circuit;

[0009] The voltage measurement circuit is adapted to measure the breakdown voltage of the transistor;

[0010] The current detection circuit is adapted to send a breakdown voltage measurement signal to the voltage measurement circuit and a stop operation signal to the high-voltage power supply circuit when the value of the received current signal of the transistor is greater than a preset rated current value.

[0011] In one or some optional embodiments, the high-voltage power supply circuit includes: a step signal generator, a first operational amplifier, a first MOS transistor, a second MOS transistor, a third MOS transistor, a transformer, a voltage doubling circuit, a second operational amplifier, a first capacitor, a first resistor, a second resistor, and a PWM control chip;

[0012] The non-inverting input terminal of the first operational amplifier is grounded, the inverting input terminal of the first operational amplifier is connected to the step signal generator and the output terminal of the second operational amplifier respectively, and the output terminal of the first operational amplifier is connected to the gate of the third MOS transistor;

[0013] The source of the third MOS transistor is connected to the input voltage, and the drain of the third MOS transistor is connected to the source of the first MOS transistor;

[0014] The gate of the first MOS transistor is connected to the input voltage and the second output terminal of the PWM control chip, and the drain of the first MOS transistor is connected to the drain of the second MOS transistor;

[0015] The gate of the second MOS transistor is connected to the first output terminal of the PWM control chip and is grounded, and the drain of the second MOS transistor is connected to the third terminal of the transformer and is grounded;

[0016] The first end of the transformer is connected between the drain of the first MOS transistor and the drain of the second MOS transistor, the second end and the fourth end of the transformer are respectively connected to the input end of the voltage doubler circuit, the output end of the voltage doubler circuit is connected to the non-inverting input end of the second operational amplifier via the first capacitor C15, and the output end of the voltage doubler circuit is connected to the inverting input end of the second operational amplifier via the first resistor R14;

[0017] The non-inverting input terminal of the second operational amplifier is grounded;

[0018] A second resistor R19 is connected between the inverting input terminal and the output terminal of the non-inverting input terminal of the second operational amplifier;

[0019] The step signal generator is capable of outputting a first constant voltage signal or a first pulse voltage signal;

[0020] The PWM control chip can output a preset waveform signal.

[0021] In one or some optional embodiments, the current detection circuit includes: an absolute value circuit, a fourth operational amplifier, a twentieth resistor, a twenty-first resistor, a comparator, and a control unit;

[0022] One end of the absolute value circuit is connected to the current measurement circuit, and the other end is connected to the non-inverting input terminal of the fourth operational amplifier;

[0023] The inverting input terminal of the fourth operational amplifier is grounded via the twentieth resistor, the twenty-first resistor is connected between the inverting input terminal and the output terminal of the fourth operational amplifier, and the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the comparator;

[0024] The non-inverting input terminal of the comparator is connected to the comparison reference voltage terminal, and the output terminal of the comparator is connected to the control unit;

[0025] The control unit is connected to the voltage measurement circuit and the high-voltage power supply circuit, and is used to send a breakdown voltage measurement signal to the voltage measurement circuit and a stop working signal to the high-voltage power supply circuit when it is determined that the output signal level of the comparator is inverted.

[0026] In one or some optional embodiments, the absolute value circuit includes a sixth operational amplifier and a seventh operational amplifier;

[0027] The output terminal of the sixth operational amplifier is connected to the non-inverting input terminal of the fourth operational amplifier via a twenty-second resistor, a twenty-third resistor and a thirteenth capacitor are connected in parallel between the inverting input terminal and the output terminal of the sixth operational amplifier, the inverting input terminal of the sixth operational amplifier is connected to the output terminal of the seventh operational amplifier via a twenty-fourth resistor and a fourth diode, and the inverting input terminal of the sixth operational amplifier is connected to the current measurement circuit via a twenty-fifth resistor;

[0028] The non-inverting input terminal of the seventh operational amplifier is grounded via a twenty-sixth resistor, the inverting input terminal of the seventh operational amplifier is connected to the current measurement circuit via a twenty-seventh resistor, a fifth diode is connected between the output terminal and the inverting input terminal of the seventh operational amplifier, and a twenty-eighth resistor is connected between the inverting input terminal of the seventh operational amplifier and the common terminal of the twenty-fourth resistor and the fourth diode.

[0029] In one or some optional embodiments, a twenty-ninth resistor is connected between the non-inverting input terminal of the comparator and the comparison reference voltage terminal;

[0030] A thirtieth resistor is connected between the output terminal of the fourth operational amplifier and the inverting input terminal of the comparator.

[0031] In one or some optional embodiments, the voltage measurement circuit includes: an eighth operational amplifier and a sample-and-hold unit;

[0032] The non-inverting input terminal of the eighth operational amplifier is connected to the high-voltage power supply circuit via a thirty-first resistor, a negative feedback resistor unit is connected between the inverting input terminal and the output terminal of the eighth operational amplifier, and the output terminal of the eighth operational amplifier is connected to the signal output terminal of the sampling and holding unit via a thirty-second resistor;

[0033] The logic signal terminal of the sampling and holding unit is connected to the current detection circuit, and the output terminal of the sampling and holding unit is externally connected to a voltage measurement unit;

[0034] The sampling and holding unit is used to perform sampling and holding when receiving the breakdown voltage measurement signal of the current detection circuit, and send the sampling and holding signal to the voltage measurement unit.

[0035] In one or some optional embodiments, the negative feedback resistor unit includes a first negative feedback resistor, a switch, and a second negative feedback resistor connected in sequence.

[0036] In one or some optional embodiments, the negative feedback resistance unit further includes: a compensation capacitor; the compensation capacitor is connected in parallel between the inverting input terminal and the output terminal of the eighth operational amplifier.

[0037] In one or some optional embodiments, the current measurement circuit includes: a tenth operational amplifier, an eleventh operational amplifier, a twelfth operational amplifier, a current driving circuit, and at least one set of negative feedback resistor circuits;

[0038] The non-inverting input terminal of the tenth operational amplifier is connected to the first electrode of the transistor, a thirty-fifth resistor is connected between the inverting input terminal and the output terminal of the tenth operational amplifier, and the output terminal of the tenth operational amplifier is connected to the inverting input terminal of the eleventh operational amplifier via a thirty-sixth resistor;

[0039] The non-inverting input terminal of the eleventh operational amplifier is grounded, a thirty-seventh resistor is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier, and the output terminal of the eleventh operational amplifier is connected to the inverting input terminal of the twelfth operational amplifier via a thirty-eighth resistor;

[0040] The non-inverting input terminal of the twelfth operational amplifier is grounded; a thirty-ninth resistor is connected between the inverting input terminal and the output terminal of the twelfth operational amplifier, and the output terminal of the third operational amplifier is connected to the current detection circuit;

[0041] One common end of the at least one group of negative feedback resistor circuits is connected to the first electrode of the transistor, and the other common end is connected to the common end of the thirty-eighth resistor and the thirty-ninth resistor via the fortieth resistor R40;

[0042] One end of the current driving circuit is connected to the first electrode of the transistor, and the other end is connected to the common end of the at least one group of negative feedback resistor circuits and the fortieth resistor.

[0043] In a second aspect, an embodiment of the present invention provides a breakdown voltage measurement device, comprising: the breakdown voltage measurement circuit described in any one of the above items.

[0044] The beneficial effects of the above technical solutions provided by the embodiments of the present invention include at least:

[0045] The breakdown voltage measurement circuit provided by an embodiment of the present invention utilizes a high-voltage power supply circuit to provide a step-by-step pulse voltage to a transistor, and measures the current flowing through the transistor via a current measurement circuit. When the transistor breaks down, the current measured by the current measurement circuit increases instantaneously. A current detection circuit connected to the current measurement circuit determines that the value of the transistor's current signal is greater than a preset rated current value, sends a stop signal to the high-voltage power supply circuit, and sends a breakdown voltage measurement signal to the voltage measurement circuit, thereby measuring the breakdown voltage of the transistor. The circuit implementation logic is simple, does not require complex circuit design, reduces circuit cost, and facilitates the miniaturization of measurement devices utilizing the breakdown voltage measurement circuit. The circuit has a simple circuit structure, is easy to operate, and provides convenient and fast measurement with high stability, enabling accurate and effective measurement of the breakdown voltage of the transistor.

[0046] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0047] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0049] Figure 1 A schematic structural diagram of a breakdown voltage measurement circuit provided in an embodiment of the present invention;

[0050] Figure 2 A schematic structural diagram of a high-voltage power supply circuit provided in an embodiment of the present invention;

[0051] Figure 3 A schematic diagram of a local circuit structure of a high-voltage power supply including a PWM control chip provided in an embodiment of the present invention;

[0052] Figure 4 A schematic structural diagram of a current detection circuit provided by an embodiment of the present invention;

[0053] Figure 5 A schematic diagram of the structure of a voltage measurement circuit provided by an embodiment of the present invention;

[0054] Figure 6 A schematic structural diagram of a current measurement circuit provided in an embodiment of the present invention;

[0055] Figure 7 for Figure 6 Schematic diagram of the current driving circuit structure of the current measurement circuit shown. DETAILED DESCRIPTION

[0056] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0057] In order to illustrate the technical solution of the present invention, specific embodiments are provided below.

[0058] Example 1

[0059] The embodiment of the present invention provides a breakdown voltage measurement circuit, referring to Figure 1 As shown, it includes: a high-voltage power supply circuit 1, a current measurement circuit 2, a voltage measurement circuit 3 and a current detection circuit 4;

[0060] When the transistor is connected to the breakdown voltage measurement circuit, the current measurement circuit 2 is connected to the first electrode of the transistor, and the high-voltage power supply circuit 1 and the voltage measurement circuit 3 are connected to the second electrode of the transistor;

[0061] The current detection circuit 4 is connected to the high-voltage power supply circuit 1, the current measurement circuit 2 and the voltage measurement circuit 3 respectively;

[0062] The high-voltage power supply circuit 1 is suitable for outputting a step-by-step increasing pulse voltage signal to the transistor;

[0063] The current measurement circuit 2 is adapted to measure the current signal of the transistor and send the signal to the current detection circuit 4;

[0064] The voltage measurement circuit 3 is suitable for measuring the breakdown voltage of the transistor;

[0065] The current detection circuit 4 is adapted to send a breakdown voltage measurement signal to the voltage measurement circuit 3 and a stop operation signal to the high-voltage power supply circuit 1 when the value of the received current signal of the transistor is greater than a preset rated current value.

[0066] The breakdown voltage measurement circuit provided by the embodiment of the present invention uses a high-voltage power supply circuit 1 to provide a step-by-step pulse voltage to the cathode of the diode (the collector of the transistor). The anode of the diode (the emitter of the transistor) is connected to the current measurement circuit 2. The current flowing through the transistor is continuously measured by the current measurement circuit 2 and the measured current value is sent to the current detection circuit 4. When the transistor breaks down, the current measured by the current measurement circuit 2 increases instantaneously. The current detection circuit 4 connected to the current measurement circuit 2 determines that the value of the current signal of the transistor is greater than the preset rated current value, sends a stop signal to the high-voltage power supply circuit 1, setting the output of the high-voltage power supply circuit 1 to zero, and sends a breakdown voltage measurement signal to the voltage measurement circuit 3, so that the breakdown voltage of the transistor is measured by the voltage measurement circuit 3. The circuit implementation logic is simple, thus eliminating the need for complex circuit design, reducing circuit cost, and facilitating the miniaturization of a measurement device using the breakdown voltage measurement circuit. The circuit structure is simple, easy to operate, convenient and fast to measure, and highly stable, and can achieve accurate and effective measurement of the breakdown voltage of the transistor.

[0067] As a specific implementation of the embodiment of the present invention, refer to Figure 2 As shown, the high-voltage power supply circuit 1 includes: a step signal generator, a first operational amplifier U1, a first MOS transistor Q1, a second MOS transistor Q2, a third MOS transistor Q3, a transformer T1, a voltage doubling circuit, a second operational amplifier U2, a first capacitor C1, a first resistor R1, a second resistor R2 and a PWM control chip U3;

[0068] The non-inverting input terminal of the first operational amplifier U1 is grounded, the inverting input terminal of the first operational amplifier U1 is connected to the output terminals of the step signal generator and the second operational amplifier U2 respectively, and the output terminal of the first operational amplifier U1 is connected to the gate of the third MOS transistor Q3;

[0069] The source of the third MOS transistor Q3 is externally connected to the input voltage terminal, and the drain of the third MOS transistor Q3 is connected to the source of the first MOS transistor Q1;

[0070] The gate of the first MOS transistor Q1 is connected to the input voltage terminal and the second output terminal DV2 of the PWM control chip U3, and the drain of the first MOS transistor Q1 is connected to the drain of the second MOS transistor Q2;

[0071] The gate of the second MOS transistor Q2 is connected to the first output terminal DV1 of the PWM control chip U3 and is grounded, and the drain of the second MOS transistor Q2 is connected to the third terminal of the transformer T1 and is grounded;

[0072] The first end of the transformer T1 is connected between the drain of the first MOS transistor Q1 and the drain of the second MOS transistor Q2, and the second end and the fourth end of the transformer T1 are respectively connected to the input end of the voltage doubling circuit;

[0073] The output end of the voltage doubling circuit is connected to the non-inverting input end of the second operational amplifier U2 via the first capacitor C1, and is connected to the inverting input end of the second operational amplifier U2 via the first resistor R1;

[0074] The non-inverting input terminal of the second operational amplifier U2 is grounded, and a second resistor R2 is connected between the inverting input terminal and the output terminal of the second operational amplifier U2; the resistance of the first resistor R1 is greater than the resistance of the second resistor R2;

[0075] The step signal generator can output a preset constant voltage signal or a pulse voltage signal;

[0076] The PWM control chip U3 can output a preset square wave signal.

[0077] In an embodiment of the present invention, the step signal generator can be implemented using a digital-to-analog converter (DA) chip. By controlling the input digital signal, the DA chip outputs a pulse voltage signal, which can be a step-increasing signal. By varying the input digital signal according to a preset period, the desired pulse voltage signal can be generated. For example, by varying the input digital signal according to a 1ms period, an output pulse voltage signal with a 1ms interval can be generated.

[0078] In the embodiment of the present invention, a push-pull circuit is formed by the first MOS transistor Q1 and the second MOS transistor Q2. In order to prevent the first MOS transistor Q1 and the second MOS transistor Q2 from being turned on at the same time, the square wave signal output by the PWM control chip U3 needs to be set with a dead time and a reasonable duty cycle. Based on this, the specific model and specifications of the PWM control chip U3 can be selected according to the actual circuit requirements, for example, it can be an SG3525 chip. Figure 3As shown, the models and specifications of the components in the circuit can be set according to the guidance of the SG3525 device manual, so that the first output terminal DV1 and the second output terminal DV2 of the SG3525 chip can output square wave signals with appropriate duty cycle and dead time. Specifically, the sizes of R16, R17, C7 and C8 can be selected according to the duty cycle requirements, and the desired square wave waveform can be adjusted by selecting R18, C9, C10, C11 and adjusting the resistance value of potentiometer RV2. At the same time, the frequency can be adjusted by adjusting the resistance value of potentiometer RV1.

[0079] In the embodiment of the present invention, a square wave signal with a suitable duty cycle and dead time is outputted through the first output terminal DV1 and the second output terminal DV2 of the PWM control chip U3. The first MOS transistor Q1 and the second MOS transistor Q2 cause the primary coil of the transformer T1 to generate a corresponding square wave. Then, a geometrically amplified square wave is generated in the secondary coil of the transformer T1. Then, the voltage outputted by the transformer T1 is amplified by the voltage doubling circuit to obtain the output voltage of the high-voltage power supply circuit 1.

[0080] In the embodiment of the present invention, the transformation ratio of the transformer T1 can be selected according to actual needs, for example, a transformer with a transformation ratio of 500 or 1000 can be selected.

[0081] In a specific embodiment, referring to Figure 2 As shown, the voltage doubling circuit may be a half-bridge voltage doubling circuit, and the half-bridge voltage doubling circuit includes a first diode D1, a second diode D2, a second capacitor C2, and a third capacitor C3;

[0082] The first diode D1 and the second diode D2 are connected in reverse parallel, the second capacitor C2 is connected to the third terminal of the transformer T1 and the common terminal of the first diode D1 and the second diode D2, and the third capacitor C3 is connected between the anode of the first diode D1 and the cathode of the second diode D2. Figure 2 The half-bridge voltage doubling circuit shown can achieve the output voltage of the transformer T1 to be amplified by two times to obtain the output voltage HVOUT+. Those skilled in the art can also choose other ways to implement the voltage doubling circuit according to actual circuit requirements, and can also change the model and specifications of the first diode D1, the second diode D2, the second capacitor C2 and the third capacitor C3. Figure 2 The specific implementation process of the amplification factor of the half-bridge voltage doubler circuit shown can be referred to the detailed description of the relevant technology, which will not be repeated here.

[0083] Reference Figure 2As shown, the high-voltage current circuit also includes a resistor matrix disposed between the voltage output terminal and the output terminal of the voltage multiplier circuit. This resistor matrix is ​​a current-limiting resistor matrix. By configuring the current-limiting resistor matrix, a preset output voltage HVSOUT is obtained. By configuring the resistor matrix, current is limited, circuit short circuits are prevented, and the high-voltage power supply and components under test are protected.

[0084] The resistance matrix described in the embodiment of the present invention can be composed of a series of relay switches and resistors connected in series and parallel. By controlling the on and off of different relay switches, the resistance value connected to the high-voltage power supply circuit 1 is controlled. The specific control method of the resistance matrix and its relay switches can be implemented according to the detailed description of the relevant technology and will not be repeated here.

[0085] In the embodiment of the present invention, referring to Figure 2 As shown, the first MOS transistor Q1 is a PNP-type MOS transistor, and the second MOS transistor Q2 is an NPN-type MOS transistor. The voltage input terminal continuously provides voltage to the gate of the first MOS transistor Q1. If the first MOS transistor Q1 is to be turned on, its gate needs to be at a low level. Since the first output terminal DV1 and the second output terminal DV2 of the SG3525 chip are non-inverting terminals, in order to achieve control of the first MOS transistor Q1 and the second MOS transistor Q2, the second output terminal DV2 can also be connected to an inverting circuit. The inverting circuit inverts the output waveform of the second output terminal DV2. When the second output terminal DV2 is at a high level, the first MOS transistor Q1 is turned on, and when the first output terminal DV1 is at a high level, the second MOS transistor is turned on.

[0086] In a specific embodiment, referring to Figure 3 As shown, the inverting circuit includes: a fourth MOS transistor Q4, a sixth resistor R6 and a seventh resistor R7;

[0087] The sixth resistor R6 is connected between the gate of the fourth MOS transistor Q4 and the second output terminal DV2 of the PWM control chip. The source of the fourth MOS transistor Q4 is grounded. The seventh resistor R7 is connected between the source and gate of the fourth MOS transistor Q4. The drain of the fourth MOS transistor Q4 is connected to the gate of the first MOS transistor Q1.

[0088] In the embodiment of the present invention, the fourth MOS transistor Q4 may be a BS107A MOS transistor. Of course, those skilled in the art may also select other suitable MOS transistors according to the teachings of relevant technologies, and this is not specifically limited in the embodiment of the present invention.

[0089] In a specific embodiment, referring to Figure 2As shown, a third resistor R3 is connected between the inverting input terminal of the first operational amplifier U1 and the step signal generator, and a fourth resistor R4 is connected between the inverting input terminal of the first operational amplifier U1 and the output terminal of the second operational amplifier U2.

[0090] In the embodiment of the present invention, a Kirchhoff circuit is formed based on the virtual ground characteristic of the operational amplifier input terminal. The inverting input terminal of the operational amplifier, that is, the node TP1, is at zero potential. According to Kirchhoff's current law (KCL), the sum of the currents of the third resistor R3 and the fourth resistor R4 is zero. Therefore, as shown in FIG2 , DA+ / R3=-UTP4 / R4, as shown in FIG2 . Figure 2 As shown, since the third resistor R3 and the fourth resistor R4 are both set to be 10KΩ precision resistors, the voltage at the TP4 point is equal to -DV+, that is, the voltage at the output end of the second operational amplifier U2 is -DA+. Figure 2 As shown, the resistance of the first resistor R1 is much greater than the resistance of the second resistor R2. The second operational amplifier U2 and the connected first resistor R1 and second resistor R2 form an inverting attenuation circuit. According to Kirchhoff's law, HVOUT+ / R1=DA+ / R2, so HVOUT+=200*DA+. From this, it can be seen that when DA+ is a constant value, HVOUT+ is also a constant value. When DA+ is a pulse voltage signal, HVOUT+ is also a pulse signal. In this embodiment of the present invention, in order to ensure the reliability of the circuit, the pulse voltage signal output by the step signal generator, that is, the width of the DA+ pulse signal, can be set to be greater than 10uS.

[0091] In a specific embodiment, referring to Figure 2 As shown, an energy storage capacitor C5 is connected in parallel between the inverting input terminal and the output terminal of the second operational amplifier U2 to achieve the function of stabilizing the circuit.

[0092] In a specific embodiment, referring to Figure 2 As shown, the high-voltage power supply circuit 1 further includes: a twelfth resistor R12 arranged between the gate and the drain of the third MOS transistor Q3 and a thirteenth resistor R13 arranged between the gate of the third MOS transistor Q3 and the first operational amplifier U1.

[0093] In the embodiment of the present invention, the third MOS transistor Q3 is connected via the twelfth resistor R12 and the thirteenth resistor R13 to provide a bias voltage for the third MOS transistor Q3, thereby ensuring the normal operation of the third MOS transistor Q3. Since the gate of the third MOS transistor is connected to the output end of the first operational amplifier U1 via the thirteenth resistor R13, the second operational amplifier U2 serves as the main operational amplifier of the high-voltage power supply circuit 1 between the output end and the inverting input end, forming a closed loop. The variable resistance area of ​​the third MOS transistor is automatically adjusted by the first operational amplifier U1 to ensure the stability of the closed loop. Since the resistance values ​​of the first resistor R1 and the second resistor R2 are not variable, the attenuation multiple of the reverse attenuation circuit formed by the second operational amplifier U2, the first resistor R1, and the second resistor R2 is fixed. Therefore, the source voltage of the first MOS transistor (i.e., Figure 2 The voltage at the middle node TP3 is automatically adjusted to achieve the circuit voltage, thereby improving the regulation accuracy of the circuit.

[0094] In a specific embodiment, referring to Figure 2 As shown, a third diode D3 is further connected between the inverting input and output of the first operational amplifier. By providing the third diode D3 and utilizing the unidirectional conduction characteristic of the third diode D3, the output is ensured not to deviate toward the negative power supply, thereby preventing the circuit output voltage from being too high.

[0095] In a specific embodiment, referring to Figure 2 As shown, a fourth capacitor C4 and a fifth resistor R5 are connected between the inverting input terminal and the output terminal of the first operational amplifier.

[0096] In a specific embodiment, referring to Figure 2 As shown, the high-voltage power supply circuit 1 further includes: an eighth resistor R8 provided between the gate of the first MOS transistor and the input voltage terminal;

[0097] a ninth resistor R9 disposed between the gate of the first MOS transistor and the drain of the fourth MOS transistor;

[0098] a tenth resistor R10 provided between the gate of the second MOS transistor and the input voltage terminal;

[0099] an eleventh resistor R11 disposed between the gate of the second MOS transistor and the first input terminal of the PWM control chip.

[0100] In the embodiment of the present invention, voltage division is achieved by providing voltage dividing resistors at the gates of the first MOS transistor and the second MOS transistor, thereby ensuring the stability of the circuit.

[0101] In a specific embodiment, referring to Figure 2As shown, a bypass capacitor C6 is also connected between the voltage input terminal and the ground terminal to achieve circuit filtering and reduce noise in the circuit; an electrolytic capacitor E1 is also connected between the common terminal of the voltage input terminal and the eighth resistor and the ground terminal to achieve circuit energy storage.

[0102] In a specific embodiment, referring to Figure 2 As shown, a resistor R14 is further connected between the gate and source of the first MOS transistor; a resistor R15 is further connected between the gate and source of the second MOS transistor to achieve a circuit stabilization function.

[0103] As a specific implementation of the embodiment of the present invention, refer to Figure 4 As shown, the current detection circuit 4 includes: an absolute value circuit, a fourth operational amplifier U4, a twentieth resistor R20, a twenty-first resistor R21, a comparator U5 and a control unit;

[0104] One end of the absolute value circuit is connected to the current measurement circuit 2, and the other end is connected to the non-inverting input terminal of the fourth operational amplifier U4;

[0105] The inverting input terminal of the fourth operational amplifier U4 is grounded via the twentieth resistor R20, the twenty-first resistor R21 is connected between the inverting input terminal and the output terminal of the fourth operational amplifier U4, and the output terminal of the fourth operational amplifier U4 is connected to the inverting input terminal of the comparator U5;

[0106] The non-inverting input terminal of the comparator U5 is connected to the comparison reference voltage terminal LDA, and the output terminal CMPOUT of the comparator U5 is connected to the control unit;

[0107] The control unit is connected to the voltage measurement circuit 3 and the high-voltage power supply circuit 1, and is used to send a breakdown voltage measurement signal to the voltage measurement circuit 3 and a stop working signal to the high-voltage power supply circuit 1 when it is determined that the output signal level of the comparator U5 is reversed.

[0108] In an optional embodiment, a twelfth capacitor C12 is connected between the inverting input terminal and the output terminal of the fourth operational amplifier U4.

[0109] In an optional embodiment, the absolute value circuit includes a sixth operational amplifier U6 and a seventh operational amplifier U7;

[0110] The output terminal of the sixth operational amplifier U6 is connected to the non-inverting input terminal of the fourth operational amplifier U4 via a twenty-second resistor R22, a twenty-third resistor R23 and a thirteenth capacitor C13 are connected in parallel between the inverting input terminal and the output terminal of the sixth operational amplifier U6, the inverting input terminal of the sixth operational amplifier U6 is connected to the output terminal of the seventh operational amplifier U7 via a twenty-fourth resistor R24 ​​and a fourth diode D4, and the inverting input terminal of the sixth operational amplifier U6 is connected to the current measurement circuit 2 via a twenty-fifth resistor R25;

[0111] The non-inverting input terminal of the seventh operational amplifier U7 is grounded via the twenty-sixth resistor R26, the inverting input terminal of the seventh operational amplifier U7 is connected to the current measurement circuit 2 via the twenty-seventh resistor R27, the fifth diode D5 is connected between the output terminal and the inverting input terminal of the seventh operational amplifier U7, and the twenty-eighth resistor R28 is connected between the inverting input terminal of the seventh operational amplifier U7 and the common terminal of the twenty-fourth resistor R24 ​​and the fourth diode D4.

[0112] In an optional embodiment, a twenty-ninth resistor R29 is connected between the non-inverting input terminal of the comparator U5 and the comparison reference voltage terminal LDA;

[0113] A thirtieth resistor R30 is connected between the output terminal of the fourth operational amplifier U4 and the inverting input terminal of the comparator U5 .

[0114] In a specific embodiment, the control unit is a Field Programmable Gate Array (FPGA). In the embodiment of the present invention, the control logic of the control unit when it is an FPGA can be implemented according to the detailed description in the relevant art, which will not be repeated here.

[0115] In the embodiment of the present invention, the sixth operational amplifier and the seventh operational amplifier form an absolute value circuit, so that the voltage IVCOUT output by the current measurement circuit 2 is a positive voltage, wherein IVCOUT is the voltage value after the current is measured in the current measurement circuit 2 and converted into a voltage; in the embodiment of the present invention, after obtaining the positive voltage of the voltage IVCOUT, the voltage is amplified by the fourth operational amplifier U4, referring to Figure 4 As shown, the resistance value of the 21st resistor R21 is 4 times that of the 20th resistor R20, that is, R20:(R20+R21)=1:5. Therefore, the voltage value after the fourth operational amplifier U4 performs in-phase amplification is the positive voltage of IVCOUT, which is amplified 5 times. In the embodiment of the present invention, due to the setting Figure 2The full-scale range of the current measurement circuit 2 shown is 2V, meaning that the maximum voltage output by the output terminal of the fourth operational amplifier U4 is 10V. Next, the comparator U5 compares the positive voltage, amplified five times, with the value of the reference voltage terminal LDA. When the voltage output by the output terminal of the fourth operational amplifier U4 is greater than LDA, it indicates that the transistor has broken down. At this point, the current flowing through the transistor reaches the rated current value, and the level of the output signal at the output terminal CMP OUT of the comparator U5 reverses. The output signal of the comparator U5 is sent to the control unit. Upon receiving the level-reversed output signal, the control unit sends a breakdown voltage measurement signal to the voltage measurement circuit 3 and a stop signal to the high-voltage power supply circuit 1.

[0116] In a specific embodiment, referring to Figure 2 As shown, in an embodiment of the present invention, the step signal generator of the high-voltage power supply circuit 1 may be connected to the control unit, and upon receiving the stop working signal from the control unit, the step signal generator is reset to zero, so that the output DA+ is zero.

[0117] As a specific implementation of the embodiment of the present invention, refer to Figure 5 As shown, the voltage measurement circuit 3 includes: an eighth operational amplifier U8 and a sampling and holding unit U9;

[0118] The non-inverting input terminal of the eighth operational amplifier U8 is connected to the high-voltage power supply circuit 1 via a thirty-first resistor R31, a negative feedback resistor unit is connected between the inverting input terminal and the output terminal of the eighth operational amplifier U8, and the output terminal of the eighth operational amplifier U8 is connected to the signal output terminal of the sampling and holding unit U9 via a thirty-second resistor R32;

[0119] The logic signal terminal of the sampling and holding unit U9 is connected to the current detection circuit 4, and the output terminal of the sampling and holding unit U9 is externally connected to a voltage measurement unit;

[0120] The sampling and holding unit U9 is used to perform sampling and holding upon receiving the breakdown voltage measurement signal from the current detection circuit 4 , and send the sampling and holding signal to the voltage measurement unit.

[0121] In the embodiment of the present invention, the sampling and holding unit U9 can use the LF398 chip. Of course, in some other embodiments, the sampling and holding unit can also be implemented by selecting other chips in the prior art. Specifically, those skilled in the art can implement it based on the detailed description of the relevant technology, and no specific limitation is made here.

[0122] In an alternative embodiment, referring to Figure 5As shown, the negative feedback resistor unit includes a first negative feedback resistor R33, a switch K0 and a second negative feedback resistor R34 connected in sequence.

[0123] In the embodiment of the present invention, the switching switch k can be an electromagnetic relay switch. Of course, those skilled in the art can also select other suitable types of switching switches according to the description in the relevant technology to connect the second negative feedback resistor R34 to the circuit, or connect the first negative feedback resistors R33 and R34 in series to the circuit. The specific implementation method of the switching switch k0 is not specifically limited here.

[0124] In an alternative embodiment, referring to Figure 5 As shown, the negative feedback resistance unit further includes: a compensation capacitor C14; the compensation capacitor C14 is connected in parallel between the inverting input terminal and the output terminal of the eighth operational amplifier U8.

[0125] In the embodiment of the present invention, the eighth operational amplifier U8 constitutes a reverse attenuation circuit. Figure 5 As shown, the resistance value of the thirty-fourth resistor R34 is 50 times that of the thirty-second resistor R32, and the resistance value of the thirty-third resistor R33 and the thirty-fourth resistor R34 is 200 times that of the thirty-second resistor R32. Therefore, the voltage value after inverse attenuation by the eighth operational amplifier U8 is 1 / 50 or 1 / 200 of the voltage value of the output terminal HVSOUT of the current measurement circuit 2, and is transmitted to the input terminal of the sampling and holding unit U9.

[0126] Reference Figure 5 As shown, when the level signal sent by the control unit to the sampling and holding signal terminal (i.e., pin 8) of the sampling and holding unit U9 changes from a sampling signal to a holding signal, that is, after the breakdown voltage measurement signal is sent, the input voltage of the input terminal (i.e., pin 3) of the sampling and holding unit U9 is sampled and held. At this time, the voltage of the output terminal (i.e., pin 5) of the sampling and holding unit U9 is measured by the voltage measuring unit, and then multiplied by the attenuation multiple (50 times or 200 times) to obtain the breakdown high voltage of the transistor.

[0127] As a specific implementation of the embodiment of the present invention, refer to Figure 6 As shown, the current measurement circuit 2 includes: a tenth operational amplifier U10, an eleventh operational amplifier U11, a twelfth operational amplifier U12, a current driving circuit and at least one set of negative feedback resistor circuits;

[0128] The non-inverting input terminal of the tenth operational amplifier U10 is connected to the first electrode of the transistor, a thirty-fifth resistor R35 is connected between the inverting input terminal and the output terminal of the tenth operational amplifier U10, and the output terminal of the tenth operational amplifier U10 is connected to the inverting input terminal of the eleventh operational amplifier U11 via a thirty-sixth resistor R36;

[0129] The non-inverting input terminal of the eleventh operational amplifier U11 is grounded, a thirty-seventh resistor R37 is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier U11, and the output terminal of the eleventh operational amplifier U11 is connected to the inverting input terminal of the twelfth operational amplifier U12 via a thirty-eighth resistor R38;

[0130] The non-inverting input terminal of the twelfth operational amplifier U12 is grounded; a thirty-ninth resistor R39 is connected between the inverting input terminal and the output terminal of the twelfth operational amplifier U12, and the output terminal of the twelfth operational amplifier U12 is connected to the current detection circuit 4;

[0131] One common end of the at least one group of negative feedback resistor circuits is connected to the first electrode of the transistor, and the other common end is connected to the common end of the thirty-eighth resistor R38 and the thirty-ninth resistor R39 via the fortieth resistor R40;

[0132] One end of the current driving circuit is connected to the first electrode of the transistor, and the other end is connected to a common end of the at least one group of negative feedback resistor circuits and the fortieth resistor R40.

[0133] In an embodiment of the present invention, the current direction of the transistor is controlled by a current driving circuit so that the current flows into or out of the transistor. The voltage is followed by the tenth operational amplifier to obtain the reverse voltage value of the voltage of the first pole of the transistor, and the voltage is reversed by the eleventh operational amplifier to prevent the voltage floating of the grounding point from affecting the circuit, thereby obtaining the true voltage of the first pole of the transistor. The virtual ground characteristic of the input terminal of the twelfth operational amplifier is utilized to form a Kirchhoff circuit. According to Kirchhoff's current law (KCL), the sum of the currents at the inverting input terminal of the twelfth operational amplifier is zero, thereby being able to obtain the voltage of the load resistance circuit. According to the relationship between voltage, resistance and current, the magnitude of the current flowing through the transistor can be obtained.

[0134] In an alternative embodiment, referring to Figure 7 As shown, the current driving circuit includes a thirteenth operational amplifier U13, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7 and an eighth transistor Q8;

[0135] The non-inverting input terminal of the thirteenth operational amplifier U13 is grounded via a forty-first resistor R41, the inverting input terminal of the thirteenth operational amplifier U13 is connected to the first electrode of the transistor via a forty-second resistor R42, the non-inverting input terminal and the inverting input terminal of the thirteenth operational amplifier U13 are virtually short-circuited, the output terminal of the thirteenth operational amplifier U13 is respectively connected to the bases of the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8, the collectors of the fifth transistor Q5 and the sixth transistor Q6 are connected to the positive voltage input terminal, the collectors of the seventh transistor Q7 and the eighth transistor Q8 are connected to the negative voltage input terminal, and the emitters of the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8 are connected to the common terminal of the at least one group of negative feedback resistor circuits and the sixth resistor.

[0136] The current driving circuit provided in an embodiment of the present invention collects the voltage of the first electrode of the transistor through a thirteenth operational amplifier U13. A push-pull circuit consisting of a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8 is connected to the output terminal of the thirteenth operational amplifier U13. When current flows into the first electrode of the transistor, the output terminal of the thirteenth operational amplifier U13 outputs a negative voltage. At this time, the seventh transistor Q7 and the eighth transistor Q8 are turned on, and the current flows to the power supply F28-. When current flows out of the first electrode of the transistor, the output terminal of the thirteenth operational amplifier U13 outputs a positive voltage. At this time, the fifth transistor Q5 and the sixth transistor Q6 are turned on, and the current flows out from the power supply F28+. As a result, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are driven by the thirteenth operational amplifier U13 to provide current from the power supply. This enables the current measurement circuit 2 to have the ability to measure current under positive and negative voltages.

[0137] In an alternative embodiment, referring to Figure 7 As shown, the bases of the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8 are respectively connected to the output end of the thirteenth operational amplifier U13 via a forty-third resistor (i.e., resistors R43A-R43D), and the emitters of the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7 and the eighth transistor Q8 are respectively connected to the common end of the at least one group of negative feedback resistor circuits and the sixth resistor via a forty-fourth resistor (i.e., resistors R44A-R44D).

[0138] In an alternative embodiment, referring to Figure 7 As shown, the collectors of the fifth transistor Q5 and the sixth transistor Q6 are connected to the positive voltage input terminal via a forty-fifth resistor R45, and the collectors of the seventh transistor Q7 and the eighth transistor Q8 are connected to the negative voltage input terminal via a forty-sixth resistor R46.

[0139] In an alternative embodiment, referring to Figure 6 As shown, the negative feedback resistor circuit includes seven or more negative feedback resistors RF1-RF7 connected in parallel, and each of the seven or more negative feedback resistors RF1-RF7 is connected in series with a control switch K1-K7.

[0140] In the embodiment of the present invention, the control switches K1-K7 may be reed relays. The resistors RF6 and RF7 may be power resistors.

[0141] In an alternative embodiment, referring to Figure 6 As shown, the non-inverting input and the inverting input of the thirteenth operational amplifier U13 are connected via two diodes D6 and D7 connected in parallel in opposite directions. The two oppositely connected diodes serve as a voltage clamping protection circuit. When the potential difference between the non-inverting input and the inverting input of the thirteenth operational amplifier U13 exceeds the withstand voltage of diodes D6 or D7 due to a transient voltage change, the diodes open, preventing the voltage deviation between the non-inverting input and the inverting input of the thirteenth operational amplifier U13 from exceeding the voltage limit of the virtual short connection. This voltage deviation between the non-inverting input and the inverting input of the thirteenth operational amplifier U13 is amplified by the thirteenth operational amplifier U13, causing damage to the circuit of the thirteenth operational amplifier U13.

[0142] In an alternative embodiment, referring to Figure 6 As shown, a compensation capacitor C19 is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier U11, which can not only realize current energy storage, but also change the phase margin, thereby stabilizing the circuit.

[0143] In an alternative embodiment, referring to Figure 6 As shown, a third potentiometer RV3 is connected between the first zero adjustment terminal and the second zero adjustment terminal of the tenth operational amplifier U10 to balance the voltage offset between the non-inverting input terminal and the inverting input terminal of the tenth operational amplifier U10 caused by the bias current, perform voltage compensation, and balance the circuit offset voltage.

[0144] In an alternative embodiment, referring to Figure 6 As shown, the non-inverting input terminal of the tenth operational amplifier U10 is connected to the first electrode of the transistor via the forty-seventh resistor R47.

[0145] Example 2

[0146] Based on the same inventive concept, an embodiment of the present invention further provides a breakdown voltage measurement device, characterized in that it includes: the breakdown voltage measurement circuit described in the above embodiment 1.

[0147] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

[0148] Unless otherwise specifically stated, terms such as process, calculate, compute, determine, display, and the like may refer to the actions and / or processes of one or more processing or computing systems, or similar devices, that manipulate and convert data represented as physical (e.g., electronic) quantities within registers or memories of a processing system into other data similarly represented as physical quantities within the memories, registers, or other such information storage, transmission, or display devices of the processing system. Information and signals may be represented using any of a variety of different techniques and methods. For example, data, instructions, commands, information, signals, bits, symbols, and chips referred to throughout the above description may be represented by voltages, currents, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0149] It should be understood that the specific order or hierarchy of steps in the disclosed processes is an example of an exemplary method. Based on design preferences, it should be understood that the specific order or hierarchy of steps in the process can be rearranged without departing from the scope of the present disclosure. The accompanying method claims present elements of the various steps in an exemplary order and are not intended to be limited to the specific order or hierarchy described.

[0150] In the foregoing detailed description, various features are grouped together in a single embodiment to simplify the disclosure. This method of disclosure should not be interpreted as reflecting an intention that embodiments of the claimed subject matter require more features than are expressly recited in each claim. On the contrary, as reflected in the appended claims, the invention comprises less than all the features of any individual disclosed embodiment. The appended claims are therefore hereby expressly incorporated into the detailed description, with each claim standing on its own as a separate preferred embodiment of the invention.

[0151] Those skilled in the art will also appreciate that the various illustrative logic blocks, modules, circuits, and algorithmic steps described in conjunction with the embodiments herein may be implemented as electronic hardware, computer software, or a combination thereof. In order to clearly illustrate the interchangeability between hardware and software, the various illustrative components, blocks, modules, circuits, and steps described above are generally described around their functions. Whether such functions are implemented as hardware or software depends on the specific application and the design constraints imposed on the entire system. A skilled person may implement the described functions in an adaptable manner for each specific application, but such implementation decisions should not be interpreted as departing from the scope of protection of this disclosure.

[0152] The steps of the methods or algorithms described in conjunction with the embodiments herein may be directly embodied as hardware, software modules executed by a processor, or a combination thereof. The software module may be located in a RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, register, hard disk, removable disk, CD-ROM, or any other form of storage medium well known in the art. An exemplary storage medium is connected to the processor so that the processor can read information from the storage medium and write information to the storage medium. Of course, the storage medium may also be an integral part of the processor. The processor and storage medium may be located in an ASIC. The ASIC may be located in a user terminal. Of course, the processor and storage medium may also be present in a user terminal as discrete components.

[0153] For software implementation, the techniques described in this application can be implemented using modules (e.g., procedures, functions, etc.) that perform the functions described in this application. These software codes can be stored in a memory unit and executed by a processor. The memory unit can be implemented within the processor or external to the processor. In the latter case, it is communicatively coupled to the processor via various means, which are well known in the art.

[0154] The foregoing description includes examples of one or more embodiments. Of course, it is not possible to describe all possible combinations of components or methods for the purposes of describing the above embodiments, but one of ordinary skill in the art will recognize that the various embodiments may be further combined and arranged. Therefore, the embodiments described herein are intended to encompass all such changes, modifications and variations that fall within the scope of the appended claims. Furthermore, to the extent the term "comprising" is used in the specification or claims, the term is intended to be encompassed in a manner similar to the term "including," as explained in terms of "including," used as a transitional word in the claims. Furthermore, any use of the term "or" in the specification of the claims is intended to mean a "non-exclusive or."

Claims

1. A breakdown voltage measurement circuit, characterized in that: include: High voltage power supply circuit, current measurement circuit, voltage measurement circuit and current detection circuit; When the transistor is connected to the breakdown voltage measurement circuit, the current measurement circuit is connected to a first electrode of the transistor, and the high-voltage power supply circuit and the voltage measurement circuit are connected to a second electrode of the transistor; The current detection circuit is respectively connected to the high-voltage power supply circuit, the current measurement circuit and the voltage measurement circuit; The high-voltage power supply circuit is suitable for outputting a step-by-step increasing pulse voltage signal to the transistor; The current measurement circuit is adapted to measure the current signal of the transistor and send the current signal to the current detection circuit; The voltage measurement circuit is adapted to measure the breakdown voltage of the transistor; The current detection circuit is adapted to send a breakdown voltage measurement signal to the voltage measurement circuit and a stop operation signal to the high-voltage power supply circuit when the value of the received current signal of the transistor is greater than a preset rated current value; The high-voltage power supply circuit includes: a step signal generator, a first operational amplifier, a first MOS transistor, a second MOS transistor, a third MOS transistor, a transformer, a voltage doubling circuit, a second operational amplifier, a first capacitor, a first resistor, a second resistor and a PWM control unit; The current detection circuit includes: an absolute value circuit, a fourth operational amplifier, a twentieth resistor, a twenty-first resistor, a comparator and a control unit; One end of the absolute value circuit is connected to the current measurement circuit, and the other end is connected to the non-inverting input terminal of the fourth operational amplifier; The inverting input terminal of the fourth operational amplifier is grounded via the twentieth resistor, the twenty-first resistor is connected between the inverting input terminal and the output terminal of the fourth operational amplifier, and the output terminal of the fourth operational amplifier is connected to the inverting input terminal of the comparator; The non-inverting input terminal of the comparator is connected to the comparison reference voltage terminal, and the output terminal of the comparator is connected to the control unit; The control unit is connected to the voltage measurement circuit and the high-voltage power supply circuit, and is used to send a breakdown voltage measurement signal to the voltage measurement circuit and a stop working signal to the high-voltage power supply circuit when it is determined that the output signal level of the comparator is inverted.

2. The breakdown voltage measurement circuit according to claim 1, wherein: The non-inverting input terminal of the first operational amplifier is grounded, the inverting input terminal of the first operational amplifier is connected to the output terminals of the signal generator and the second operational amplifier respectively, and the output terminal of the operational amplifier is connected to the gate of the third MOS transistor; The source of the third MOS transistor is connected to the input voltage, and the drain of the third MOS transistor is connected to the source of the first MOS transistor; The gate of the first MOS transistor is connected to the input voltage and the second output terminal of the PWM control unit, and the drain of the first MOS transistor is connected to the drain of the second MOS transistor; The gate of the second MOS transistor is connected to the first output terminal of the PWM control unit and is grounded, and the drain of the second MOS transistor is connected to the third terminal of the transformer and is grounded; The first end of the transformer is connected between the drain of the first MOS transistor and the drain of the second MOS transistor, the second end and the fourth end of the transformer are respectively connected to the input end of the voltage doubler circuit, the output end of the voltage doubler circuit is connected to the non-inverting input end of the second operational amplifier via the first capacitor C15, and the output end of the voltage doubler circuit is connected to the inverting input end of the second operational amplifier via the first resistor R14; The non-inverting input terminal of the second operational amplifier is grounded; A second resistor R19 is connected between the inverting input terminal and the output terminal of the non-inverting input terminal of the second operational amplifier; The signal generator is capable of outputting a first constant voltage signal or a first pulse voltage signal; The PWM control unit can output a preset waveform signal.

3. The breakdown voltage measurement circuit according to claim 1, wherein: The absolute value circuit includes a sixth operational amplifier and a seventh operational amplifier; The output terminal of the sixth operational amplifier is connected to the non-inverting input terminal of the fourth operational amplifier via a twenty-second resistor, a twenty-third resistor and a thirteenth capacitor are connected in parallel between the inverting input terminal and the output terminal of the sixth operational amplifier, the inverting input terminal of the sixth operational amplifier is connected to the output terminal of the seventh operational amplifier via a twenty-fourth resistor and a fourth diode, and the inverting input terminal of the sixth operational amplifier is connected to the current measurement circuit via a twenty-fifth resistor; The non-inverting input terminal of the seventh operational amplifier is grounded via a twenty-sixth resistor, the inverting input terminal of the seventh operational amplifier is connected to the current measurement circuit via a twenty-seventh resistor, a fifth diode is connected between the output terminal and the inverting input terminal of the seventh operational amplifier, and a twenty-eighth resistor is connected between the inverting input terminal of the seventh operational amplifier and the common terminal of the twenty-fourth resistor and the fourth diode.

4. The breakdown voltage measurement circuit according to claim 1, wherein: A twenty-ninth resistor is connected between the non-inverting input terminal of the comparator and the comparison reference voltage terminal; A thirtieth resistor is connected between the output terminal of the fourth operational amplifier and the inverting input terminal of the comparator.

5. The breakdown voltage measurement circuit according to claim 1, wherein: The voltage measurement circuit includes: an eighth operational amplifier and a sampling and holding unit; The non-inverting input terminal of the eighth operational amplifier is connected to the high-voltage power supply circuit via a thirty-first resistor, a negative feedback resistor unit is connected between the inverting input terminal and the output terminal of the eighth operational amplifier, and the output terminal of the eighth operational amplifier is connected to the signal output terminal of the sampling and holding unit via a thirty-second resistor; The logic signal terminal of the sampling and holding unit is connected to the current detection circuit, and the output terminal of the sampling and holding unit is externally connected to a voltage measurement unit; The sampling and holding unit is used to perform sampling and holding when receiving the breakdown voltage measurement signal of the current detection circuit, and send the sampling and holding signal to the voltage measurement unit.

6. The breakdown voltage measurement circuit according to claim 5, wherein: The negative feedback resistor unit includes a first negative feedback resistor, a switch, and a second negative feedback resistor that are connected in sequence.

7. The breakdown voltage measurement circuit according to claim 5, wherein: The negative feedback resistance unit further includes: a compensation capacitor; the compensation capacitor is connected in parallel between the inverting input terminal and the output terminal of the eighth operational amplifier.

8. The breakdown voltage measurement circuit according to claim 1, wherein: The current measurement circuit includes: a tenth operational amplifier, an eleventh operational amplifier, a twelfth operational amplifier, a current driving circuit and at least one set of negative feedback resistance circuits; The non-inverting input terminal of the tenth operational amplifier is connected to the first electrode of the transistor, a thirty-fifth resistor is connected between the inverting input terminal and the output terminal of the tenth operational amplifier, and the output terminal of the tenth operational amplifier is connected to the inverting input terminal of the eleventh operational amplifier via a thirty-sixth resistor; The non-inverting input terminal of the eleventh operational amplifier is grounded, a thirty-seventh resistor is connected between the inverting input terminal and the output terminal of the eleventh operational amplifier, and the output terminal of the eleventh operational amplifier is connected to the inverting input terminal of the twelfth operational amplifier via a thirty-eighth resistor; The non-inverting input terminal of the twelfth operational amplifier is grounded; a thirty-ninth resistor is connected between the inverting input terminal and the output terminal of the twelfth operational amplifier, and the output terminal of the twelfth operational amplifier is connected to the current detection circuit; One common end of the at least one group of negative feedback resistor circuits is connected to the first electrode of the transistor, and the other common end is connected to the common end of the thirty-eighth resistor and the thirty-ninth resistor via the fortieth resistor R40; One end of the current driving circuit is connected to the first electrode of the transistor, and the other end is connected to the common end of the at least one group of negative feedback resistor circuits and the fortieth resistor.

9. A breakdown voltage measuring device, characterized in that: include: The breakdown voltage measurement circuit according to any one of claims 1 to 8.

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