Interval oscillator, control method thereof, and memory having the same

Abstract

The present invention provides an interval oscillator, a control method thereof, and a memory capable of obtaining a specified time interval and eliminating time differences caused by delays. The interval oscillator includes: a clock generator that generates a clock signal of a specific frequency; a timer that counts the clock signal and outputs a timing signal; a start signal generator that uses a signal edge corresponding to a first timing of the clock signal to trigger the inversion of a timing signal that has not undergone level conversion, thereby generating a start signal that starts the interval oscillator; and a stop signal generator that uses a signal edge corresponding to a second timing of the clock signal to trigger a timing signal that has undergone level conversion, thereby generating a stop signal that stops the interval oscillator. The second timing is a timing that has passed a specified count of clock cycles after the first timing, and the time interval between the start signal and the stop signal is equal to the specified time interval.

Description

Technical Field

[0001] The present invention relates to an interval oscillator, in particular to an interval oscillator capable of eliminating delay time difference to obtain accurate time intervals. The present invention also relates to a control method of the interval oscillator and a memory equipped with the interval oscillator. Background Art

[0002] Random access memory (RAM) can be divided into SRAM (static random access memory) and DRAM (dynamic random access memory). DRAM uses the charge stored in capacitors to store data, requiring a periodic refresh circuit to overcome capacitor leakage. It is commonly used in large-capacity main memory, such as computers, smartphones, and server memory. DRAM can be further divided into SDRAM, DDR SDRAM, and RDRAM.

[0003] Among them, SDRAM (Synchronous DRAM) is a clock-synchronized memory that operates based on the clock signal generated by the processor. The command signal used to define the action and the address signal used to specify the memory cell are sent in parallel and synchronized with the rising edge of the clock signal. DDR SDRAM (double data rate SDRAM: double data rate synchronous dynamic random access memory; hereinafter referred to as DDR) is a memory with a double data rate. Data can be transmitted on both the rising and falling edges of the clock signal, that is, its data transmission speed is twice the frequency of the clock signal. Due to the increased speed, its transmission performance is better than traditional SDRAM. DDR is widely used in various smart products such as tablets, set-top boxes, automotive electronics, digital TVs, etc. due to its higher data rate, lower energy consumption and higher density.

[0004] On the other hand, LPDDR (Low Power DDR) is specifically used in mobile electronic products due to its advantages such as low power consumption and small size. Moreover, due to its significantly reduced energy consumption, it effectively extends battery life.

[0005] The initialization process for SDRAM, DDR, and other memory devices involves using the standard mode register (MRS) or the extended mode register (EMRS) to define the operating mode. The data in the MRS mode register controls CAS (Column Address Signal) delay, burst length, burst sequence, test mode, and DLL (Delay-Locked Loop) reset, supporting various SDRAM and DDR applications. The default value of the mode register is undefined, so the mode register value must be set according to the specified timing specifications after power-on.

[0006] On the other hand, the DQS (Bi-directional Data Strobe) signal, which controls the read and write timing of the data signal DQ, accurately distinguishes each transmission cycle within a clock cycle and facilitates the receiver to accurately receive data. The DQS signal can be considered the data synchronization signal. However, when DDR is working, the internal synchronization clock is the clock signal CK rather than DQS. Data needs to be synchronized with the clock signal CK (the internal clock is slower than the external clock) for internal transmission and storage. Therefore, all DQ signals must be synchronized and maintain a certain relationship with the clock signal CK. Therefore, the delay between the DQS and CK signals must be controlled.

[0007] To achieve this, DDR and other devices include a DQS interval oscillator to generate the desired time interval. The DQS interval oscillator starts when it receives a start signal from a microprocessor, etc., and stops when the timer inside the DQS interval oscillator reaches a specified time, thereby generating the desired time interval.

[0008] However, the DQS interval oscillator takes a certain amount of time to actually start or stop after receiving the start or stop command signal. In other words, inherent delays in the DQS interval oscillator's internal components and circuits, as well as signal transmission delays, can cause a certain time difference between the interval generated by the DQS interval oscillator and the actual expected interval. As a result, the timing generated by the DQS interval oscillator may not accurately achieve the expected value, that is, it may not accurately reflect the preset interval. Summary of the Invention

[0009] The present invention is completed in order to solve the above-mentioned problem, and its purpose is to provide an interval oscillator that can eliminate the time difference caused by the above-mentioned delay and thus obtain an accurate time interval.

[0010] The interval oscillator involved in the first aspect of the present invention is used to obtain a specified time interval, comprising:

[0011] Clock generator, generates a clock signal of a specific frequency;

[0012] a timer for counting the clock signal generated by the clock generator and outputting a timing signal, wherein the timing signal undergoes a level conversion when the count value of the clock signal reaches a prescribed count value preset in the timer and corresponding to the prescribed time interval;

[0013] a start signal generating unit that triggers the inversion of the timing signal that has not undergone level conversion by using a signal edge corresponding to the first timing of the clock signal, thereby generating a start signal for starting the operation of the interval oscillator; and

[0014] a stop signal generating unit that generates a stop signal for stopping the operation of the interval oscillator by triggering the timing signal whose level has been converted by a signal edge corresponding to a second timing of the clock signal, wherein the second timing is a timing that has elapsed by the predetermined count value of clock cycles after the first timing,

[0015] The time interval between the start signal and the stop signal is equal to the prescribed time interval.

[0016] Preferably, in the interval oscillator involved in the first aspect of the present invention, the second aspect of the present invention is that when the count value of the clock signal does not reach the specified count value, the timing signal is at a low level, and when the count value of the clock signal reaches the specified count value, the timing signal changes from a low level to a high level.

[0017] Preferably, in the interval oscillator according to the second aspect of the present invention, the high level of the timing signal is maintained for one or more clock cycles and then changes to a low level, and a signal for stopping the operation of the clock generator is output to the clock generator.

[0018] Preferably, in the interval oscillator according to any one of the first to third aspects of the present invention according to a fourth aspect of the present invention, the first timing is a first rising edge of the clock signal.

[0019] Preferably, in the fifth aspect of the present invention, in the interval oscillator involved in any one of the first to third aspects of the present invention, the interval oscillator is arranged in DDR (double data rate synchronous dynamic random access memory) to generate the specified time interval for the DQS (data select pulse) signal.

[0020] A sixth aspect of the present invention relates to a method for controlling an interval oscillator, for obtaining a prescribed time interval, comprising the following steps:

[0021] A clock generator is used to generate a clock signal of a specific frequency;

[0022] Counting the clock signal generated by the clock generator using a timer and outputting a timing signal, wherein the timing signal undergoes a level conversion when the count value of the clock signal reaches a predetermined count value preset in the timer and corresponding to the predetermined time interval;

[0023] Using a signal edge corresponding to a first timing of the clock signal to trigger an inversion of the timing signal that has not undergone level conversion, thereby generating a start signal for starting the interval oscillator; and

[0024] The timing signal having undergone level conversion is triggered by a signal edge corresponding to a second timing of the clock signal to generate a stop signal for stopping the interval oscillator, wherein the second timing is a timing after the first timing by the predetermined count value of clock cycles.

[0025] The time interval between the start signal and the stop signal is made equal to the prescribed time interval.

[0026] Preferably, in the control method of the interval oscillator involved in the sixth aspect of the present invention, the seventh aspect of the present invention is that when the count value of the clock signal does not reach the specified count value, the timing signal is at a low level, and when the count value of the clock signal reaches the specified count value, the timing signal changes from a low level to a high level.

[0027] Preferably, in the eighth aspect of the present invention, in the control method of the interval oscillator involved in the seventh aspect of the present invention, the high level of the timing signal becomes a low level after being maintained for one or more clock cycles, and a signal is output to the clock generator to stop its operation.

[0028] Preferably, in the ninth aspect of the present invention, in the control method of the interval oscillator according to any one of the sixth to eighth aspects of the present invention, the first timing is a first rising edge of the clock signal.

[0029] A tenth aspect of the present invention relates to a memory, comprising at least the interval oscillator according to any one of the first to fifth aspects of the present invention.

[0030] Effects of the Invention

[0031] According to the interval oscillator of the present invention, a start signal generating unit generates a start signal for starting the interval oscillator at a timing corresponding to a signal edge of a clock signal based on a timing signal, and a stop signal generating unit generates a stop signal for stopping the interval oscillator at a timing corresponding to a signal edge of the clock signal based on the timing signal, so that the time interval between the start signal and the stop signal is equal to a predetermined time interval. This eliminates the time difference between the generated time interval and the actual desired time interval caused by inherent delays in components and circuits within the interval oscillator and signal transmission delays, allowing the timing recorded by the interval oscillator to accurately reflect the timing set in the timer. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 is a block diagram showing the basic structure of a DQS interval oscillator.

[0033] Figure 2 is a timing diagram showing the DQS interval oscillator.

[0034] Figure 3 This is a block diagram showing a basic configuration of a DQS interval oscillator according to the first embodiment of the present invention.

[0035] Figure 4 This is a timing chart showing the DQS interval oscillator according to the first embodiment of the present invention.

[0036] Figure 5 This is a flowchart showing a method for controlling a DQS interval oscillator according to the first embodiment of the present invention. DETAILED DESCRIPTION

[0037] The present invention is described more fully below with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention may be implemented in various ways and should not be limited to the embodiments set forth herein. The sizes and relative sizes of layers and regions may be exaggerated in the drawings for clarity.

[0038] For ease of description, spatially relative terms, such as "below," "beneath," "below," "above," and "upper," may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, an element described as "below" or "beneath" another element or feature would then be oriented "above" the other element or feature.

[0039] Unless otherwise defined, the terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention belongs. Terms should be understood to have meanings consistent with their meanings in the context of the relevant technology and should not be understood in an idealized or overly formal sense unless explicitly defined herein.

[0040] The present invention uses a DQS interval oscillator as an example, which is used in DDR to generate a predetermined time interval for a DQS signal. However, the present invention can also be applied to other types of interval oscillators as long as they can generate a desired time interval.

[0041] Therefore, the basic structure of the DQS interval oscillator and its signal timing are first described. Figure 1 FIG. 1 is a block diagram showing the basic structure of the DQS interval oscillator 100 . Figure 2 is a timing diagram of the DQS interval oscillator 100 .

[0042] like Figure 1 As shown in the upper part of FIG, the DQS interval oscillator 100 includes a clock generator 10, a counter 20, and a timer 30. The clock generator 10 generates a clock signal of a specific frequency for the timer 30. Here, the detailed structure of the clock generator 10 is as follows Figure 1 As shown in the lower portion of the , it receives an interval oscillator start signal START_OSC input from an external source, such as a microprocessor (not shown), to instruct the DQS interval oscillator 100 and timer 30 to begin operation. The clock generator 10 also receives inputs of the system clock signal CLK and the signal DQS_SETb_p, which will be discussed later. Based on the input system clock signal CLK, the clock generator 10 outputs a downconverted clock signal DCNT_CK. In the present invention, the frequency of the clock signal DCNT_CK is described as 1 / 16 of the system clock signal CLK. This is merely an example and can be appropriately set based on actual needs. Figure 1 The logic circuit structure shown in the lower part is also an example of the clock generator 10. As long as it can generate the clock signal DCNT_CK of the specified frequency based on the input interval oscillator start signal START_OSC, the system clock signal CLK and the signal DQS_SETb_p, the clock generator 10 can also adopt any structure.

[0043] The clock signal DCNT_CK output by the clock generator 10 is input to the counter 20. The counter 20 counts the clock signal DCNT_CK. In the present invention, the first 8 bits of data are used as an example. That is, the counter 20 outputs the clock signal count values ​​DCNT<7:0> corresponding to the first 8 bits of data 0-7 to the timer 30.

[0044] The timer 30 compares the received clock signal count value DCNT<7:0> with the preset setting signal DSET<7:0> corresponding to the first 8 bits of data 0-7, and outputs the timing signal DQS_SET according to the comparison result. Figure 1 The middle shows the detailed structure of the timer 30. For example, for the first bit, the count value DCNT <0> Its corresponding set value DSET <0> For comparison, for the second bit, the count value DCNT <1> Its corresponding set value DSET <1> Compare, ..., for the 8th bit, the count value DCNT <7> Its corresponding set value DSET <7> For comparison, the exemplary logic circuit shown in the figure outputs the timing signal DQS_SET, and outputs the signal DQS_SETb_p according to the timing signal DQS_SET. For details of the timing signal DQS_SET and the signal DQS_SETb_p, please refer to Figure 2 The timing diagram is used to illustrate this.

[0045] Here, the counter 20 and the timer 30 are schematically described as separate components, but the counter 20 is not essential, and the counting function of the timer 30 itself can also be used to implement the operation.

[0046] according to Figure 2 In the timing diagram, the system clock signal CLK is a high-frequency clock signal. The clock generator 10 of the interval oscillator 100 reduces the frequency of the system clock signal CLK and outputs the clock signal DCNT_CK. To simplify the description, Figure 2 Only the count values ​​DCNT of the first and second bits are shown. <0> 、DCNT <1> , omitting the DCNT <2> ~DCNT <7> In addition, Figure 2 In the example, the preset count value DSET<7:0> in the timer 30 is 3. That is, when the count value of the counter 20 reaches the preset value of 3, the timer 30 will output the timing signal DQS_SET which becomes high. After the high level of the timing signal DQS_SET lasts for a certain period of time, the timer 30 outputs the signal DQS_SETb_p, indicating that one operation of the timer 30 is completed, thereby terminating the operation of the clock generator 10 and causing it to stop generating the clock signal (e.g. Figure 1 shown).

[0047] Figure 2In the example, the interval oscillator start signal START_OSC, input from an external device or a microcontroller (not shown), is a low-level pulse. Upon receiving this interval oscillator start signal START_OSC, the interval oscillator 100 is powered on and begins operation. However, due to time delays caused by circuit components within clock generator 10, the starting point of the actually measured time interval is earlier than the starting point of the desired time interval. When the count value of counter 20 reaches 3, timer 30 outputs a high-level timing signal DQS_SET. However, due to time delays caused by circuit components within timer 30, the ending point of the actually measured time interval is later than the ending point of the desired time interval. Therefore, the time difference caused by the delay in the interval oscillator can cause the actually measured time interval to fail to reach the desired value, making it impossible to obtain an accurate time interval.

[0048] <Implementation Method 1>

[0049] In view of the above problems, the inventors of the present invention Figure 1 Based on the structure of the interval oscillator 100, a start signal generating unit for controlling the start signal of the interval oscillator to start timing and a stop signal generating unit for stopping timing are further provided, and the start signal and the stop signal are used to obtain the desired time interval.

[0050] Figure 3 This is a block diagram showing a basic configuration of a DQS interval oscillator 100 ′ according to the first embodiment of the present invention.

[0051] The basic structure of the DQS interval oscillator 100' of this embodiment includes a clock generator 10', a counter 20', a timer 30', a start signal generating unit 40 and a stop signal generating unit 50. Figure 3 The basic structure and function of the clock generator 10', counter 20' and timer 30' shown are similar to those of FIG. Figure 1 The clock generator 10 , counter 20 , and timer 30 ′ shown are the same and their description is not repeated here.

[0052] The DQS interval oscillator 100' of this embodiment is different from Figure 1 The DQS interval oscillator 100 further includes a start signal generating unit 40 and a stop signal generating unit 50. Figure 3 As shown in the lower part.

[0053] The start signal generating unit 40 includes an inverter 401, a D flip-flop 402, and a pulse generator 403. The timing signal DQS_SET generated by the timer 30' is input to the D terminal of the D flip-flop 402 via the inverter 401. The clock signal DCNT_CK generated by the clock generator 10' is input to the CK terminal of the D flip-flop 402. The signal output from the Q terminal of the D flip-flop 402 passes through the pulse generator 403 and is output as the start signal START.

[0054] The stop signal generating unit 50 includes a D flip-flop 502 and a pulse generator 503. The timing signal DQS_SET generated by the timer 30' is input to the D terminal of the D flip-flop 502, and the clock signal DCNT_CK generated by the clock generator 10' is input to the CK terminal of the D flip-flop 502. The signal output from the Q terminal of the D flip-flop 502 passes through the pulse generator 503 and is output as the stop signal STOP.

[0055] Next, combine Figure 4 To illustrate the timing of the start signal START and the stop signal STOP. Figure 4 CLK, DCNT_CK, DCNT <0> 、DCNT <1> , DCNT<7:0>, DSET<7:0>, START_OSC, DQS_SET, and the impact of time differences caused by delays. Figure 2 The situations shown are the same and therefore will not be repeated.

[0056] In this embodiment, the start signal START is a signal generated based on the timing signal DQS_SET output by the timer 30' and the clock signal DCNT_CK output by the clock generator 10' to start timing the DQS interval oscillator 100', that is, a signal that determines the starting timing of the time interval to be generated. Figure 3 As shown, the timing signal DQS_SET is input to the D terminal of the D flip-flop 402 via the inverter 401. The timing signal DQS_SET is generated by the timer 30' counting the clock signal DCNT_CK. According to this embodiment, when the count value of the clock signal DCNT_CK has not reached a predetermined value (3 in this embodiment), the timing signal DQS_SET is at a low level. Once the count value of the clock signal DCNT_CK reaches the predetermined value of 3, the timing signal DQS_SET undergoes a level transition, changing from a low level to a high level.

[0057] On the other hand, since the clock signal DCNT_CK is input to the CK terminal of the D flip-flop 402 as a synchronous clock signal, Figure 4As shown, during the period when the timing signal DQS_SET is at a low level, that is, before the count value of the clock signal DCNT_CK reaches a specified value, under the synchronization of the clock signal DCNT_CK, the first rising edge of the clock signal DCNT_CK (corresponding to DCNT <0> The first rising edge of DCNT<7:0> (the timing between "0" and "1") triggers the inversion of the low-level timing signal DQS_SET, generating a rising edge (i.e., a high level) of the pulse signal of the start signal START. The start signal START causes the DQS interval oscillator 100' to start timing.

[0058] In order to obtain a desired time interval, this embodiment further generates a stop signal STOP to cause the DQS interval oscillator 100 ′ to stop timing when the specified time interval is reached.

[0059] In this embodiment, the stop signal STOP is a signal generated based on the timing signal DQS_SET output by the timer 30' and the clock signal DCNT_CK output by the clock generator 10' to stop the timing of the DQS interval oscillator 100', that is, a signal that determines the end timing of the time interval to be generated. Figure 3 As shown, the timing signal DQS_SET is directly input to the D terminal of the D flip-flop 502 .

[0060] On the other hand, since the clock signal DCNT_CK is input to the CK terminal of the D flip-flop 502 as a synchronous clock signal, Figure 4 As shown in FIG, after a predetermined time interval (i.e., three clock signal cycles) has passed since the rising edge of the start signal START, the count value of the clock signal DCNT_CK has exceeded 3, so the timing signal DQS_SET has become a high level. At this time, under the synchronization of the clock signal DCNT_CK, the rising edge of the clock signal DCNT_CK (corresponding to DCNT_CK) <0> The high-level timing signal DQS_SET is triggered by a falling edge of DCNT<7:0> or the timing of "3" of DCNT<7:0>, generating a rising edge (ie, high-level) of the pulse signal of the stop signal STOP. The stop signal STOP stops the DQS interval oscillator 100' from timing.

[0061] The time interval between the rising edge of the start signal START and the rising edge of the stop signal STOP is equal to the desired time interval. Since the influence of the time delay in the clock generator 10' and the timer 30' is eliminated, the actually measured time interval is the desired time interval. Therefore, the DQS interval oscillator 100' can accurately generate the desired time interval.

[0062] In this embodiment, the start signal START is used to start the DQS interval oscillator 100', thereby starting timing, and the stop signal STOP is used to stop the DQS interval oscillator 100', thereby stopping timing. Before the counter 20' reaches the desired value for the clock signal DCNT_CK, the clock signal DCNT_CK is synchronized with the counter 20' to trigger the inversion of the currently low-level timing signal DQS_SET to generate a pulse of the start signal START. After the clock signal DCNT_CK reaches the desired value, the clock signal DCNT_CK is synchronized with the counter 20' to trigger the currently high-level timing signal DQS_SET to generate a pulse of the stop signal STOP. This ensures that the interval between the start signal START and the stop signal STOP exactly equals the desired interval. Furthermore, after the high-level timing signal DQS_SET remains for a certain period of time, the output signal DQS_SETb_p stops the clock generator 10'. Figure 4 In the embodiment, the time for the timing signal DQS_SET to maintain a high level is equivalent to one cycle of the clock signal DCNT_CK, but it can also be multiple cycles or other time lengths, which can be set according to actual conditions.

[0063] In addition, in this embodiment, the timing signal DQS_SET changes from low level to high level when the count value of the clock signal DCNT_CK reaches a specified value, but it can also change from high level to low level according to the requirements of the system circuit.

[0064] In this embodiment, during the period when the timing signal DQS_SET is at a low level, the first rising edge of the clock signal DCNT_CK (eg Figure 4 As shown, the timing between "0" and "1" of DCNT<7:0> triggers the inversion of the timing signal DQS_SET, thereby generating a pulse of the start signal START at the first rising edge of the clock signal DCNT_CK.

[0065] Then, while the timing signal DQS_SET is at a high level, at the rising edge of the clock signal DCNT_CK after a predetermined count value (here 3) has passed (eg, Figure 4 As shown, the timing between "3" and "4" (not shown) of DCNT<7:0> is triggered by the timing signal DQS_SET, thereby generating a pulse of the stop signal STOP at the rising edge of the clock signal DCNT_CK.

[0066] Therefore, the timing signal DQS_SET, the start signal START, and the stop signal STOP are synchronized by the clock signal DCNT_CK, thereby avoiding the delay time difference caused by circuit elements, and the DQS interval oscillator can provide the desired time interval.

[0067] Figure 5 This is a flowchart of a method for controlling the DQS interval oscillator 100 ′ according to the first embodiment of the present invention.

[0068] In step S1 , the clock generator 100 ′ generates a down-converted clock signal DCNT_CK according to the system clock signal CLK.

[0069] In step S2 , the counter 20 ′ counts the clock signal DCNT_CK and obtains a count value.

[0070] In step S3, timer 30' compares the count value with a predetermined count value corresponding to the desired time interval (in this embodiment, three cycles of the clock signal DCNT_CK) to determine whether the count value has reached the predetermined count value. If the count value has not reached the predetermined count value, that is, if the count value is less than the predetermined count value (step S3: Yes), the timer 30' outputs a low-level timing signal DQS_SET (step S4) and returns to step S2 to continue counting the clock signal.

[0071] Then, in step S5, at the first rising edge of the clock signal DCNT_CK (combined with Figure 4 As shown, here referred to as the "first timing"), using Figure 3 The start signal generating unit 40 triggers the low-level timing signal DQS_SET to be inverted, thereby generating a pulse of the start signal START in step S6.

[0072] When the count value of the clock signal DCNT_CK reaches the predetermined count value in step S3 , that is, the count value is greater than or equal to the predetermined count value (step S3 : No), the low-level timing signal DQS_SET changes to a high level (step S7 ).

[0073] Then, in step S8 , at the rising edge of the clock signal DCNT_CK corresponding to a second timing which is a predetermined time interval, ie, three clock cycles from the first timing, the high-level timing signal DQS_SET is triggered, thereby generating a pulse of the stop signal STOP in step S9 .

[0074] Therefore, through steps S6 and S9, the time interval between the rising edge of the pulse of the start signal START and the rising edge of the pulse of the stop signal STOP is the desired time interval (3 clock cycles). Therefore, the time interval generated thereby eliminates the influence of the time difference caused by the delay and can accurately generate the desired time interval (step S10).

[0075] Then, when the high level timing signal DQS_SET continues for a predetermined time, in this embodiment, Figure 4 As shown, the predetermined time is set to one cycle of the clock signal DCNT_CK. In step S11, a signal DQS_SETb_p is generated to stop the clock generator 10' from generating the clock signal.

[0076] The control method for the DQS interval oscillator 100' according to the first embodiment is used to obtain a specified time interval and includes the following steps: generating a clock signal DCNT_CK of a specific frequency using a clock generator 10', counting the clock signal DCNT_CK using a timer, outputting a low-level timing signal DQS_SET when the count value does not reach a specified count value corresponding to the specified time interval, and outputting a high-level timing signal DQS_SET when the count value reaches the specified count value; triggering the inversion of the low-level timing signal DQS_SET by a rising edge corresponding to a first timing of the clock signal DCNT_CK to generate a start signal START for starting timing of the DQS interval oscillator 100'; and triggering the high-level timing signal DQS_SET by a rising edge corresponding to a second timing of the clock signal DCNT_CK that is a specified time interval away from the first timing to generate a stop signal STOP for stopping timing of the DQS interval oscillator 100', so that the time interval between the start signal START and the stop signal STOP is the specified time interval.

[0077] Thus, the time difference between the generated time interval and the actual expected time interval caused by the inherent delay of the components or circuits inside the interval oscillator and the delay of signal transmission can be eliminated, so that the timing recorded by the interval oscillator can accurately reflect the timing set in the timer.

[0078] The present invention has been described in detail, but the above embodiments are merely examples of all embodiments and the present invention is not limited thereto. The present invention can freely combine the various embodiments within the scope of the invention, or modify or omit any constituent elements of the various embodiments.

[0079] Industrial applicability

[0080] The interval oscillator and the control method thereof of the present invention can be applied to various types of memories such as SRAM including SDR SRAM, DDR SRAM, QDR SRAM, and ZBT SRAM; DRAM including SDRAM, DDR DRAM, and RDRAM; and ROM.

Claims

1. An interval oscillator for obtaining a specified time interval, characterized in that: include: Clock generator, generates a clock signal of a specific frequency; a timer for counting the clock signal generated by the clock generator and outputting a timing signal, wherein the timing signal undergoes a level conversion when the count value of the clock signal reaches a prescribed count value preset in the timer and corresponding to the prescribed time interval; a start signal generating unit comprising an inverter and a first flip-flop, wherein the timing signal and the clock signal are input to the first flip-flop via the inverter, and a signal edge corresponding to a first timing of the clock signal is used to trigger the inversion of the timing signal that has not undergone level conversion, thereby generating a start signal for starting the operation of the interval oscillator; as well as A stop signal generating unit includes a second flip-flop, wherein the timing signal and the clock signal are input to the second flip-flop, and the timing signal, whose level has been converted, is triggered by a signal edge corresponding to a second timing of the clock signal to generate a stop signal for stopping the operation of the interval oscillator, wherein the second timing is a timing after the first timing by the predetermined count value of clock cycles. The time interval between the start signal and the stop signal is equal to the prescribed time interval.

2. The interval oscillator according to claim 1, wherein When the count value of the clock signal does not reach the specified count value, the timing signal is at a low level. When the count value of the clock signal reaches the specified count value, the timing signal changes from a low level to a high level.

3. The interval oscillator according to claim 2, wherein After the high level of the timing signal is maintained for one or more clock cycles, the timing signal changes to a low level and outputs a signal to the clock generator to stop the operation.

4. The interval oscillator according to any one of claims 1 to 3, characterized in that The first timing is a first rising edge of the clock signal.

5. The interval oscillator according to any one of claims 1 to 3, characterized in that The interval oscillator is provided in a DDR (double data rate synchronous dynamic random access memory) to generate the prescribed time interval for a DQS (data strobe) signal.

6. A method for controlling an interval oscillator, for obtaining a prescribed time interval, characterized in that: The process includes the following steps: A clock generator is used to generate a clock signal of a specific frequency; Counting the clock signal generated by the clock generator using a timer and outputting a timing signal, wherein the timing signal undergoes a level conversion when the count value of the clock signal reaches a predetermined count value preset in the timer and corresponding to the predetermined time interval; The timing signal and the clock signal are input to a first flip-flop via an inverter, and a signal edge corresponding to a first timing of the clock signal is used to trigger the inversion of the timing signal that has not undergone level conversion, thereby generating a start signal for starting the interval oscillator; as well as The timing signal and the clock signal are input to a second flip-flop, and the timing signal whose level has been converted is triggered by a signal edge corresponding to a second timing of the clock signal, thereby generating a stop signal for stopping the operation of the interval oscillator, wherein the second timing is a timing after the first timing by the predetermined count value of clock cycles. The time interval between the start signal and the stop signal is made equal to the prescribed time interval.

7. The control method of the interval oscillator according to claim 6, wherein: When the count value of the clock signal does not reach the specified count value, the timing signal is at a low level. When the count value of the clock signal reaches the specified count value, the timing signal changes from a low level to a high level.

8. The control method of the interval oscillator according to claim 7, wherein: After the high level of the timing signal is maintained for one or more clock cycles, the timing signal changes to a low level and outputs a signal to the clock generator to stop the operation.

9. The control method of the interval oscillator according to any one of claims 6 to 8, characterized in that: The first timing is a first rising edge of the clock signal.

10. A memory, characterized in that: At least comprising the interval oscillator according to any one of claims 1 to 5.

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