Integrated device including a transistor coupled to a dummy gate contact

Abstract

An integrated device includes a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled only to the gate.

Description

[0001] Cross-References to Related Applications

[0002] This patent application claims priority to Non-Provisional Application No. 16 / 828,487, filed March 24, 2020, entitled “INTEGRATED DEVICE COMPRISING TRANSISTOR COUPLED TO A DUMMY GATE CONTACT” and assigned to the assignee of the present application, and hereby expressly incorporated by reference herein. TECHNICAL FIELD

[0003] Various features relate to transistors, but more specifically, to an integrated device including a transistor coupled to a dummy gate contact. BACKGROUND

[0004] Figure 1 A planar field effect transistor (FET) 100 is shown. FET 100 is formed over a substrate 102 and an oxide 104. FET 100 includes a source 106, a drain 108, and a gate 110. Source 106 and drain 108 are located over substrate 102. Current can flow between source 106 and drain 108 when a minimum voltage is applied between gate 110 and substrate 102. There is a constant need to improve transistor performance, for example, to better control current flow between the source and drain of a transistor. SUMMARY

[0005] Various features relate to transistors, but more specifically, to an integrated device including a transistor coupled to a dummy gate contact.

[0006] One example provides an integrated device including a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is only directly electrically coupled to the gate.

[0007] Another example provides an apparatus including a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The apparatus includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The apparatus includes a means for regulating a voltage required to induce a first current in the first transistor, where the means for regulating is only directly electrically coupled to the gate.

[0008] Yet another example provides an integrated device including a substrate and a first transistor over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact over the gate and a contact interconnect coupled to the second gate contact, where the contact interconnect is directly electrically coupled to only the gate contact.

[0009] Still another example provides a method for fabricating an integrated device. The method provides a substrate. The method forms a first transistor over the substrate, where the first transistor includes a gate. The method forms a first gate contact over the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The method forms a second gate contact over the gate, where the second gate contact is directly electrically coupled to only the gate. BRIEF DESCRIPTION OF DRAWINGS

[0010] Various features, nature, and advantages can become apparent from the detailed description set forth below, considered in connection with the attached drawings, in which like reference numerals are used to identify correspondingly throughout the several views.

[0011] Figure 1 A planar field effect transistor (FET) is shown.

[0012] Figure 2 An example of a fin field effect transistor (FET) (finFET) coupled to a gate contact is shown.

[0013] Figure 3 An example of a finFET coupled to at least one dummy gate contact is shown.

[0014] Figure 4 Examples of various positions of a gate contact relative to a transistor are shown.

[0015] Figure 5 An example of a finFET coupled to a gate contact is shown.

[0016] Figure 6 An example of a finFET coupled to a gate contact is shown.

[0017] Figure 7 An example of a finFET coupled to a gate contact and a dummy gate contact is shown.

[0018] Figure 8 An example of a finFET coupled to a gate contact and a dummy gate contact is shown.

[0019] Figure 9 An example of a finFET coupled to a gate contact and dummy gate contact is shown.

[0020] Figure 10 An example of a finFET coupled to a gate contact and dummy gate contact is shown.

[0021] Figure 11 An example of a finFET coupled to a gate contact and dummy gate contact is shown.

[0022] Figure 12 A sequence for coupling a gate contact and dummy gate contact to a transistor is shown.

[0023] FIG. 13 (including Figures 13A-13D ) shows an exemplary sequence for fabricating a finFET coupled to a dummy gate contact.

[0024] Figure 14 An exemplary flowchart of a method for fabricating a finFET coupled to a dummy gate contact is shown.

[0025] Figure 15 A gate all around (GAA) FET coupled to a dummy gate contact is shown.

[0026] Figure 16 A view of an integrated device including a transistor coupled to a dummy gate contact is shown.

[0027] FIG. 17 (including Figures 17A-17B ) shows an exemplary sequence for fabricating an integrated device including a transistor coupled to a dummy gate contact.

[0028] Figure 18 An exemplary flowchart of a method for fabricating an integrated device including a transistor coupled to a dummy gate contact is shown.

[0029] Figure 19 Various electronic devices that can integrate a die, integrated device, integrated passive device (IPD), device package, package, integrated circuit, and / or PCB as described herein are shown. DETAILED DESCRIPTION

[0030] In the following description, specific details are given to provide a thorough understanding of the various aspects of the disclosure. However, a person skilled in the art will understand that the aspects can be practiced without these specific details. For example, circuits can be shown in block diagrams in order to avoid obscuring aspects of the disclosure in unnecessary detail. In other instances, well-known circuits, structures and techniques can not be shown in detail in order to avoid obscuring aspects of the disclosure.

[0031] The disclosure describes an integrated device that includes a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is directly electrically coupled only to the gate. The integrated device can include a second transistor located over the substrate, where the second transistor includes the gate. The second gate contact is configured to adjust (e.g., lower) a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor. The first transistor can be a p-channel field effect transistor (PFET) and the second transistor can be an n-channel field effect transistor (NFET). The integrated device in a device can operate under different operating conditions, and thus the ability to adjust the threshold voltage required to induce a current in one or more transistors can help optimize the performance of the integrated device of the device.

[0032] Exemplary transistors coupled to gate contacts and dummy gate contacts

[0033] Figure 2An example of a transistor 200 formed in an integrated device is shown. The transistor 200 can comprise a fin field effect transistor (FET). The transistor 200 includes a substrate 202, an oxide 204, a fin 205, a source 206, a drain 208, a gate oxide 209, and a gate 210. The oxide 204 is located on the substrate 202. The source 206 can be a portion of the fin 205 configured as a source of the transistor 200. The drain 208 can be a portion of the fin 205 configured as a drain of the transistor 200. The fin 205 is located on the substrate 202. The fin 205 can be a portion of the substrate 202. The fin 205 can be at least partially located in the oxide 204. The source 206 can be defined by a first portion of the fin 205 and the drain 208 can be defined by a second portion of the fin 205. The gate oxide 209 is located on the oxide 204 and the fin 205. The gate 210 is located on the oxide 204 and the fin 205. The gate oxide 209 can be located between the gate 210 and the oxide 204 and between the gate 210 and the fin 205. Although not shown, the substrate 202 can include a well doped with N-type dopants or P-type dopants. The type of dopants used in the well can specify whether the transistor 200 is an N-type transistor or a P-type transistor.

[0034] A gate contact 250 is coupled to the transistor 200. In particular, the gate contact 250 is coupled to the gate 210 of the transistor 200. A contact interconnect 260 is coupled to the gate contact 250. An interconnect 270 (e.g., an Ml layer interconnect of the integrated device) can be coupled to the contact interconnect 260.

[0035] A current flowing between the source 206 and the drain 208 can be induced when a voltage is applied between the gate 210 and the substrate 202. The voltage can be applied to the gate 210 through the interconnect 270, the contact interconnect 260, and the gate contact 250. The gate contact 250 can be a drive gate contact at which the voltage is applied. The transistor 200 can require a threshold voltage (Vt) to be applied to the gate 210 for a current to flow between the source 206 and the drain 208. The threshold voltage can be a minimum voltage. In some implementations, a minimum voltage applied to a gate (e.g., the gate 210) can be equal to or greater than the threshold voltage of the gate. As described further below, one or more transistors of an integrated device can be configured in such a way (i.e., requiring a low threshold voltage) so as to induce a flow of current in the one or more transistors. Similarly, one or more transistors of an integrated device can be configured in such a way (i.e., requiring a high threshold voltage) so as to induce a flow of current in the one or more transistors.

[0036] Figure 3A structure 300 including a first transistor 301 and a second transistor 302 is shown. The structure 300 can be implemented in an integrated device. The structure 300 can be part of a device-level cell of an integrated device.

[0037] The structure 300 includes a substrate 202, an oxide 204, a plurality of fins 205, a gate oxide 209, and a gate 210. The plurality of fins 205 includes several fins (e.g., 205a, 205b, 205c, 205d). Each of the fins from the plurality of fins 205 includes a respective source and a respective drain, as shown in Figure 2

[0038] The first transistor 301 includes the substrate 202, the oxide 204, the fin 205a, the fin 205b, the gate oxide 209, and the gate 210. The fin 205a can have a source and a drain. Similarly, the fin 205b can have a source and a drain. The second transistor 302 includes the substrate 202, the oxide 204, the fin 205c, the fin 205d, the gate oxide 209, and the gate 210. The fin 205c can have a source and a drain. Similarly, the fin 205d can have a source and a drain. In this example, the first transistor 301 and the second transistor 302 share the same gate (e.g., 210). However, in some implementations, the first transistor 301 and the second transistor 302 can have different gates. It should be noted that not all components are shown in Figure 3

[0039] Figure 3 ​​A p-channel field effect transistor (PFET) active region 310, an n-channel field effect transistor (NFET) active region 320, and a field region 330 are shown. The field region 330 is between the PFET active region 310 and the NFET active region 320. Although not shown, the substrate 202 can include a well doped with N-type dopants or P-type dopants. The type of dopants used in the well can dictate whether a transistor is an N-type transistor or a P-type transistor. The PFET active region 310 can include a portion of the substrate 202 that includes one or more wells with N-type dopants. The NFET active region 320 can include a portion of the substrate 202 that includes one or more wells with P-type dopants. A first transistor 301 includes the PFET active region 310 and / or is located in the PFET active region 310. The first transistor 301 can be configured as a p-type metal-oxide-semiconductor (PMOS) transistor. A second transistor 302 includes the NFET active region 320 and / or is located in the NFET active region 320. The second transistor 302 can be configured as an n-type metal-oxide-semiconductor (NMOS) transistor. The first transistor 301 and the second transistor 302 are each defined by two fins (e.g., a first fin, a second fin). However, different implementations can employ a different number of fins (e.g., one or more fins) to define a transistor.

[0040] Figure 3 Several gate contacts are shown coupled to the gate 210. In particular, a gate contact 250a, a gate contact 250b, a gate contact 250c, a gate contact 250d, and a gate contact 250e are coupled to the gate 210 (e.g., to different portions of the gate 210). The gate contact 250a and the gate contact 250b are over the PFET active region 310. In particular, the gate contact 250a is over the fin 205a, and the gate contact 250b is over the fin 205b. The gate contact 250c and the gate contact 250d are over the NFET active region 320. In particular, the gate contact 250c is over the fin 205c, and the gate contact 250d is over the fin 205d. The gate contact 250e is over the field region 330. A contact interconnect 260e is coupled to the gate contact 250e. In some implementations, the contact interconnect 260e can be considered a portion of the gate contact 250e. An interconnect 270e is coupled to the contact interconnect 260e. In some implementations, the interconnect 270e can be directly coupled to the gate contact 250e. The gate contacts (e.g., 250) can be configured to be electrically coupled to interconnects (e.g., of an Ml metal layer) of an integrated device.

[0041] A voltage can be applied to the gate 210 through the interconnect 270e, the contact interconnect 260e, and the gate contact 250e. The gate contact 250e can be a drive gate contact at which the voltage is applied. When a threshold voltage (Vt) is applied between the gate 210 and the substrate 202, a first current can flow through the source and drain of the first transistor 301 (defined by the fins 205a and 205b), and a second current can flow through the source and drain of the second transistor 302 (defined by the fins 205c and 205d). As mentioned above, the first transistor 301 can operate as a different transistor than the second transistor 302. As such, each transistor requires a different threshold voltage to induce current flow. In some implementations, to induce current flow in both transistors, the voltage provided at the gate 210 must be higher than the threshold voltage of the first transistor 301 and the second transistor 302.

[0042] It is possible to adjust and / or tune the threshold voltage required to induce current flow by setting the location at which the gate contact is coupled to the gate 210, and / or by coupling one or more dummy gate contacts. In the example of FIG. 3, the gate contact 250e is coupled to the gate 210 at a location that is approximately in the center of the field region 330. However, in other implementations, the gate contact 250e can be located in a different portion of the field region 330. Figure 3 In the example of FIG. 3, the gate contact 250e is approximately in the center of the field region 330. However, in other implementations, the gate contact 250e can be located in a different portion of the field region 330. Figure 3 The gate contact 250e is shown as a drive gate contact. However, different implementations can employ any of these gate contacts as a drive gate contact. Figure 3Some of the gate contacts (e.g., 250a, 250b, 250c, 250d) coupled to gate 210 are not directly coupled to other interconnects. That is, these gate contacts are directly coupled only to gate 210, but not directly coupled to other interconnects (e.g., contact interconnects 260, interconnects 270). These gate contacts (e.g., 250a, 250b, 250c, 250d) can be considered dummy gate contacts. Interconnects (e.g., 270b, 270d) may be located above some of the gate contacts (e.g., 250a, 250b, 250c, 250d). Contact interconnects 260a and 260c are coupled to gate contacts 250a and 250c, respectively. However, contact interconnects 260a and 260c are not directly coupled to other interconnects (e.g., interconnects on layer M1). Although gate contacts 250a and 250c are coupled to corresponding contact interconnects 260a and 260c, both gate contacts 250a and 250c can be considered dummy gate contacts. Gate contacts 250a and 250c can be considered dummy gate contacts because neither is a driving gate contact. In some embodiments, contact interconnect 260a is considered a portion of gate contact 250a, and contact interconnect 260c is considered a portion of gate contact 250c.

[0043] As further described below, the formation or fabrication process of one or more gate contacts (e.g., one or more dummy gate contacts) can cause ions (e.g., oxygen ions) to diffuse into the gate and / or fins, which will change the work function of the transistor and thus regulate the drive strength and / or voltage threshold of the transistor. For example, forming at least one gate contact (e.g., a dummy gate contact) closer to the PFET can allow more ions to diffuse into the PFET (compared to the NFET). Forming at least one gate contact (e.g., a dummy gate contact) closer to the NFET can allow more ions to diffuse into the NFET (compared to the PFET). At least one dummy gate contact can be a mechanism for regulating the voltage required to induce current (e.g., a first current, a second current) in at least one transistor (e.g., a first transistor, a second transistor).

[0044] Dummy gate contacts (e.g., 250a, 250b, 250c, 250d) are coupled (e.g., directly coupled) to different portions of gate 210 to regulate (e.g., decrease, increase) the threshold voltage required to initiate current flow in the first transistor 301 and / or the second transistor 302. Figure 3In the example of FIG. 3, there are four dummy gate contacts. However, as further described below, different implementations can have different numbers of dummy gate contacts. Moreover, the location of the dummy gate contacts can vary from implementation to implementation. Different implementations can have different dimensions for the fin, gate contact(s), and / or gate. For example, in some implementations, the fin (e.g., 205a, 205b, 205c, 205d) can have a fin width of approximately 4 to 10 nanometers (nm). In some implementations, the gate (e.g., 210) can have a length of approximately 8 to 14 nanometers (nm). In some implementations, the gate contact (e.g., 250a, 250b, 250c, 250d) can have a lateral dimension (e.g., along the X and Y axes) of approximately 15 to 25 nanometers (nm). However, different implementations can have different dimensions for the fin, gate contact, and / or gate.

[0045] Figure 4 Three examples are shown of how the location of the gate contact can affect the threshold voltage (Vt) needed to induce current in the PFET and NFET. Figure 4 (i) a first configuration 401 in which the location of the gate contact is close to the NFET and offset from the PFET, (ii) a second configuration 402 in which the location of the gate contact is halfway between the PFET and NFET, and (iii) a third configuration 403 in which the location of the gate contact is close to the PFET and offset from the NFET.

[0046] As shown in graph 410, when the gate contact is close to the PFET (C), the threshold voltage needed to induce current in the PFET drops by approximately 7 millivolts (mV). When the gate contact is between the PFET and NFET (B), the threshold voltage needed to induce current in the PFET does not change much. When the gate contact is close to the NFET (A) and offset from the PFET, the threshold voltage needed to induce current in the PFET increases by approximately 4 millivolts (mV).

[0047] As shown in graph 420, when the gate contact is close to the NFET (D), the threshold voltage needed to induce current in the NFET increases by approximately 15 millivolts (mV). When the gate contact is between the PFET and NFET (E), the threshold voltage needed to induce current in the PFET does not change much. When the gate contact is close to the PFET (F) and offset from the NFET, the threshold voltage needed to induce current in the PFET drops by approximately 7 millivolts (mV).

[0048] The placement of the gate contact is important because the formation or fabrication process of the gate contact can cause ions (e.g., oxygen ions) to diffuse into the gate and / or fin, which will change the work function of the transistor and thus modulate the drive strength and / or voltage threshold of the transistor. A gate contact closer to the PFET can cause more ions to diffuse into the PFET (compared to the NFET). A gate contact closer to the NFET can cause more ions to diffuse into the NFET (compared to the PFET).

[0049] Thus, as shown in graphs 410 and 420, positioning the gate contact closer to the PFET will lower the threshold voltage required to initiate current flow in both the PFET and the NFET. This means that positioning the gate contact closer to the PFET will increase the drive strength of the PFET and the NFET. In contrast, positioning the gate contact closer to the NFET will increase the threshold voltage required to initiate current flow in both the PFET and the NFET. This means that positioning the gate contact closer to the PFET will decrease the drive strength of the PFET and the NFET.

[0050] To further modulate the transistor, change the drive strength of the gate contact, and / or change the threshold voltage of the transistor, a dummy gate contact can be coupled to the gate. The placement and formation of at least one dummy gate contact over the gate can cause additional ions (e.g., oxygen ions) to diffuse into the gate and / or fin. The above-mentioned ion diffusion can be considered a metal gate function change resulting from the gate contact and / or dummy gate contact etch process, which is described further below at least in Figure 13C For example, forming at least one gate contact (and / or at least one dummy gate contact) closer to the PFET can cause more ions to diffuse into the PFET (compared to the NFET). Forming at least one gate contact (and / or at least one dummy gate contact) closer to the NFET can cause more ions to diffuse into the NFET (compared to the PFET). As mentioned above, the at least one dummy gate contact can be a mechanism for modulating the threshold voltage required to initiate current flow in the transistor.

[0051] Figures 5-11 Various examples are shown of how the gate contact and / or dummy gate contact can be coupled to the gate. It should be noted that, Figure 3 and Figures 5-11The examples shown in the middle are not limiting, and other implementations can include other configurations. As shown below, the formation of dummy gate contacts can cause more ions to diffuse into the NFET and / or PFET, which will modulate the transistor(s), change the drive strength of the gate contacts, and / or change the threshold voltage of the transistor(s). How many ions diffuse into the NFET and / or PFET can depend on the location and size of the gate contacts and / or dummy gate contacts, as well as the number of dummy gate contacts. For example, more dummy gate contacts can mean more ions being diffused. The larger the size of the gate contact(s) and / or dummy gate contacts can mean the more ions being diffused.

[0052] Figure 5 A structure 500 including a first transistor 501 and a second transistor 502 is shown. The structure 500 is similar to the structure 300, and includes the same or similar components as the structure 300. The first transistor 501 is similar to the first transistor 301, and includes the same or similar components as the first transistor 301. The second transistor 502 is similar to the second transistor 302, and includes the same or similar components as the second transistor 302. Figure 5 A gate contact 250f is shown, which is coupled to a portion of the gate 210 proximate to the fin 205c. The gate contact 250f is located in the field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260f is coupled to the gate contact 250f. An interconnect 270f is coupled to the contact interconnect 260f.

[0053] Figure 6 A structure 600 including a first transistor 601 and a second transistor 602 is shown. The structure 600 is similar to the structure 300, and includes the same or similar components as the structure 300. The first transistor 601 is similar to the first transistor 301, and includes the same or similar components as the first transistor 301. The second transistor 602 is similar to the second transistor 302, and includes the same or similar components as the second transistor 302. Figure 6 A gate contact 250g is shown, which is coupled to a portion of the gate 210 proximate to the fin 205b. The gate contact 250g is located in the field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260g is coupled to the gate contact 250g. An interconnect 270g is coupled to the contact interconnect 260g.

[0054] Figure 7A structure 700 including a first transistor 701 and a second transistor 702 is shown. The structure 700 is similar to the structure 300 and includes the same or similar components as the structure 300. The first transistor 701 is similar to the first transistor 301 and includes the same or similar components as the first transistor 301. The second transistor 702 is similar to the second transistor 302 and includes the same or similar components as the second transistor 302. Figure 7 A gate contact 250g is shown that is coupled to a portion of the gate 210 proximate to the fin 205b. A gate contact 250h is coupled to another portion of the gate 210 proximate to the fin 205c. The gate contact 250h can be a dummy gate contact. The gate contact 250g and the gate contact 250h are located in the field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260g is coupled to the gate contact 250g. An interconnect 270g is coupled to the contact interconnect 260g. The gate contact 250h is only directly coupled (e.g., directly electrically coupled) to the gate 210, which can mean that the gate contact 250h does not have a direct coupling (e.g., a direct electrical coupling) to other interconnects. An interconnect 270h can be located over the gate contact 250h. The gate contact 250h can not be used as a drive gate contact.

[0055] Figure 8 A structure 800 including a first transistor 801 and a second transistor 802 is shown. The structure 800 is similar to the structure 300 and includes the same or similar components as the structure 300. The first transistor 801 is similar to the first transistor 301 and includes the same or similar components as the first transistor 301. The second transistor 802 is similar to the second transistor 302 and includes the same or similar components as the second transistor 302. Figure 8 A gate contact 250i is shown that is coupled to a portion of the gate 210 proximate to the fin 205c. A gate contact 250j is coupled to another portion of the gate 210 proximate to the fin 205b. The gate contact 250j can be a dummy gate contact. The gate contact 250i and the gate contact 250j are located in the field region 330 between the PFET active region 310 and the NFET active region 320. A contact interconnect 260i is coupled to the gate contact 250i. An interconnect 270i is coupled to the contact interconnect 260i. The gate contact 250j is only directly coupled (e.g., directly electrically coupled) to the gate 210 and does not have a direct coupling (e.g., a direct electrical coupling) to other interconnects. An interconnect 270j can be located over the gate contact 250h.

[0056] Figure 9Structures 900a and 900b are shown each including a first transistor 901 and a second transistor 902. The first transistor 901 is similar to the first transistor 301 and includes similar components as the first transistor 301. The second transistor 902 is similar to the second transistor 302 and includes similar components as the second transistor 302. Figure 9 Examples of structures with low drive strength (e.g., high threshold voltage (Vt)) for NFETs and PFETs are shown.

[0057] Figure 9 A gate contact 250n is shown that is coupled to a portion of the gate 210 between the fin 205c and the fin 205d of the structure 900a. The gate contact 250n is located over the NFET active region 320. A contact interconnect 260n is coupled to the gate contact 250n. An interconnect 270n is coupled to the contact interconnect 260n.

[0058] Figure 9 A gate contact 250c is shown that is coupled to a portion of the gate 210 above the fin 205c of the structure 900b, and a gate contact 250d is shown that is coupled to a portion of the gate 210 above the fin 205d of the structure 900b. The gate contact 250c and the gate contact 250d are located in the NFET active region 320. The gate contact 250c is a dummy gate. A contact interconnect 260d is coupled to the gate contact 250d. An interconnect 270d is coupled to the contact interconnect 260d. In some implementations, the gate contact 250d can be a dummy gate, and the gate contact 250c can be coupled to an interconnect. In such cases, a contact interconnect (e.g., 260c) can be coupled to the gate contact 250c, and the gate contact 250d is not coupled to the contact interconnect 260d.

[0059] Figure 10 Structures 1000a and 1000b are shown each including a first transistor 1001 and a second transistor 1002. The first transistor 1001 is similar to the first transistor 301 and includes similar components as the first transistor 301. The second transistor 1002 is similar to the second transistor 302 and includes similar components as the second transistor 302. Figure 10 Examples of structures with high drive strength (e.g., low threshold voltage (Vt)) for NFETs and PFETs are shown.

[0060] Figure 10A gate contact 250p is shown that is coupled to a portion of the gate 210 between the fin 205a and the fin 205b of the structure 1000a. The gate contact 250p is over the PFET active region 310. A contact interconnect 260p is coupled to the gate contact 250p. An interconnect 270p is coupled to the contact interconnect 260p.

[0061] Figure 10 A gate contact 250a is shown that is coupled to a portion of the gate 210 over the fin 205a of the structure 1000b. A gate contact 250b is shown that is coupled to a portion of the gate 210 over the fin 205b of the structure 1000b. The gate contact 250a and the gate contact 250b are in the PFET active region 310. The gate contact 250a is a dummy gate. A contact interconnect 260b is coupled to the gate contact 250b. An interconnect 270b is coupled to the contact interconnect 260b. In some embodiments, the gate contact 250b can be a dummy gate, and the gate contact 250a can be coupled to an interconnect. In such cases, a contact interconnect (e.g., 260a) can be coupled to the gate contact 250a, and the gate contact 250b is not coupled to the contact interconnect 260b.

[0062] Figure 11 Structures 1100a and 1100b are shown that each include a first transistor 1101 and a second transistor 1102. The first transistor 1101 is similar to the first transistor 301 and includes similar components to the first transistor 301. The second transistor 1102 is similar to the second transistor 302 and includes similar components to the second transistor 302. Figure 11 An example of a structure that has a high drive strength (e.g., low threshold voltage (Vt)) for PFETs and a low drive strength (e.g., high drive voltage (Vt)) for NFETs is shown.

[0063] Figure 11 A gate contact 250p is shown that is coupled to a portion of the gate 210 between the fin 205a and the fin 205b of the structure 1100a. The gate contact 250p is in the PFET active region 310. A contact interconnect 260p is coupled to the gate contact 250p. An interconnect 270p is coupled to the contact interconnect 260p.

[0064] Figure 11A gate contact 250n is also shown, which is coupled to a portion of the gate 210 between the fin 205c and the fin 205d of the structure 1100a. The gate contact 250n is in the NFET active region 320. The gate contact 250n can be a dummy gate contact.

[0065] In some implementations, the configuration shown for the structure 1100a can be different. That is, the structure 1100a can be modified such that the gate contact 250p is a dummy gate, and the gate contact 250n is a drive gate contact. In such a modification, a contact interconnect (e.g., 260p) can be coupled to the gate contact 250n (rather than the gate contact 250p), and the gate contact 250p is not coupled to the contact interconnect 260p.

[0066] Figure 11 A gate contact 250a is shown that is coupled to a portion of the gate 210 over the fin 205a of the structure 1100b, a gate contact 250b that is coupled to a portion of the gate 210 over the fin 205b of the structure 1100b, a gate contact 250c that is coupled to a portion of the gate 210 over the fin 205c of the structure 1100b, and a gate contact 250d that is coupled to a portion of the gate 210 over the fin 205d of the structure 1100b. The gate contact 250a and the gate contact 250b are in the PFET active region 310. The gate contact 250c and the gate contact 250d are in the NFET active region 320. The gate contact 250a, the gate contact 250b, and the gate contact 250c are dummy gate contacts. A contact interconnect 260b is coupled to the gate contact 250b. The contact interconnect 260b can be a dummy contact interconnect because the contact interconnect 260b is not directly coupled to an interconnect. A contact interconnect 260d is coupled to the gate contact 250d. An interconnect 270d is coupled to the contact interconnect 260d. The gate contact 250d is a drive gate contact through which a voltage is transmitted to the gate 210. However, any of the gate contacts can be a drive gate contact.

[0067] Exemplary sequence for fabricating a structure including a transistor coupled to a dummy gate contact

[0068] In some implementations, fabricating a structure coupled to a dummy gate includes several processes. Figure 12 An exemplary sequence for providing or fabricating a structure coupled to a dummy gate is shown. In some implementations, Figure 12 The sequence of FIG. 1 1 can be used to provide or fabricate the structures described in this disclosure. Figure 3 andFigures 5-11 The structure. Furthermore, the sequence used to create the structure can be used to create several structures simultaneously.

[0069] It should be pointed out that, Figure 12 The sequence can be combined with one or more stages to simplify and / or clarify the sequence used to provide or fabricate the structure coupled to the dummy gate. In some embodiments, the order of the processes can be changed or modified. In some embodiments, one or more of the processes can be substituted or replaced without departing from the spirit of this disclosure.

[0070] like Figure 12 Phase 1 shown illustrates the state after structure 1200 is provided. Structure 1200 includes a substrate, multiple fins 205, multiple gates 210, a PFET active region 310, an NFET active region 320, and multiple gate contacts 250. A front-end (FEOL) process can be used to provide (e.g., fabricate) the multiple fins 205, multiple gates 210, PFET active region 310, NFET active region 320, and multiple gate contacts 250.

[0071] Phase 2 illustrates the state after contact interconnects 260 have been formed over some of the gate contacts 250. When contact interconnects 260 are not formed over the gate contacts, these gate contacts are considered dummy gate contacts. Contact interconnects can be formed using a plating process.

[0072] Stage 3 illustrates the state after interconnect 270 is formed on contact interconnect 260. Interconnect 270 can be an M1 layer interconnect of an integrated device. Contact interconnects can be formed using a plating process.

[0073] A high-level description of how to fabricate the structure and dummy gate contacts has already been described; the sequence for fabricating the structure and dummy gate contacts will now be described in more detail below. An exemplary sequence for fabricating a transistor structure including a dummy gate contact is provided.

[0074] In some embodiments, fabricating the structure coupled to the dummy gate contact includes several processes. Figure 13 (including...) Figures 13A-13D This illustrates an exemplary sequence of structures for providing or fabricating coupling to dummy gate contacts. In some embodiments, Figures 13A-13D The sequence can be used to provide or create coupling to Figure 3 and Figures 5-11 The structure of the dummy gate contact. Furthermore, the sequence for fabricating the structures coupled to the dummy gate contact can be used to fabricate several structures simultaneously. However, for clarity, the sequence in Figure 13 shows the fabrication of only one structure.

[0075] It should be pointed out that,Figures 13A-13D The sequence of processes can be combined with one or more stages to simplify and / or clarify the sequence used to provide or fabricate the structure coupled to the dummy gate. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the spirit of this disclosure.

[0076] like Figure 13A Stage 1 shown illustrates the state after substrate 202 has been provided. Different embodiments may provide different materials for substrate 202. In some embodiments, substrate 202 may include silicon (Si). In some embodiments, substrate 202 may already contain dopants. In some embodiments, substrate 202 may be doped with p-type or n-type dopants. Substrate 202 may include wells (e.g., N-well, P-well).

[0077] Stage 2 illustrates the state after fins 205 have been formed on substrate 202. The process of forming fins 205 includes forming trenches 1305 in substrate 202. A hard mask and a photoresist (e.g., a patterned photoresist) may be positioned on substrate 202. Fins 205 may be etched using an etching process (e.g., an anisotropic etching process). Fins 205 may include multiple fins (e.g., 205a, 205b, 205c, 205d).

[0078] Stage 3 illustrates the state after oxide 204 is formed on substrate 202 and trench 1305 such that oxide 204 is positioned between fins 205. Oxide 204 can be formed using oxide deposition processes. Planarization processes such as chemical mechanical polishing (CMP) can be used to planarize oxide 204.

[0079] like Figure 13B Stage 4 shown illustrates the state after the oxide recess, where a portion of oxide 204 has been further removed. Another etching process can be used to remove the portion of oxide 204, thereby exposing the side portions of fin 205.

[0080] Stage 5 shows the state after the gate oxide 209 has been formed over the portions of oxide 204 and fin 205. The gate oxide 209 can be formed using a deposition process.

[0081] Stage 6 illustrates the state after the gate 210 is formed over the fin 205 and oxide 204. The gate 210 may be formed over the gate oxide 209. The gate 210 may comprise a polysilicon layer doped with a dopant (e.g., N+ dopant). As shown in Stage 6, the gate 210 surrounds three sides of the fin 205.

[0082] likeFigure 13C Stage 7, shown in FIG. 7, illustrates a state after one or more gate contacts 250 (e.g., 250a, 250b, 250c, 250d, 250e) are formed over portions of the gate 210. In this example, the gate contact 250a is over the fin 205a, the gate contact 250b is over the fin 205b, the gate contact 250c is over the fin 205c, and the gate contact 250d is over the fin 205d. The gate contact 250e is between the gate contact 250b and the gate contact 250c. The gate contacts 250 can be formed using a plating and etching process. As described further below, at least one of the gate contacts can be a dummy gate contact. As mentioned above, the process of forming the gate contacts 250 can cause ions (e.g., oxygen ions) to diffuse into the fins 205. How many ions diffuse from a respective gate contact (e.g., dummy gate contact) into a respective fin can depend on the size and location of each particular gate contact (e.g., dummy gate contact). The number and / or amount of ions in the fins 205 can affect the transistor’s work function, which will affect the transistor’s gate contact drive strength as well as threshold voltage. Stage 7 conceptually illustrates an example of how ions from a gate contact (e.g., dummy gate contact) can diffuse into a fin.

[0083] Stage 8 illustrates a state after at least one contact interconnect 260 is formed over the gate contacts 250. The contact interconnect 260 can be formed using a plating process. The contact interconnect 260e is coupled to the gate contact 250e.

[0084] As Figure 13D Stage 9, shown in FIG. 9, illustrates a state after an interconnect 270 is formed. The interconnect 270 can be formed using a plating process. The interconnect 270 can be an Ml layer interconnect of the integrated device. The interconnect 270 can be formed such that the interconnect 270e is coupled to the contact interconnect 260e. Stage 9 can illustrate an example of a structure 300 coupled to at least one dummy gate contact. The dummy gate contact can be considered part of the structure 300.

[0085] Although not shown for purposes of clarity, one or more dielectric layers can be formed over and / or around the fins 205, the gate 210, the gate contacts 250, the contact interconnect 260, and / or the interconnect 270.

[0086] Example flow diagram of a method for fabricating a structure including a transistor coupled to a dummy gate contact

[0087] In some implementations, fabricating a structure coupled to a dummy gate contact includes several processes.Figure 14 An exemplary flowchart of a method 1400 for providing or fabricating a structure coupled to a dummy gate contact is shown. In some embodiments, Figure 14 Method 1400 can be used to provide or make the product described in this disclosure. Figure 3 and Figures 5-11 The structure is coupled to the dummy gate contact.

[0088] It should be pointed out that, Figure 14 The method may combine one or more processes to simplify and / or clarify the methods used to provide or fabricate structures coupled to dummy gate contacts. In some implementations, the order of the processes may be changed or modified.

[0089] The method (at 1405) provides a substrate 202. Substrate 202 may include silicon. Substrate 202 may be doped with a P-type dopant or an N-type dopant. Substrate 202 may include a well (e.g., an N-well, a P-well). Figure 13A Phase 1 can be illustrated by providing an example of substrate 202.

[0090] This method (at 1410) forms fins 205 in the substrate. The fins can be formed using masking, resist, and etching processes. Fins 205 can be formed by forming trenches 1305 in the substrate 202. Separate portions of the fins can form the bases for the source and drain electrodes of a transistor. Figure 13A Stage 2 can be illustrated as an example of forming fins in a substrate.

[0091] This method (at 1415) forms oxide 204 on substrate 202 and in trench 1305 such that oxide 204 is between fins 205. Oxide 204 can be formed using an oxide deposition process. Planarization processes such as chemical mechanical polishing (CMP) can be used to planarize oxide 204. Figure 13A Stage 3 can be illustrated with an example of oxide formation.

[0092] This method (at 1420) removes a portion of oxide 204. Oxide recessing can be used to remove a portion of oxide 204. Etching can be used to remove a portion of oxide 204, thereby exposing the side portions of fin 205. Figure 13B Stage 4 can show the state after the oxide depression.

[0093] This method (at 1425) forms a gate oxide 209 over portions of oxide 204 and fin 205. The gate oxide 209 can be formed using a deposition process. Figure 13BStage 5 of FIG. 1 can illustrate an example of forming a gate oxide.

[0094] The method (at 1430) forms gates 210 over the fins 205 and the oxide 204. The gates 210 can be formed over the gate oxide 209. The gates 210 can include a polysilicon layer doped with a dopant (e.g., N+ dopant). The gates 210 can be formed using a deposition process. Figure 13B Stage 6 of FIG. 1 can illustrate an example of forming gates over fins.

[0095] The method (at 1435) forms gate contacts 250 over the gates 210. At least one of the gate contacts can be a dummy gate contact, and at least one of the gate contacts can be a driven gate contact configured to provide a voltage to the gate 210. The gate contacts 250 can be formed using a plating process. Figure 13C Stage 7 of FIG. 1 can illustrate an example of providing dummy gate contacts.

[0096] The method (at 1440) forms at least one contact interconnect 260 over the at least one gate contact 250. The contact interconnect 260 can be formed using a plating process. In some implementations, a gate contact defined as a dummy gate contact can not have a contact interconnect coupled thereto. Figure 13C Stage 8 of FIG. 1 can illustrate an example of forming contact interconnects. In some implementations, at least one of the contact interconnects can be a dummy contact interconnect.

[0097] The method (at 1445) forms interconnects 270 over the structure. In particular, the interconnects 270 can be formed over the at least one gate contact 250 and / or over the at least one contact interconnect 260. The interconnects 270 can be formed using a plating process. The interconnects 270 can be Ml layer interconnects of an integrated device. Figure 13D Stage 9 of FIG. 1 can illustrate a state after forming the interconnects 270.

[0098] Example integrated device including transistors and dummy gate contacts

[0099] The use of dummy gate contacts is not limited to finFETs. Dummy gate contacts as in the present disclosure can be applicable to other transistors, such as planar FET transistors 200 and gate-all-around (GAA) FETs. Figure 15An example of a structure 1500 including a first GAA FET 1501 and a second GAA FET 1502 is shown. The first GAA FET 1501 includes a substrate 202, a source 1506a, a drain 1508a, a plurality of channels 1509a, and a gate 1510. The second GAA FET 1502 includes the substrate 202, a source 1506b (not shown), a drain 1508b, a plurality of channels 1509b, and the gate 1510.

[0100] A gate contact 1550a and a gate contact 1550b are coupled to the gate 1510. The gate contact 1550a can be a dummy gate contact and the gate contact 1550b can be a drive gate contact. A contact interconnect 1560 is coupled to the gate contact 1550b. An interconnect 1570 is coupled to the contact interconnect 1560. The structure 1500, the first GAA FET 1501, and / or the second GAA FET 1502 can be implemented in any integrated device described in the present disclosure. Any dummy gate contact described in the present disclosure can be implemented over the structure 1500, the first GAA FET 1501, and / or the second GAA FET 1502. The GAA FETs can be fabricated using processes known to those skilled in the art.

[0101] Exemplary integrated device including a transistor and a dummy gate contact

[0102] Figure 16 A cross-sectional view of an integrated device 1600 including transistors and dummy gate contacts is shown. The integrated device 1600 includes a substrate 1620, a plurality of device-level units 1622 (e.g., logic units), an interconnect portion 1604, and a packaging portion 1606. The plurality of device-level units 1622 are formed over the substrate 1620. The plurality of device-level units 1622 can form a device-level layer of the integrated device 1600. In some implementations, the plurality of device-level units 1622 can include portions of the substrate 1620. In some implementations, the substrate 1620, the device-level layer, and the plurality of device-level units 1622 can be referred to as a substrate portion 1602 of the integrated device 1600.

[0103] The plurality of device-level units 1622 can include one or more transistors. As shown in FIG. 16A, one of the device-level units includes a structure 700 (e.g., a dummy gate contact) and a structure 800 (e.g., a drive gate contact). The structure 700 includes a dummy gate contact 710 and a dummy gate contact 720. The structure 800 includes a drive gate contact 810 and a drive gate contact 820. Figure 16 The structure 700 and the structure 800 can be formed over the substrate 1620. The structure 700 and the structure 800 can be formed in a device-level layer of the integrated device 1600. The structure 700 and the structure 800 can be formed in a device-level unit of the plurality of device-level units 1622. Figure 7As shown and described herein, structure 700 includes a transistor coupled to a dummy gate contact. It should be noted that integrated device 1600 can include other types of devices, structures, and / or transistors as described in the present disclosure. In some embodiments, different cells of integrated device 1600 can use different or the same configurations of transistors coupled to gate contacts, contact interconnects, and / or interconnects. Integrated device 1600 can include any configuration of transistors, gate contacts, dummy gate contacts, contact interconnects, and / or dummy contact interconnects described in the present disclosure. Device-level cells 1622 included in integrated device 1600 can have the same configuration of transistors, gate contacts, dummy gate contacts, contact interconnects, and / or dummy contact interconnects; different configurations of transistors, gate contacts, dummy gate contacts, contact interconnects, and / or dummy contact interconnects; and / or a combination thereof. Gate contacts (e.g., 250) can be configured to be electrically coupled to interconnects (e.g., Ml metal layer interconnects) of the integrated device. For example, gate contacts can be configured to be electrically coupled to contact interconnects that are coupled to Ml layer interconnects.

[0104] Interconnect portion 1604 is formed over substrate portion 1602. In particular, interconnect portion 1604 is formed over multiple device-level cells 1622. Interconnect portion 1604 includes a wiring layer. Interconnect portion 1604 includes multiple interconnects 1640 (e.g., traces, pads, vias) and at least one dielectric layer 1642. Interconnect portion 1604 can provide interconnections between multiple transistors. Ml layer interconnects can be part of interconnect portion 1604. Interconnect portion 1604 can include other metal layers (e.g., M2 layer interconnects, M3 layer interconnects).

[0105] Encapsulation portion 1606 is formed over interconnect portion 1604. Encapsulation portion 1606 includes a passivation layer 1660, a bump under bump metallization (UBM) layer 1662, and a solder interconnect 1664. It should be noted that the size and shape of integrated device 1600 is exemplary. Moreover, the components of the illustrated integrated device 1600 can not be drawn to scale.

[0106] Exemplary sequence for fabricating an integrated device including a transistor and a dummy gate contact

[0107] In some embodiments, fabricating an integrated device including a transistor and a dummy gate contact includes several processes. FIG. 17 (including Figures 17A-17B ) illustrates an exemplary sequence for providing or fabricating an integrated device including a transistor and a dummy gate contact. In some embodiments, Figures 17A-17BThe sequence can be used to provide or create Figure 16 The integrated devices and / or other integrated devices described in this disclosure.

[0108] It should be pointed out that, Figures 17A-17B The sequence of processes can be combined with one or more stages to simplify and / or clarify the sequence of processes used to provide or fabricate an integrated device comprising transistors and dummy gate contacts. In some embodiments, the order of processes can be changed or modified. In some embodiments, one or more of these processes can be substituted or replaced without departing from the spirit of this disclosure.

[0109] like Figure 17A Phase 1 shown illustrates the state after substrate 1620 has been provided. Different embodiments may provide different materials for substrate 1620. In some embodiments, substrate 1620 may include silicon (Si). Substrate 1620 may be doped or undoped. Substrate 1620 may be a semi-insulating substrate. The term "undoped" as used in this disclosure may refer to a component without dopant or may include a component with a low level of dopant. Low doping level may be a residual doping level.

[0110] Phase 2 illustrates the state after a device-level layer has been formed on substrate 1620. The device-level layer includes a plurality of device-level cells 1622. Thus, Phase 2 illustrates the state after a plurality of device-level cells 1622 have been formed on substrate 1620. In some embodiments, the device-level layer (e.g., the plurality of device-level cells 1622) may be fabricated using a front-end (FEOL) process. One or more cells from the plurality of device-level cells may include transistors and / or gate contacts, as described above. Device-level cells may include at least a portion of the structures described in this disclosure (e.g., 300, 500, 600, 700, 800, 900a, 900b, 1000a, 1000b, etc.). Figures 13A-13D The diagram illustrates a sequence for fabricating transistors and dummy gate contacts. In some embodiments, interconnects may be formed over the gates, sources, and / or drains of one or more transistors, as well as over the gate contacts and / or contact interconnects.

[0111] Stage 3 illustrates the state after interconnect portion 1604 has been formed. Interconnect portion 1604 may include a plurality of interconnects 1640 (located on different metal layers) and at least one dielectric layer 1642. In some embodiments, interconnect portion 1604 may be fabricated using a back-to-end (BEOL) process. Interconnect portion 1604 may be configured to electrically couple one or more transistors.

[0112] like Figure 17BStage 4 shown in FIG. 16B illustrates a state after a passivation layer 1660 and an under bump metallization (UBM) layer 1662 are formed over the interconnect portion 1604.

[0113] Stage 5 illustrates a state after a solder interconnect is coupled to the under bump metallization (UBM) layer 1662.

[0114] Exemplary flow diagram of a method for fabricating an integrated device including a transistor and a dummy gate contact

[0115] In some embodiments, providing an integrated device including a transistor and a dummy gate contact includes several processes. Figure 18 An exemplary flow diagram of a method 1800 for providing or fabricating an integrated device including a transistor and a dummy gate contact is shown. In some embodiments, Figure 18 The method 1800 can be used to provide or fabricate an integrated device including a transistor and a dummy gate contact and / or other integrated devices described in the present disclosure. Figure 16

[0116] It should be noted that, Figure 18 The methods of the present disclosure can combine one or more processes in order to simplify and / or clarify a method for providing or fabricating an integrated device including a transistor and a dummy gate contact. In some embodiments, the order of the processes can be changed or modified.

[0117] The method provides a substrate (e.g., 1620) (at 1805). Different embodiments can provide different materials for the substrate. In some embodiments, the substrate can include silicon (Si). The substrate can be doped with an N-type dopant or a P-type dopant. The substrate can be a semi-insulating substrate. Figure 17A Stage 1 of FIG. 16A illustrates an example of providing a substrate.

[0118] ​This method (at 1810) forms a device-level layer (e.g., a plurality of device-level cells 1622) on a substrate. In some embodiments, the device-level layer (e.g., the plurality of device-level cells 1622) may be fabricated using a front-end (FEOL) process. The device-level layer may include a plurality of device-level cells. These device-level cells may include one or more active devices. One or more device-level cells may include transistors (e.g., 1102), as described in this disclosure. Forming the device-level layer may include forming one or more transistors and one or more dummy gate contacts. In some embodiments, forming the device-level layer includes forming transistors on a substrate. In some embodiments, forming transistors (e.g., a first transistor) on a substrate includes forming a transistor having a source, a drain, and a gate. This method may form a first gate contact on the gate of the transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of an integrated device (e.g., an interconnect of the M1 layer). This method may form a second gate contact on the gate, wherein the second gate contact is directly electrically coupled to the gate only. Figures 13A-13D as well as Figure 17A An example of forming transistors and dummy gate contacts on a substrate is shown and described in stage 2.

[0119] The method (at 1815) forms an interconnect portion 1604 over a device-level layer (e.g., multiple device-level cells 1622) and / or a substrate 1620. The interconnect portion 1604 may include multiple interconnects 1640 and at least one dielectric layer 1642. In some embodiments, the interconnect portion 1604 may be formed using a back-to-end (BEOL) process. The interconnect portion 1604 may include an M1 layer. The interconnect portion 1604 may be configured to electrically couple one or more transistors. Stage 3 of Figure 20A illustrates an example of forming the interconnect portion 1604.

[0120] The method (at 1820) forms a package portion 1606 over the interconnect portion 1604. The package portion 1606 may include a passivation layer 1660 and an under-bump metallization (UBM) layer 1662. The passivation layer 1660 and the under-bump metallization (UBM) layer 1662 are formed over the interconnect portion 1604. Stage 4 of Figure 20B illustrates an example of forming the package portion 1606.

[0121] This method (at 1825) provides solder interconnect 1664. In some embodiments, solder interconnect 1664 is coupled to under-bump metallization (UBM) layer 1662. Phase 5 of Figure 20B illustrates an example of coupling solder interconnect to package portion 1604.

[0122] It should also be pointed out that, Figure 18The method 1800 can be used to fabricate (e.g., fabricate simultaneously) several integrated devices on a wafer. The wafer is then singulated (e.g., diced) into individual integrated devices. These singulated integrated devices are then coupled to other integrated devices and / or printed circuit boards (PCBs).

[0123] Exemplary Electronic Devices

[0124] Figure 19 Various electronic devices are shown that can integrate any of the above-mentioned transistors, devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, dies, interposers, packages, or package-on-package (PoP). For example, a mobile phone device 1902, a laptop computer device 1904, a fixed location terminal device 1906, or a wearable device 1908 can include a device 1900 as described herein. The device 1900 can be, for example, any of the devices and / or integrated circuit (IC) packages described herein. Figure 19 The devices 1902, 1904, 1906, and 1908 shown in FIG. 19 are merely exemplary. Other electronic devices can also feature the device 1900, including but not limited to the group of devices (e.g., electronic devices) including: mobile devices, hand-held personal communication systems (PCS) units, portable data units such as personal digital assistants, global positioning system (GPS) enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units such as meter reading equipment, communications devices, smartphones, tablet computers, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or combinations thereof.

[0125] Figures 2-12 Figures 13A-13D Figures 14-16 Figures 17A-17B Figures 18-19 One or more of the components, processes, features and / or functions illustrated in FIGS. 1-18 can be rearranged and / or combined into a single component, process, feature or function or embodied in several components, processes, or functions. Additional elements, components, processes, and / or functions can also be added without departing from the disclosure. It should be noted that, Figures 2-12 Figures 13A-13D Figures 14-16 Figures 17A-17B Figures 18-19 and their corresponding description in the disclosure are not limited to dies and / or ICs. In some implementations, Figures 2-12 ,​​​​​​​​Figures 13A-13D 、 Figures 14-16 、 Figures 17A-17B and / or Figures 18-19 Figures 2-12 Figures 13A-13D Figures 14-16 Figures 17A-17B Figures 18-19 and corresponding descriptions can be used to make, create, provide, and / or produce devices and / or integrated devices. In some embodiments, a device can include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a package on package (PoP) device, and / or an interposer.

[0126] It should be noted that the figures in the present disclosure can represent actual and / or conceptual representations of various parts, components, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the figures can not be drawn to scale. In some cases, not all components and / or parts can be shown for purposes of clarity. In some cases, the positioning, location, size, and / or shape of various parts and / or components in the figures can be exemplary. In some embodiments, various components and / or parts in the figures can be optional.

[0127] The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects of the disclosure. Likewise, the term "aspects" does not require that all aspects of the disclosure include the discussed feature, advantage or mode of operation. The term "coupled" is used herein to refer to the direct or indirect coupling between two objects. For example, if object A physically touches object B, and object B touches object C, then objects A and C can still be considered coupled to one another - even if they do not directly physically touch each other - as through their coupling to object B. The term "electrically coupled" can refer to two objects being directly or indirectly coupled together such that electrical current (e.g., signals, power, ground) can pass between the two objects. The two objects that are electrically coupled can or can not have electrical current passing between them. The term "encapsulate" refers to one object can partially or completely encapsulate another object. The use of the terms "first," "second," "third," and "fourth" (and / or any beyond fourth ordinal number) is arbitrary. Any of the described components can be first, second, third, or fourth. For example, a component referred to as a second component can be a first component, a second component, a third component, or a fourth component. It should also be noted that the word "over" used in the context of one component being over another component in this application can be used to refer to one component being on another component and / or in another component (e.g., on the surface of the component or embedded in the component). Thus, for example, a first component over a second component can refer to (1) the first component being over the second component but not directly contacting the second component, (2) the first component being on the second component (e.g., on the surface of the second component), and / or (3) the first component being in the second component (e.g., embedded in the second component). The term "about value X" or "approximately value X" used in the disclosure refers to within 10% of "value X." For example, a value of about 1 or approximately 1 refers to a value within the range of 0.9-1.1.

[0128] In some embodiments, interconnects are elements or components of a device or package that allow or facilitate electrical connections between two points, elements, and / or components. In some embodiments, interconnects may include traces, vias, pads, pillars, redistributed metal layers, and / or under-bump metallization (UBM) layers. Interconnects may include one or more metal components (e.g., a seed layer + metal layer). In some embodiments, interconnects are conductive materials that can be configured to provide an electrical path for a signal (e.g., a data signal, ground, or power). Interconnects may be part of a circuit. Interconnects may include more than one element or component. Interconnects may be defined by one or more interconnects. Different embodiments may use similar or different processes to form interconnects. In some embodiments, chemical vapor deposition (CVD) processes and / or physical vapor deposition (PVD) processes are used to form interconnects. For example, sputtering, spraying, and / or plating processes may be used to form interconnects.

[0129] Furthermore, it should be noted that the various disclosures contained herein can be described as processes shown as flowcharts, flowcharts, structure diagrams, or block diagrams. Although flowcharts can describe operations as sequential processes, many operations can be performed in parallel or simultaneously. Moreover, the order of operations can be rearranged. A process ends when its operations are completed.

[0130] The various features of the disclosure described herein can be implemented in different systems without departing from this disclosure. It should be noted that the foregoing aspects of this disclosure are merely illustrative and should not be construed as limiting the scope of this disclosure. The description of various aspects of this disclosure is intended to be illustrative and not to limit the scope of the claims. Accordingly, this teaching can be readily applied to other types of devices, and many alternatives, modifications, and variations will be apparent to those skilled in the art.

[0131] Other embodiments will be described below to facilitate understanding of the invention.

[0132] An integrated device includes a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate, where the second gate contact is only directly electrically coupled to the gate. The integrated device also includes a second transistor located over the substrate, where the second transistor includes a gate. The second gate contact is configured to adjust a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor. The first transistor includes a first fin and a second fin. The first gate contact can be located over an area that includes the first fin and the second fin. The second gate contact can be located over the area that includes the first fin and the second fin. The second gate contact can be a dummy gate contact.

[0133] An apparatus includes a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The apparatus includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The apparatus includes a mechanism for adjusting a voltage required to induce a first current in the first transistor, where the mechanism for adjusting is only directly electrically coupled to the gate.

[0134] An integrated device includes a substrate and a first transistor located over the substrate, where the first transistor includes a gate. The integrated device includes a first gate contact coupled to the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The integrated device includes a second gate contact coupled to the gate and a contact interconnect coupled to the second gate contact, where the contact interconnect is only directly electrically coupled to the gate contact.

[0135] A method for fabricating an integrated device. The method provides a substrate. The method forms a first transistor over the substrate, where the first transistor includes a gate. The method forms a first gate contact over the gate of the first transistor, where the first gate contact is configured to be electrically coupled to an interconnect of the integrated device. The method forms a second gate contact over the gate, where the second gate contact is only directly electrically coupled to the gate.

Claims

1. An integrated device, comprising: The substrate includes a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor is located on the substrate, wherein the first transistor includes the first active region and a gate; A second transistor is located on the substrate, wherein the second transistor includes the second active region and the gate; A first gate contact is coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; as well as A second gate contact is coupled to the gate, wherein the second gate contact is entirely located above the field region of the substrate, and wherein the second gate contact is electrically coupled only directly to the gate. The first gate contact is located above the field region of the substrate.

2. The integrated device of claim 1, further comprising a contact interconnect coupled to the first gate contact.

3. The integrated device of claim 1, wherein the second gate contact is configured to adjust a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

4. The integrated device of claim 1, wherein the first transistor comprises a p-channel field-effect transistor (PFET) and the second transistor comprises an n-channel field-effect transistor (NFET).

5. The integrated device of claim 1, wherein the first transistor comprises an n-channel field-effect transistor (NFET) and the second transistor comprises a p-channel field-effect transistor (PFET).

6. The integrated device of claim 1, wherein the first transistor comprises a first fin and a second fin.

7. The integrated device of claim 6, wherein the first gate contact is located over the region including the first fin and the second fin.

8. The integrated device of claim 6, wherein the second transistor includes a third fin and a fourth fin.

9. The integrated device of claim 6, wherein the first transistor comprises a p-channel field-effect transistor (PFET).

10. The integrated device of claim 6, wherein the first transistor comprises an n-channel field-effect transistor (NFET).

11. The integrated device of claim 1, further comprising a third gate contact coupled to the gate, wherein the third gate contact is directly electrically coupled to the gate only, and wherein the second gate contact is a dummy gate contact.

12. The integrated device according to claim 1, The first transistor is a p-channel field-effect transistor (PFET). The second transistor is an n-channel field-effect transistor (NFET), and The first gate contact is located above the first transistor.

13. The integrated device according to claim 1, The first transistor is a p-channel field-effect transistor (PFET). The second transistor is an n-channel field-effect transistor (NFET), and The first gate contact is located above the second transistor.

14. The integrated device according to claim 1, The first transistor includes a field-effect transistor (FET).

15. The integrated device of claim 1, wherein the first transistor comprises a planar transistor or a gate-all-around (GAA) FET.

16. An integrated device, comprising: A substrate, the substrate comprising: a first active region, a second active region, and a field region located between the first active region and the second active region; and a third active region, a fourth active region, and a second field region located between the third active region and the fourth active region; and A first transistor is located on the substrate, wherein the first transistor includes the first active region and a gate; A second transistor is located on the substrate, wherein the second transistor includes the second active region and the gate; A first gate contact is coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; A second gate contact is coupled to the gate, wherein the second gate contact is located above the field region of the substrate, and the second gate contact is electrically coupled only directly to the gate. A third transistor is located on the substrate, wherein the third transistor includes the third active region and the second gate; A fourth transistor is located on the substrate, wherein the fourth transistor includes the fourth active region and the second gate; A third gate contact is coupled to the second gate of the third transistor and the fourth transistor, wherein the third gate contact is configured to be electrically coupled to another interconnect of the integrated device; and A fourth gate contact is coupled to the second gate, wherein the fourth gate contact is only directly electrically coupled to the second gate. The third gate contact and the fourth gate contact are located on the third active region of the substrate or the fourth active region of the substrate.

17. The integrated device of claim 16, wherein the integrated device is incorporated into a device selected from the group consisting of: music players, video players, navigation devices, mobile phones, computers, and wearable devices.

18. An apparatus comprising: The substrate includes a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor is located on the substrate, wherein the first transistor includes the first active region and a gate; A second transistor is located on the substrate, wherein the second transistor includes the second active region and the gate; A first gate contact is coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the device; as well as A mechanism for adjusting the threshold voltage required to induce a first current in the first transistor, wherein the mechanism for adjustment is directly electrically coupled to the gate only. The first gate contact and the mechanism for adjusting the threshold voltage are located above the first active region.

19. The apparatus of claim 18, further comprising a third gate contact coupled to the gate.

20. The apparatus of claim 18, wherein the mechanism for adjusting the threshold voltage is configured to adjust the threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

21. The apparatus of claim 20, wherein the first transistor comprises a p-channel field-effect transistor (PFET) and the second transistor comprises an n-channel field-effect transistor (NFET).

22. The apparatus of claim 20, wherein the first transistor comprises an n-channel field-effect transistor (NFET) and the second transistor comprises a p-channel field-effect transistor (PFET).

23. The apparatus of claim 18, wherein the mechanism for adjusting the threshold voltage includes a dummy gate contact.

24. The apparatus of claim 18, wherein the mechanism for adjusting the threshold voltage comprises a dummy contact interconnect.

25. An integrated device, comprising: The substrate includes a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor is located on the substrate, wherein the first transistor includes the first active region and a gate; A second transistor is located on the substrate, wherein the second transistor includes the second active region and the gate; A first gate contact is coupled to the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; A second gate contact is coupled to the gate; and A contact interconnect is coupled to the second gate contact, wherein the contact interconnect is electrically coupled only directly to the second gate contact. The first gate contact and the second gate contact are located above the first active region of the substrate.

26. The integrated device of claim 25, further comprising a third gate contact coupled to the gate.

27. The integrated device of claim 25, wherein the second gate contact is configured to adjust a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

28. The integrated device of claim 27, wherein the first transistor comprises a p-channel field-effect transistor (PFET) and the second transistor comprises an n-channel field-effect transistor (NFET).

29. The integrated device of claim 27, wherein the first transistor comprises an n-channel field-effect transistor (NFET) and the second transistor comprises a p-channel field-effect transistor (PFET).

30. The integrated device according to claim 25, The substrate further includes a third active region, a fourth active region, and a second field region located between the third active region and the fourth active region; and The integrated device also includes: A third transistor is located on the substrate, wherein the third transistor includes the third active region and the second gate; A fourth transistor is located on the substrate, wherein the fourth transistor includes the fourth active region and the second gate; A third gate contact is coupled to the second gate of the third transistor and the fourth transistor, wherein the third gate contact is configured to be electrically coupled to another interconnect of the integrated device; as well as A fourth gate contact is coupled to the second gate, wherein the fourth gate contact is only directly electrically coupled to the second gate. The third gate contact and the fourth gate contact are located on the third active region of the substrate or the fourth active region of the substrate.

31. A method for fabricating an integrated device, comprising: A substrate is provided, the substrate including a first active region, a second active region, and a field region located between the first active region and the second active region; A first transistor is formed on the substrate, wherein the first transistor includes the first active region and a gate; A second transistor is formed on the substrate, wherein the second transistor includes the second active region and the gate; A first gate contact is formed over the gates of the first transistor and the second transistor, wherein the first gate contact is configured to be electrically coupled to an interconnect of the integrated device; as well as A second gate contact is formed on the gate, wherein the second gate contact is directly electrically coupled to the gate only. The first gate contact and the second gate contact are located above the first active region of the substrate.

32. The method of claim 31, further comprising forming a third gate contact on the gate such that the third gate contact is electrically coupled only directly to the gate.

33. The method of claim 31, wherein the second gate contact is configured to adjust a threshold voltage required to induce a first current in the first transistor and a second current in the second transistor.

34. The method of claim 33, wherein the first transistor comprises a p-channel field-effect transistor (PFET) and the second transistor comprises an n-channel field-effect transistor (NFET).

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