Parasitic resistance visualization method, device, system, electronic device and storage medium

Abstract

The application relates to a parasitic resistance visualization method, device, system, electronic device and storage medium, wherein the parasitic resistance visualization method comprises the following steps: acquiring a preset parasitic parameter netlist, and acquiring a netlist node and a parasitic resistance in the parasitic parameter netlist; displaying the netlist node and the parasitic resistance; acquiring node selection information of the netlist node, acquiring a first resistance matched with the node selection information from the parasitic resistance, and displaying at least the first resistance according to preset key identification information; and acquiring at least an end-to-end equivalent resistance value of the first resistance according to the first resistance and displaying the end-to-end equivalent resistance value. Through the application, the problem that the parasitic resistance visualization method has a single function and low visualization efficiency is solved, and efficient visualization of the parasitic resistance is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to a method, device, system, electronic device and storage medium for visualizing parasitic resistance. BACKGROUND

[0002] Parasitic parameters include parasitic capacitance and parasitic resistance, etc. Visualizing parasitic resistance is an important tool for users to locate problems in layout design in the process of integrated circuit design. In order to locate problems in layout design, the current method is to back-label parasitic resistance to a schematic diagram for users to query, so that users can determine problems in layout design by observing the situation of parasitic resistance values in integrated circuits.

[0003] However, as the design scale of integrated circuits increases, there are more and more parasitic resistances in the layout. The existing technology only visualizes parasitic resistance by directly back-labeling it to the layout, lacks the function of auxiliary analysis of parasitic resistance, and in the case of huge data volume and complex connection, the visual interface will become cluttered and the loading efficiency will be affected by the loading data volume, making the efficiency of users using the visual interface become low and it is difficult to quickly locate the layout design parameters.

[0004] At present, there is no effective solution to the problem of single function and low visualization efficiency of the related art parasitic resistance visualization method. SUMMARY

[0005] The present application provides a method, device, system, electronic device and storage medium for visualizing parasitic resistance to solve the problem of single function and low visualization efficiency of the related art parasitic resistance visualization method.

[0006] In a first aspect, the present application provides a method for visualizing parasitic resistance, applied to a terminal device, comprising:

[0007] Obtaining a preset parasitic parameter netlist, and obtaining a netlist node and a parasitic resistance in the parasitic parameter netlist, and displaying the netlist node and the parasitic resistance;

[0008] Obtaining node selection information for the netlist node, obtaining a first resistance matched with the node selection information from the parasitic resistance, and displaying at least the first resistance according to preset key identification information;

[0009] According to the first resistance, at least the end-to-end equivalent resistance value of the first resistance is obtained and displayed.

[0010] Further, the obtaining of the node selection information for the netlist node comprises:

[0011] obtaining a user inputted graphical selection instruction for the netlist node, and generating the node selection information according to the graphical selection instruction;

[0012] Alternatively, obtaining a user inputted netlist node name, and obtaining the node selection information according to the netlist node name.

[0013] Further, the obtaining, from the parasitic resistance, a first resistance matching the node selection information, and displaying at least the first resistance according to preset highlight identification information, comprises:

[0014] obtaining a start node to be displayed and an end node to be displayed according to the node selection information;

[0015] obtaining the first resistance from the parasitic resistance according to the start node to be displayed and the end node to be displayed;

[0016] displaying at least the first resistance according to preset highlight identification information.

[0017] Further, the obtaining, from the first resistance, at least an end-to-end equivalent resistance value of the first resistance and displaying, comprises:

[0018] obtaining an end-to-end equivalent resistance value of the first resistance according to the first resistance;

[0019] obtaining layer information of the first resistance according to a layout file and the parasitic parameter netlist;

[0020] obtaining a first equivalent resistance value of the first resistance according to the layer information, and a first resistance contribution percentage of the first resistance corresponding to the first equivalent resistance value;

[0021] displaying, in a window, the end-to-end equivalent resistance value of the first resistance, the layer information, the first equivalent resistance value and the first resistance contribution percentage.

[0022] Further, after the obtaining, from the first resistance, at least an end-to-end equivalent resistance value of the first resistance and displaying:

[0023] obtaining resistance selection information, and highlighting a second resistance according to the resistance selection information;

[0024] obtaining, from the second resistance, at least a second equivalent resistance value of the second resistance and displaying.

[0025] Further, the obtaining, from the second resistance, at least a second equivalent resistance value of the second resistance and displaying, comprises:

[0026] obtaining, from the second resistance, a second equivalent resistance value of the second resistance and displaying;

[0027] acquire a second resistance contribution percentage of the second resistance corresponding to the second equivalent resistance value of the second resistance;

[0028] display the second equivalent resistance value and the second resistance contribution percentage of the second resistance in a window.

[0029] In a second aspect, a device for visualizing parasitic resistance is provided in the embodiments, which includes an acquisition module, a selection module and a display module.

[0030] The acquisition module is configured to acquire a preset parasitic parameter netlist, and acquire a netlist node and a parasitic resistance in the parasitic parameter netlist, and display the netlist node and the parasitic resistance.

[0031] The selection module is configured to acquire node selection information for the netlist node, acquire a first resistance from the parasitic resistance that matches the node selection information, and display at least the first resistance according to preset highlight identification information.

[0032] The display module is configured to acquire at least an end-to-end equivalent resistance value of the first resistance according to the first resistance and display the end-to-end equivalent resistance value.

[0033] In a third aspect, a system for visualizing parasitic resistance is provided in the embodiments, which includes a terminal device, a transmission device and a server device; wherein the terminal device is connected to the server device through the transmission device.

[0034] The terminal device is configured to implement the method for visualizing parasitic resistance in the first aspect.

[0035] The transmission device is configured to send the end-to-end equivalent resistance value of the first resistance to the terminal device.

[0036] The server device is configured to calculate the end-to-end equivalent resistance value of the first resistance.

[0037] In a fourth aspect, an electronic device is provided in the embodiments, which includes a memory, a processor and a computer program stored in the memory and executable on the processor, and the processor implements the method for visualizing parasitic resistance in the first aspect when executing the computer program.

[0038] In a fifth aspect, a storage medium is provided in the embodiments, which stores a computer program executable by a processor to implement the method for visualizing parasitic resistance in the first aspect.

[0039] Compared with the related art, the parasitic resistance visualization method, device, system, electronic device and storage medium provided in the embodiment, the method is applied to a terminal device, a preset parasitic parameter netlist is acquired, a netlist node and a parasitic resistance in the parasitic parameter netlist are acquired, and the netlist node and the parasitic resistance are displayed; node selection information for the netlist node is acquired, a first resistance matched with the node selection information is acquired from the parasitic resistance, and at least the first resistance is displayed according to preset key identification information; and an end-to-end equivalent resistance value of the first resistance is acquired and displayed according to the first resistance, thereby solving the problems of single function and low visualization efficiency of the parasitic resistance visualization method, and having the following beneficial effects:

[0040] 1. The resistance is inversely labeled back to the layout, a visual graphical interface is provided, and a designer is assisted in designing a circuit;

[0041] 2. A resistance layer analysis tool is provided, a designer is facilitated to quickly understand resistances between nodes in a circuit, and layer resistance contributions are calculated, a designer is facilitated to understand circuit characteristics, and problems in layout design are quickly located;

[0042] 3. A resistance local inspection tool is provided, and a designer is facilitated to study circuit details.

[0043] Details of one or more embodiments of the present application are presented in the following drawings and description to make other features, objects and advantages of the present application more apparent. BRIEF DESCRIPTION OF DRAWINGS

[0044] The drawings described herein are used to provide further understanding of the present application, constitute a part of the present application, and the illustrative embodiments of the present application and the description thereof are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0045] Figure 1 It is an application scenario diagram of the parasitic resistance visualization method in one embodiment;

[0046] Figure 2 It is a flowchart of the parasitic resistance visualization method in one embodiment;

[0047] Figure 3 It is a schematic diagram of a part of a layer number name interface in one embodiment;

[0048] Figure 4 It is a schematic diagram of a part of node information interface in one embodiment;

[0049] Figure 5 It is a schematic diagram of a part of resistance information interface in one embodiment;

[0050] Figure 6 It is a schematic diagram of a display window in one embodiment;

[0051] Figure 7 Flowchart for the method of visualizing parasitic resistance in another embodiment;

[0052] Figure 8 Block diagram of the device for visualizing parasitic resistance in an embodiment;

[0053] Figure 9 Internal structure diagram of the computer device in an embodiment. DETAILED DESCRIPTION

[0054] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and explained below in conjunction with the drawings and embodiments.

[0055] The method of visualizing parasitic resistance provided by the present application can be applied in an application environment as shown in the figure. Figure 1 The terminal device 102 communicates with the server device 104 through a network. The terminal device 102 acquires a preset parasitic parameter netlist, acquires a netlist node and a parasitic resistance in the parasitic parameter netlist, and displays the netlist node and the parasitic resistance. The terminal device 102 acquires node selection information for the netlist node, acquires a first resistance from the parasitic resistance that matches the node selection information, and displays at least the first resistance according to preset key identification information. The terminal device 102 acquires at least an end-to-end equivalent resistance value of the first resistance according to the first resistance and displays it. The server device 104 is used to calculate the end-to-end equivalent resistance value of the first resistance. The terminal device 102 can be, but is not limited to, various personal computers, notebook computers, smart phones, tablet computers and portable wearable devices, and the server device 104 can be implemented by an independent server or a server cluster composed of multiple servers.

[0056] In the present embodiment, a method of visualizing parasitic resistance is provided, Figure 2 The flowchart of the method of visualizing parasitic resistance in the present embodiment is shown in the figure. Figure 2 The flowchart includes the following steps:

[0057] In step S202, a preset parasitic parameter netlist is acquired, a netlist node and a parasitic resistance in the parasitic parameter netlist are acquired, and the netlist node and the parasitic resistance are displayed.

[0058] The parasitic parameter netlist describes the parasitic parameters of the connection of devices in a circuit, the content of the parasitic parameter netlist includes a gate-level netlist (or a register-level netlist) and parasitic parameters; the gate-level netlist describes the connection relationship of components; the netlist node refers to a point with a coordinate position in the parasitic parameter netlist; the parasitic parameters refer to parasitic resistance, parasitic capacitance and parasitic inductance and other parameters generated due to the interconnection of components on the layout.

[0059] Specifically, the terminal device 102 acquires a parasitic parameter netlist, acquires position coordinates of a netlist node from a gate-level netlist in the parasitic parameter netlist, acquires a parasitic resistance from a parasitic parameter in the parasitic parameter netlist, marks the netlist node and the position coordinates in a layout according to the position coordinates, and connects the netlist node based on a connection relationship of the netlist node; the terminal device 102 displays the acquired netlist node and parasitic resistance, and inversely labels a resistance value of the parasitic resistance to the layout for visual display.

[0060] In step S204, node selection information for the netlist node is acquired, a first resistance matching the node selection information is acquired from the parasitic resistance, and at least the first resistance is displayed according to preset highlight identification information.

[0061] The node selection information is used to acquire a first resistance required by a user from all parasitic resistances; the first resistance refers to a resistance corresponding to the node selection information matched from all parasitic resistances according to the node selection information, and there is at least one first resistance; the highlight identification information refers to information preset to highlight the first resistance to be displayed, for example, the highlight identification information can be a highlight identification, and the terminal device can highlight the first resistance based on the highlight identification after the first resistance is acquired; or, in a case where it is detected that the highlight identification information is text annotation information, the first resistance can be highlighted in the form of annotation based on the text annotation information; or, the highlight identification information can also be preset as a red identification, and the like, which will not be described herein again.

[0062] Specifically, the terminal device 102 acquires node selection information for the netlist node, acquires at least one first node and at least one first resistance within a range of the node selection information in the parasitic parameter netlist on the layout according to the node selection information, and at least highlights the first resistance.

[0063] In step S206, an end-to-end equivalent resistance value of the first resistance is acquired and displayed at least according to the first resistance.

[0064] The end-to-end equivalent resistance value of the first resistance can be calculated by the server device 104 according to the first resistance, or can be displayed by the terminal device 102 after the first resistance is obtained and is calculated synchronously. Preferably, in order to improve the efficiency of the parasitic resistance visualization, the terminal device 102 displays the end-to-end equivalent resistance value of the first resistance calculated by the server device 104. The end-to-end equivalent resistance value refers to the equivalent resistance value from one node to another node, or the equivalent resistance value from a port of one device to a port of another device (or different ports of the same device). Preferably, the end-to-end equivalent resistance value of the first resistance can be the total equivalent resistance value of the first resistance, or can be a hierarchical equivalent resistance value calculated according to the hierarchy in the layout file.

[0065] It should be noted that after the first resistance and the end-to-end equivalent resistance value of the first resistance are displayed, and the cancel display command of the first resistance input by the user is obtained, the first resistance and the end-to-end equivalent resistance value of the first resistance can be stored in a text document or a database carrier, or can not be stored, and the display process of the first resistance and the end-to-end equivalent resistance value of the first resistance is released. Preferably, in order to improve the efficiency of the parasitic resistance visualization, the terminal device 102 directly releases the display process of the first resistance and the end-to-end equivalent resistance value of the first resistance after the cancel display command input by the user is obtained.

[0066] Through the above steps, the node selection information for the netlist node is obtained, and the first resistance and the end-to-end equivalent resistance value of the first resistance are displayed according to the node selection information. Compared with the technical solution in the related art in which the parasitic resistance is back annotated to the layout, the parasitic resistance visualization method in the embodiment can not only back annotate the parasitic resistance to the layout, but also highlight the first node and the first resistance in the selection range according to the selection result of the user for the netlist node, and display the end-to-end equivalent resistance value of the first resistance. The problem of single function and low positioning efficiency of the parasitic resistance visualization method in the related art is solved, and it is convenient for the designer to quickly understand the resistance between nodes in the circuit and quickly locate the problem in the layout design.

[0067] In some embodiments, obtaining the node selection information for the netlist node includes:

[0068] The graphical selection instruction input by the user for the netlist node is obtained, and the node selection information is generated according to the graphical selection instruction.

[0069] Alternatively, the name of the netlist node input by the user is obtained, and the node selection information is obtained according to the name of the netlist node.

[0070] The node selection information of the netlist node obtained is graphical selection information and / or parameterized selection information. The graphical selection information is a graphical selection instruction obtained by a user operating a netlist node on a visual interface. Specifically, the node selection information selected by the user on the layout file and the parasitic parameter netlist is obtained. The user operation can be a selection operation on two netlist nodes, a range selection operation on the layout file by dragging a check box, or a check operation on a netlist tree diagram. The netlist tree diagram is a tree structure composed of nets and nodes in the netlist according to a layout hierarchy, mainly in the form of a drop-down table. When a net in a first-level drop-down table is selected, all node nodes on the net are popped up for the user to select. The parameterized selection information is a netlist node number or a netlist node name input by the user. The node selection information is determined according to one of the graphical selection information and / or the parameterized selection information with a larger range.

[0071] Through the above steps, the end-to-end equivalent resistance of the first resistor can be calculated by obtaining the node selection information. Compared with the technical solution of reflecting the parasitic resistance to the layout in the related art, the parasitic resistance visualization method in the embodiment can not only reflect the parasitic resistance to the layout, but also obtain the node selection information of the netlist node, provide the user with hierarchical selection through graphical selection, facilitate the user to quickly find the node of interest, and highlight the first node and the first resistor in the selection range according to the node selection information, and display the end-to-end equivalent resistance of the first resistor, thereby solving the problems of single function and low positioning efficiency of the parasitic resistance visualization method in the related art, and facilitating the designer to quickly understand the resistance between nodes in the circuit and quickly locate the problem in the layout design.

[0072] In some embodiments, a first resistor matching the node selection information is obtained from the parasitic resistance, and the first resistor is displayed at least according to the preset key identification information, including:

[0073] The starting node to be displayed and the end node to be displayed are obtained according to the node selection information.

[0074] The first resistor is obtained from the parasitic resistance according to the starting node to be displayed and the end node to be displayed.

[0075] The first resistor is highlighted at least according to the preset key identification information.

[0076] The starting node to be displayed and the end node to be displayed include respective coordinate information.

[0077] Specifically, the terminal device 102 obtains coordinate information of a start node to be displayed and coordinate information of an end node to be displayed on a maximum range from the node selection information; the terminal device 102 obtains at least one first node and at least one first resistor connected between the start coordinate and the end coordinate from the parasitic parameter netlist corresponding to the parasitic resistor according to the coordinate information of the start node to be displayed and the coordinate information of the end node to be displayed; and the terminal device 102 displays the start node to be displayed, the end node to be displayed, the at least one first node, and the at least one first resistor according to the preset key identification information.

[0078] Through the above steps, by obtaining the node selection information selected by the user, all nodes and all resistors corresponding to the node selection information are highlighted. Compared with the technical solution of only back labeling the parasitic resistor to the layout in the related art, the parasitic resistor visualization method in the embodiment can not only back label the parasitic resistor to the layout, but also obtain the node selection information of the user on the netlist node, facilitate the user to quickly find the interested node, and highlight the first node and the first resistor in the selection range according to the node selection information, and display the end-to-end equivalent resistance value of the first resistor, thereby solving the problems of single function and low positioning efficiency of the parasitic resistor visualization method in the related art, and facilitating the designer to quickly understand the resistance between nodes in the circuit and quickly locate the problem in the layout design.

[0079] In some embodiments, according to the first resistor, at least the end-to-end equivalent resistance value of the first resistor is obtained and displayed, including:

[0080] According to the first resistor, the end-to-end equivalent resistance value of the first resistor is obtained;

[0081] Obtaining a layout file, and obtaining layer information of the first resistor according to the layout file and the parasitic parameter netlist;

[0082] According to the layer information, a first equivalent resistance value of the first resistor and a first resistance contribution percentage of the first resistor corresponding to the first equivalent resistance value are obtained;

[0083] The end-to-end equivalent resistance value of the first resistor, the layer information, the first equivalent resistance value, and the first resistance contribution percentage are displayed in a window.

[0084] The end-to-end equivalent resistance of the first resistance can be calculated by the server device 104 according to the first resistance, or can be displayed by the terminal device 102 after obtaining the first resistance and synchronous calculation. Preferably, in order to improve the efficiency of parasitic resistance visualization, the terminal device 102 displays the end-to-end equivalent resistance of the first resistance calculated by the server device 104; the end-to-end equivalent resistance refers to the equivalent resistance between one node and another node, or the equivalent resistance between a port of one device and a port of another device (or different ports of the same device); the layer information includes the layout hierarchy (layer) name, and the names, numbers and values of the components contained in each layer; the first equivalent resistance and the first resistance contribution percentage are calculated according to the layer information and the first resistance, and are preferably calculated by the server device 104, and the terminal device 102 obtains the first equivalent resistance sent by the server device 104, and at least one of the first equivalent resistance and the first resistance contribution percentage corresponds to each layer in the layer information; the first equivalent resistance refers to the equivalent resistance of the first resistance between the two nodes, and the resistance on the corresponding layer to the entire circuit, that is, if two nodes pass through three different layers, the circuits on the three different layers are equivalent to one first resistance respectively, and the first equivalent resistance has three, corresponding to different layers; the three first resistances are connected in series, which is equal to the end-to-end circuit equivalent resistance corresponding to the first resistance; the first resistance contribution percentage is the percentage of the first equivalent resistance of the first resistance to the entire circuit; the display of the end-to-end equivalent resistance of the first resistance, the layer information, the first equivalent resistance and the first resistance contribution percentage in the window can be a floating window or a pull-down window, and the display window can be located on the right side or the lower side of the display interface of the terminal device 102.

[0085] In this embodiment, the layout design with the name EP is taken as an example, Figure 3 is a part of the layer number name interface diagram in this embodiment, as shown in Figure 3 , the layout design has a total of 85 layout hierarchies (layers), and only part of the layers are shown in the figure. Figure 4 is a part of the node information interface diagram in this embodiment, as shown in Figure 4 , the layout design has a total of 159 netlist nodes, and only part of the nodes are shown in the figure. The first column field includes *|P, *|I and *|S, *|P represents a chip external port, *|I represents a device port, and *|S represents a sub-node; the first field in the brackets is the node name, such as EP:0 and XI169 / MNM0@3:G; the last two fields in the brackets are the x and y coordinates of the node; the number after the field $lvl= is the number of the corresponding layer. Figure 5is a part of the resistance information interface diagram in the embodiment, as shown in Figure 5 , there are 170 resistances in the layout design, and only part of the resistances are shown in the figure. Each row of resistance information corresponds to a resistance. The first column is the resistance name (the resistance name has no specific meaning and is only numbered for distinction). The second column and the third column are the node names of the two nodes connected by the resistance. The number after the field lvl= indicates the level of the resistance.

[0086] Figure 6 is a display window diagram in the embodiment, as shown in Figure 6 , the node selection information in the layout design is node No. 75 and node No. 45. Node No. 75 is on the M2:drawing layer and has coordinates (100.021, 134.898). Node No. 45 is on the M3:drawing layer and has coordinates (105.361, 134.646). Figure 6 The selection key in the window diagram shown in Figure 6 can obtain the operation selection result of the corresponding node after being clicked by the user. The calculation key can be triggered by the user after obtaining the node selection information, so as to obtain and display the equivalent resistance value result 60.7112 ohms (ohms) obtained according to the node selection information. Meanwhile, the command for whether to highlight the node selection information can be obtained in the window interface shown in .

[0087] Specifically, in the embodiment, the end-to-end equivalent resistance value of the first resistance is calculated according to the layout hierarchy. Taking two nodes |I in net EP as an example, node 1: XI169 / MNM0@3:G and node 2: XI169 / MNM0:G, the end-to-end equivalent resistance value (p2p value) of the first resistance corresponding to the two nodes is 1847.82Ω (ohms), and the corresponding layers are layers 13, 37, 51, 62, 68 and 73. Table 1 below is an example of visualizing the layer equivalent resistance and resistance contribution in the embodiment. The expression of the resistance contribution is as follows:

[0088]

[0089] The calculation expression of the equivalent contribution resistance value of each layer corresponding to the resistance contribution is as follows:

[0090]

[0091] wherein R p2p is the end-to-end equivalent resistance value of the first resistance, which is calculated by the server device 104 according to the connection relationship between the components in the layout file and the equivalent resistance value calculation formula of series-parallel circuit, which will not be described herein again; R tR is the target resistance value, which refers to the object for calculating the resistance contribution, in this embodiment, it refers to the equivalent resistance of each layer; R' t R is the target resistance offset resistance value, which is a differential unit, specifically refers to the proportion of the target resistance after offset and before offset, the value range is 1%~5%, the specific value of the calculation process is determined according to the actual situation; R' p2p R is the equivalent end-to-end resistance value after offset; -R e R is the equivalent contribution resistance value of the target resistance in the circuit corresponding to the resistance contribution of the resistance.

[0092] Table 1: Visualization example of layer equivalent resistance and resistance contribution

[0093]

[0094]

[0095] In this embodiment, the selected at least one first resistance in the node selection information is distributed in the above 6 layers, and 6 first equivalent resistance values are obtained; the first resistance contribution percentage distributed in the layer 13: metal1 is 0.02%, and the first equivalent resistance value is 0.3Ω; the first resistance contribution percentage distributed in the layer 37: ngate_svt_fin is 86.36%, and the first equivalent resistance value is 1595.1Ω; the first resistance contribution percentage distributed in the layer 51: npoly_svt is 7.73%, and the first equivalent resistance value is 142.9Ω; the first resistance contribution percentage distributed in the layer 62: M0G_GT is 0.50%, and the first equivalent resistance value is 9.2Ω; the first resistance contribution percentage distributed in the layer 68: M0G_GT_npoly_svt_RC is 5.3%, and the first equivalent resistance value is 98.0Ω; the first resistance contribution percentage distributed in the layer 73: V0_M0G_GT is 0.14%, and the first equivalent resistance value is 2.7Ω.

[0096] Through the above steps, the first resistance in the node selection information and the end-to-end equivalent resistance value of the first resistance, the first equivalent resistance value and the first resistance contribution percentage are visually displayed. Compared with the technical solution in the related art that only labels the parasitic resistance to the layout, the parasitic resistance visualization method in this embodiment solves the problem of single function and low positioning efficiency of the parasitic resistance visualization method in the related art, provides a resistance layer analysis tool, facilitates designers to quickly understand the resistance between nodes in the circuit, and calculates the layer resistance contribution, which facilitates designers to understand the circuit characteristics and quickly locate the problems in the layout design.

[0097] In some embodiments thereof, after the first resistance is obtained at least the end-to-end equivalent resistance value of the first resistance and displayed:

[0098] obtaining resistance selection information, and highlighting the second resistance according to the resistance selection information;

[0099] obtaining at least a second equivalent resistance value of the second resistance according to the second resistance, and displaying the second equivalent resistance value.

[0100] wherein the second resistance refers to the resistance after the user further selects at least one first resistance, and the second resistance is at least one; the coordinate range of the resistance selection information is in the node selection information, the resistance selection information only includes at least one second resistance which is further selected from the at least one first resistance, and the further selection can be all selection or partial selection; the resistance selection information can be obtained according to the obtained graphical selection information or parameterized selection information of the user selecting the first resistance in the node selection information, which will not be repeated here.

[0101] Through the above steps, the resistance selection information is obtained based on the node selection information, so as to obtain the second equivalent resistance value and the second resistance contribution percentage. The second resistance and related parameters can be highlighted based on the highlighted first resistance and related parameters, the secondary selection of the parasitic resistance visualization is realized, the problem of low positioning efficiency and single function of the parasitic resistance visualization method in the related technology is solved, and the resistance local inspection tool is provided, which facilitates the designer to study the circuit details and quickly understand the resistance between nodes in the circuit and quickly locate the problems in the layout design.

[0102] In some embodiments, obtaining at least a second equivalent resistance value of the second resistance according to the second resistance, and displaying the second equivalent resistance value, includes:

[0103] obtaining a second equivalent resistance value of the second resistance according to the second resistance, and displaying the second equivalent resistance value;

[0104] obtaining a second resistance contribution percentage of the second resistance corresponding to the second equivalent resistance value;

[0105] displaying the second equivalent resistance value and the second resistance contribution percentage of the second resistance in a window.

[0106] Specifically, the second resistance and the resistance value of the second resistance are obtained according to the resistance selection information, and the second resistance and the resistance value of the second resistance are highlighted; the layer information of the second resistance is obtained according to the layer information of the first resistance; the second equivalent resistance of the second resistance in the end-to-end equivalent resistance and the second resistance contribution percentage of the second resistance corresponding to the second equivalent resistance are obtained according to the second resistance; the second equivalent resistance and the second resistance contribution percentage of the second resistance are displayed in the window; in the display of the second equivalent resistance and the second resistance contribution percentage in the window, the display window can be a floating window or a pull-down window, etc., and the display window can be located at the right side or the bottom of the display interface of the terminal device 102, etc.

[0107] Preferably, the terminal device 102 obtains the resistance selection information on the basis of the operation of the user in the node selection information, and the terminal device 102 highlights the at least one second resistance and / or the resistance value of the second resistance selected by the user, wherein the highlight attribute of the highlighting of the second resistance is different from the highlight attribute of the highlighting of the first resistance, for example, the highlight attribute can be different in color or different in brightness, so as to display the second resistance while displaying the first resistance and distinguish the first resistance and the second resistance; the terminal device 102 obtains the layer information of the second resistance according to the layer information of the first resistance and sends the layer information to the server device 104; the server device 104 obtains the resistance value of the second resistance of the resistance selection information, and calculates the second equivalent resistance corresponding to the resistance value of the second resistance and the layer information of the second resistance, and the second resistance contribution percentage of the second resistance corresponding to the second equivalent resistance, and sends the second equivalent resistance and the second resistance contribution percentage to the terminal device 102; after the terminal device 102 obtains the second equivalent resistance and the second resistance contribution percentage of the second resistance, the terminal device 102 displays the second equivalent resistance and the second resistance contribution percentage of the second resistance in the window; wherein, the calculation formula of the second equivalent resistance and the second resistance contribution percentage is referred to the calculation formula of the first equivalent resistance and the first resistance contribution percentage, which is not described herein. Table 2 below is a visualization example of the layer equivalent resistance and the resistance contribution corresponding to the resistance selection information based on the above node selection information in this embodiment.

[0108] Table 2: Visualization example of layer equivalent resistance and resistance contribution corresponding to resistance selection information

[0109] Resistors (group) Second resistance contribution Second equivalent resistance (ohms) Group 1 (R2215098-R2215117) 20.4％ 378.0 Group 2 (R2215118-R2215127) 20.7％ 382.2 Group 3 (R2215118-R2215147) 53.0％ 978.4

[0110] As shown in Table 2, the resistance selection information includes three groups, group 1 includes resistors numbered R2215098-R2215117, group 2 includes R2215118-R2215127, and group 3 includes R2215118-R2215147; the three groups of resistance selection information are independent of each other; and the resistors in the above groups can or can not be on the same layer. The second equivalent resistance value of group 1 is calculated by the above formula to be 378.0Ω, and the second resistance contribution percentage is 20.4%; the second equivalent resistance value of group 2 is 382.2Ω, and the second resistance contribution percentage is 20.7%; and the second equivalent resistance value of group 3 is 978.4Ω, and the second resistance contribution percentage is 53.0%.

[0111] Through the above steps, the resistance selection information is obtained based on the node selection information, so as to obtain the second equivalent resistance value and the second resistance contribution percentage. The second resistance and related parameters can be highlighted based on the highlighting of the first resistance and related parameters, the secondary selection of the parasitic resistance visualization is realized, the problem of single function and low positioning efficiency of the parasitic resistance visualization method in the related art is solved, and the resistance local inspection tool is provided, which facilitates the designer to study the circuit details and facilitates the designer to quickly understand the resistance between nodes in the circuit and quickly locate the problems in the layout design.

[0112] In this embodiment, a parasitic resistance visualization method is also provided. Figure 7 is a flowchart of another parasitic resistance visualization method of this embodiment, as shown in Figure 7 The flowchart includes the following steps:

[0113] In step S702, a preset parasitic parameter netlist is obtained, and a netlist node and a parasitic resistance in the parasitic parameter netlist are obtained.

[0114] In step S704, the netlist node and the parasitic resistance are displayed.

[0115] In step S706, node selection information for the netlist node is obtained.

[0116] In step S708, a first resistance matched with the node selection information is obtained from the parasitic resistance, and at least the first resistance is displayed according to the preset highlight identification information.

[0117] In step S710, at least an end-to-end equivalent resistance value of the first resistance is obtained and displayed according to the first resistance.

[0118] In step S712, resistance selection information is obtained.

[0119] In step S714, a second resistance is highlighted according to the resistance selection information, and at least a second equivalent resistance value of the second resistance is obtained and displayed according to the second resistance.

[0120] Through the above steps, the node selection information for the netlist node is obtained, and the first resistor and the end-to-end equivalent resistance value of the first resistor are displayed according to the node selection information. Compared with the technical solution in the related art that only reversely labels the parasitic resistance into the layout file, the parasitic resistance visualization method in this embodiment can not only reversely label the parasitic resistance into the layout file, but also highlight the first node and the first resistor in the selection range according to the selection result of the user on the netlist node, and display the end-to-end equivalent resistance value of the first resistor, thereby solving the problems of single function and low positioning efficiency of the parasitic resistance visualization method in the related art, and facilitating the designer to quickly understand the resistance between nodes in the circuit and quickly locate the problems in the layout design.

[0121] It should be understood that, although Figures 2-7 the steps in the flowchart are shown in order according to the arrows, these steps are not necessarily executed in order according to the arrows. Unless otherwise specified herein, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, Figures 2-7 at least part of the steps in the flowchart can include multiple sub-steps or multiple stages, which are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but can be executed in rotation or alternation with at least part of other steps or sub-steps or stages of other steps.

[0122] In this embodiment, a parasitic resistance visualization device is also provided, which is used to implement the above-mentioned embodiments and preferred embodiments, and will not be described again. The terms "module", "unit", "sub-unit" and the like used below can be a combination of software and / or hardware that implements a predetermined function. Although the device described in the following embodiments is preferably implemented in software, hardware, or a combination of software and hardware is also possible and is contemplated.

[0123] Figure 8 is a structural block diagram of the parasitic resistance visualization device of this embodiment, as Figure 8 shown, the device includes an acquisition module 10, a selection module 20, and a display module 30;

[0124] The acquisition module 10 is configured to acquire a preset parasitic parameter netlist, acquire a netlist node and a parasitic resistance in the parasitic parameter netlist, and display the netlist node and the parasitic resistance;

[0125] The selection module 20 is configured to obtain node selection information for the netlist node, obtain a first resistance from the parasitic resistance that matches the node selection information, and display at least the first resistance according to preset highlight identification information.

[0126] The display module 30 is configured to obtain at least an end-to-end equivalent resistance value of the first resistance according to the first resistance and display the end-to-end equivalent resistance value.

[0127] For specific limitations of the parasitic resistance visualization device, refer to the limitations of the parasitic resistance visualization method described above, which will not be repeated here. Each module in the above parasitic resistance visualization device can be realized by software, hardware, and combinations thereof, in whole or in part. The above modules can be embedded in or independent of the processor in the computer device in hardware form, or can be stored in the memory in the computer device in software form, so that the processor invokes and executes the operations corresponding to each of the above modules.

[0128] In this embodiment, a parasitic resistance visualization system is also provided, which includes a terminal device 102, a transmission device, and a server device 104; wherein the terminal device 102 is connected to the server device 104 through the transmission device;

[0129] The terminal device 102 is configured to implement any one of the above-described embodiments of the parasitic resistance visualization method;

[0130] The transmission device is configured to send the end-to-end equivalent resistance value of the first resistance to the terminal device 102;

[0131] The server device 104 is configured to calculate the end-to-end equivalent resistance value of the first resistance.

[0132] In this embodiment, an electronic device is also provided, which includes a memory and a processor, the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any one of the above method embodiments.

[0133] Optionally, the above electronic device can further include a transmission device and an input / output device, wherein the transmission device is connected to the above processor, and the input / output device is connected to the above processor.

[0134] Optionally, in this embodiment, the processor can be configured to perform the following steps through the computer program:

[0135] S1, obtain a preset parasitic parameter netlist, and obtain a netlist node and a parasitic resistance in the parasitic parameter netlist, and display the netlist node and the parasitic resistance.

[0136] S2, obtaining node selection information for the netlist node, obtaining a first resistance from the parasitic resistance that matches the node selection information, and displaying at least the first resistance according to preset highlight identification information.

[0137] S3, obtaining at least an end-to-end equivalent resistance value of the first resistance according to the first resistance and displaying.

[0138] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation manners, which will not be described herein again.

[0139] In addition, in combination with the parasitic resistance visualization method provided in the above embodiments, a storage medium can also be provided in this embodiment to implement. The storage medium has a computer program stored thereon; the computer program is executed by a processor to implement any one of the parasitic resistance visualization methods in the above embodiments.

[0140] In one embodiment, a computer device is provided, which can be a terminal, and an internal structure diagram thereof can be as shown in Figure 9 The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operating system and the computer program in the non-volatile storage medium to run. The network interface of the computer device is configured to communicate with external terminals through network connection. The computer program is executed by the processor to implement a parasitic resistance visualization method. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0141] Those skilled in the art can understand that Figure 9 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device to which the scheme of the present application is applied. The specific computer device can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0142] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a non-volatile computer readable storage medium, and when the computer program is executed, the processes of the above-mentioned embodiments of the methods can be included. Any reference to memory, storage, databases, or other media in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration but not limitation, RAM is available in many forms such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0143] It should be understood that the specific embodiments described herein are merely exemplary and not intended to limit the application. According to the embodiments provided in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.

[0144] The above-described embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of patent protection. It should be pointed out that for those skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are all within the scope of protection of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A method for visualizing parasitic resistances, characterized in that, The method is applied to a terminal device, and includes: Obtaining a preset parasitic parameter netlist, and obtaining a netlist node and a parasitic resistance in the parasitic parameter netlist, and displaying the netlist node and the parasitic resistance; Obtaining node selection information for the netlist node, and obtaining a first resistance from the parasitic resistance that matches the node selection information, and displaying at least the first resistance according to preset key identification information; Wherein, the first resistance from the parasitic resistance that matches the node selection information includes: obtaining a to-be-displayed starting node and a to-be-displayed end node according to the node selection information; obtaining the first resistance from the parasitic resistance according to the to-be-displayed starting node and the to-be-displayed end node; wherein, the to-be-displayed starting node and the to-be-displayed end node include respective coordinate information; According to the first resistance, at least the end-to-end equivalent resistance value of the first resistance is obtained and displayed.

2. The method of visualizing parasitic resistance according to claim 1, wherein, The node selection information for the netlist node includes: Obtaining a graphical selection instruction input by a user for the netlist node, and generating the node selection information according to the graphical selection instruction; Or, obtaining a netlist node name input by a user, and obtaining the node selection information according to the netlist node name.

3. The method of visualizing parasitic resistance of claim 1, wherein, According to the first resistance, at least the end-to-end equivalent resistance value of the first resistance is obtained and displayed, including: According to the first resistance, the end-to-end equivalent resistance value of the first resistance is obtained; Obtaining a layout file, and obtaining layer information of the first resistance according to the layout file and the parasitic parameter netlist; According to the layer information, a first equivalent resistance value of the first resistance and a first resistance contribution percentage of the first resistance corresponding to the first equivalent resistance value are obtained; Wherein, the first equivalent resistance value refers to the equivalent resistance value of the entire circuit on the corresponding layer in the end-to-end equivalent resistance of the first resistance; The end-to-end equivalent resistance value of the first resistance, the layer information, the first equivalent resistance value and the first resistance contribution percentage are displayed in a window.

4. The method of visualizing parasitic resistance of claim 1, wherein, After at least the end-to-end equivalent resistance value of the first resistance is obtained and displayed according to the first resistance: Obtaining resistance selection information, and highlighting a second resistance according to the resistance selection information; According to the second resistance, at least a second equivalent resistance value of the second resistance is obtained and displayed.

5. The method of visualizing parasitic resistance according to claim 4, wherein, According to the second resistance, at least a second equivalent resistance value of the second resistance is obtained and displayed, including: According to the second resistance, a second equivalent resistance value of the second resistance is obtained and displayed; According to the second equivalent resistance value, a second resistance contribution percentage of the second resistance corresponding to the second equivalent resistance value is obtained; The second equivalent resistance value and the second resistance contribution percentage of the second resistance are displayed in a window.

6. A device for visualizing parasitic resistances, characterized in that it comprises: It includes: An obtaining module, a selection module and a display module; The obtaining module is used to obtain a preset parasitic parameter netlist, and obtain a netlist node and a parasitic resistance in the parasitic parameter netlist, and display the netlist node and the parasitic resistance; The obtaining module is used to obtain a preset parasitic parameter netlist, and obtain a netlist node and a parasitic resistance in the parasitic parameter netlist, and display the netlist node and the parasitic resistance; The selection module is configured to acquire node selection information for the netlist node, acquire a first resistance from the parasitic resistance that matches the node selection information, and display at least the first resistance according to preset highlight identification information. The method further includes: acquiring a starting node to be displayed and a terminal node to be displayed according to the node selection information; and acquiring the first resistance from the parasitic resistance according to the starting node to be displayed and the terminal node to be displayed, wherein the starting node to be displayed and the terminal node to be displayed each include coordinate information. The display module is configured to acquire at least an end-to-end equivalent resistance value of the first resistance and display the end-to-end equivalent resistance value.

7. A system for visualizing parasitic resistances, characterized in that The method further includes: A terminal device, a transmission device, and a server device, wherein the terminal device is connected to the server device through the transmission device; The terminal device is configured to execute the method for visualizing the parasitic resistance according to any one of claims 1 to 5. The transmission device is configured to send an end-to-end equivalent resistance value of the first resistance to the terminal device. The server device is configured to calculate the end-to-end equivalent resistance value of the first resistance. 8.An electronic device comprising a memory and a processor, the electronic device comprising: The memory stores a computer program, and the processor is configured to execute the computer program to execute the method for visualizing the parasitic resistance according to any one of claims 1 to 5.

9. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the steps of the method for visualizing the parasitic resistance according to any one of claims 1 to 5.

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