Contact hole forming process of IGBT wafer

Abstract

The application discloses an IGBT wafer contact hole forming process and belongs to the semiconductor field. The method comprises the following steps: depositing a silicon nitride layer on the front surface of an IGBT wafer with a deep trench gate through LPCVD, and then dry etching the silicon nitride layer to form a first silicon nitride gasket of the deep trench gate sidewall; depositing an ILD layer on the front surface of the wafer; dry etching the ILD layer to form an opening and a contact hole; depositing a silicon nitride layer on the surface of the ILD layer and the contact hole again, and then dry etching the silicon nitride layer to form a second silicon nitride gasket on the sidewall of the contact hole, and the sidewall of the second silicon nitride gasket is in a form of a gradually-narrowing ramp from top to bottom; and forming an Emittor structure of the IGBT through sputtering thick film Al.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a contact hole forming process of IGBT wafer. BACKGROUND

[0002] Insulated Gate Bipolar Transistor (IGBT) has the advantages of high input impedance of MOSFET device and high-speed switching characteristics of power transistor (GTR), and is widely used in AC motor, frequency converter, switching power supply, lighting circuit, traction drive and other fields.

[0003] The trench gate IGBT chip technology effectively eliminates the JFET effect in the planar gate channel by converting the channel from horizontal to vertical, so that the channel density is no longer limited by the surface area of the chip, thereby increasing the cell density and greatly improving the chip current density. Therefore, the planar gate technology is gradually replaced by the trench gate technology in the medium and low voltage application field. In order to further improve the power density of the trench gate IGBT chip, IGBT chip manufacturers have introduced fine trench design, which reduces the slot width and slot pitch through advanced photolithography technology and process, thereby increasing the MOS channel density and improving the chip current density. However, as the fine degree of the trench gate IGBT chip becomes higher and higher, the size of the metal contact hole becomes smaller and smaller, thereby making the formation process of the metal contact window and the metal filling process more and more difficult.

[0004] At present, when etching the contact window, the contact hole too close to the trench gate edge will cause the problem of electric leakage, and too far away from the trench gate edge will result in low wafer surface area utilization. At the same time, when the contact hole is less than 0.2um, the Al thick film filling is easy to form a cavity inside the contact hole (as shown in Figure 3 SUMMARY

[0005] In view of the deficiencies of the prior art, the present application provides a contact hole forming process of IGBT wafer.

[0006] The object of the present application can be achieved by the following technical solutions:

[0007] A contact hole forming process of IGBT wafer, comprising:

[0008] A silicon nitride layer is deposited on the front surface of the IGBT wafer with deep trench gate by LPCVD, and then the silicon nitride layer is dry etched to form a first silicon nitride gasket of the deep trench gate side wall;

[0009] An ILD layer is deposited on the front surface of the wafer; ​

[0010] Dry etching of the ILD layer creates openings to form contact holes;

[0011] A silicon nitride layer is deposited again on the ILD layer and the surface of the contact hole, and then the silicon nitride layer is dry etched to form a second silicon nitride pad on the sidewall of the contact hole, and the sidewall of the second silicon nitride pad is a gentle slope that gradually narrows from top to bottom.

[0012] The Emitter structure of IGBT is formed by sputtering a thick film of Al.

[0013] The beneficial effects of this invention are:

[0014] 1. This invention utilizes silicon nitride sidewall gaskets to form perfect insulation protection at the edge of the deep trench gate structure. During contact hole etching, it can automatically align, meaning that the distance between the contact hole and the deep trench gate can be minimized, and when etching the gently sloping contact hole, it will not get too close to the edge of the deep trench gate, causing leakage problems. Due to the protection of silicon nitride sidewall gaskets and ILD layer, even under high current / voltage circuit operating conditions, the insulation layer will not collapse.

[0015] 2. After forming the protective structure of the gently sloping contact holes and deep trench gate sidewalls, the present invention allows for thick film Al filling. Due to the high temperature effect (>400℃), the contact hole cavities are naturally filled, forming a perfect Al-filled emitter structure. Without sufficient ILD and sidewall silicon nitride protection, this structure is prone to leakage or collapse of the sidewall insulation layer. The key to forming the gently sloping contact holes lies in the combination of the silicon nitride sidewalls and the ILD (undoped + doped). Due to the difference in the etch rate selection ratio and side etching characteristics, the upper opening of the contact hole is wider, while the bottom opening of the ILD is slightly narrower, and the silicon nitride sidewalls have almost no etching loss, thus forming a perfect gentle slope shape from top to bottom.

[0016] 3. The present invention forms a second silicon nitride pad, which serves as a second silicon nitride sidewall and can effectively prevent short circuits and leakage at the gate of the trench.

[0017] 4. The second silicon nitride sidewall formed at the contact hole allows the contact hole to have a gentle rather than steep slope, which in turn allows aluminum atoms at high temperature to flow along the sidewall of the contact hole to the bottom when the aluminum film is formed, ensuring that the contact hole can be fully filled.

[0018] 5. The process of the present invention can form a double-layer silicon nitride sidewall, which effectively blocks two adjacent contact holes and can ensure that a short circuit will not occur between two larger contact holes. Attached Figure Description

[0019] The invention will now be further described with reference to the accompanying drawings.

[0020] Figures 1-2 This is a flowchart of the application;

[0021] Figure 3 This is a schematic diagram of a contact hole without a protective sidewall in the prior art. Detailed Implementation

[0022] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0023] A contact hole formation process for an IGBT wafer, characterized by comprising:

[0024] A silicon nitride layer 7 is deposited on the front side of the IGBT wafer 1 with the deep trench 2 gate by LPCVD, and then the silicon nitride layer is dry etched to form the first silicon nitride pad 3 of the deep trench gate sidewall.

[0025] An ILD layer is deposited on the front side of wafer 1;

[0026] Dry etching of the ILD layer creates openings, forming contact holes;

[0027] A silicon nitride layer is deposited again on the ILD layer and the surface of the contact hole, and then the silicon nitride layer is dry etched to form a second silicon nitride pad 4 on the sidewall of the contact hole, and the sidewall of the second silicon nitride pad 4 is a gentle slope that gradually narrows from top to bottom.

[0028] The Emitter structure of IGBT is formed by sputtering a thick Al5 film.

[0029] The deposition method for the ILD layer is one of LPCVD, APCVD, and PECVD.

[0030] The bottom layer of the ILD layer is an undoped dielectric 8, and the top layer of the ILD layer is a P-doped dielectric 9.

[0031] The sloped sidewall of the second silicon nitride pad 4 has an inclination angle of 75-85°.

[0032] The temperature during the sputtering of the thick Al film is above 400°C.

[0033] In the description of this specification, references to terms such as "an embodiment," "example," "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0034] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A contact hole formation process for an IGBT wafer, characterized in that, Includes the following steps: A silicon nitride layer is deposited on the front side of the IGBT wafer with a deep trench gate by LPCVD, and then the silicon nitride layer is dry etched to form the first silicon nitride pad on the sidewall of the deep trench gate. An ILD layer is deposited on the front side of the wafer; Dry etching of the ILD layer creates openings to form contact holes; A silicon nitride layer is deposited again on the ILD layer and the surface of the contact hole, and then the silicon nitride layer is dry etched to form a second silicon nitride pad on the sidewall of the contact hole, and the sidewall of the second silicon nitride pad is a gentle slope that gradually narrows from top to bottom. The Emitter structure of IGBT is formed by sputtering a thick film of Al.

2. The contact hole formation process for an IGBT wafer according to claim 1, characterized in that, The deposition method for the ILD layer is one of LPCVD, APCVD, and PECVD.

3. The contact hole formation process for an IGBT wafer according to claim 1, characterized in that, The bottom layer of the ILD layer is an undoped dielectric, and the top layer of the ILD layer is a P-doped dielectric.

4. The contact hole formation process for an IGBT wafer according to claim 1, characterized in that, The sloped sidewall of the second silicon nitride pad has an inclination angle of 75-85°.

5. The contact hole formation process for an IGBT wafer according to claim 1, characterized in that, The temperature during the sputtering of the thick Al film is above 400°C.

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