Control method, control device, two-way interleaved pfc circuit and apparatus

Abstract

The present disclosure provides a control method, a control device, a two-path interleaved PFC circuit and a device. The two-path interleaved PFC circuit comprises a first PFC branch and a second PFC branch, the first PFC branch comprises a first switching device for receiving a first PWM wave signal, and the second PFC branch comprises a second switching device for receiving a second PWM wave signal; the control method comprises: obtaining a first current value of a first input current of the first PFC branch and a second current value of a second input current of the second PFC branch; and in the case that the first current value and the second current value do not satisfy a current sharing condition, adjusting a duty cycle of the first PWM wave signal or a duty cycle of the second PWM wave signal, so that the first current value and the second current value satisfy the current sharing condition. The present disclosure realizes current sharing of two branches of the two-path interleaved PFC circuit.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of PFC (Power Factor Correction), and in particular to a control method and a control device for a two-path interleaved PFC circuit, a two-path interleaved PFC circuit and a device. BACKGROUND

[0002] In the related art, the PWM wave generation manner of the two-path interleaved PFC circuit is generated by the up-down edge counting method, the first PWM (Pulse Width Modulation) wave signal PWMA adopts the manner of setting low at the rising edge, and the second PWM wave signal PWMB adopts the manner of setting high at the rising edge, that is, the two branches of the two-path interleaved PFC circuit output the same duty cycle voltage through the complementary comparison value manner. SUMMARY

[0003] One of the technical problems solved by the present disclosure is that the two-path interleaved PFC circuit may appear uneven current phenomenon in the related art.

[0004] According to one aspect of the present disclosure, a control method for a two-path interleaved PFC (Power Factor Correction) circuit is provided, wherein the two-path interleaved PFC circuit includes a first PFC branch and a second PFC branch, the first PFC branch includes a first switching device for receiving a first PWM (Pulse Width Modulation) wave signal, and the second PFC branch includes a second switching device for receiving a second PWM wave signal; the control method includes: obtaining a first current value of a first input current of the first PFC branch and a second current value of a second input current of the second PFC branch; and in the case that the first current value and the second current value do not satisfy a current sharing condition, adjusting a duty cycle of the first PWM wave signal or a duty cycle of the second PWM wave signal, so that the first current value and the second current value satisfy the current sharing condition.

[0005] In some embodiments, the first PWM wave signal changes from a first level to a second level when a counting waveform rises from 0 to a first comparison value and changes from the second level to the first level when the counting waveform drops from a maximum value to the first comparison value in a normal period, wherein the first level is greater than the second level; the second PWM wave signal changes from a third level to a fourth level when the counting waveform rises from 0 to a second comparison value and changes from the fourth level to the third level when the counting waveform drops from a maximum value to the second comparison value in a normal period, wherein the third level is less than the fourth level; and wherein the sum of the first comparison value and the second comparison value is the maximum value of the counting waveform.

[0006] In some embodiments, the duty cycle of the first PWM wave signal is adjusted by adjusting a first comparison value corresponding to the first PWM wave signal; or the duty cycle of the second PWM wave signal is adjusted by adjusting a second comparison value corresponding to the second PWM wave signal.

[0007] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal comprises: in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in a first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in a second period are both not 0, decreasing the duty cycle of the second PWM wave signal in the second period so that the duty cycle of the second PWM wave signal in the second period after the decrease is equal to the duty cycle of the first PWM wave signal in the second period, wherein the second period is a next period of the first period.

[0008] In some embodiments, the duty cycle of the second PWM wave signal in the second period is decreased by increasing a second comparison value corresponding to the second PWM wave signal in the second period.

[0009] In some embodiments, the second comparison value T' after the increase is T' b For example, T' = T + T

[0010]

[0011] wherein T max is a maximum value of the counting waveform, T a is an original first comparison value.

[0012] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal comprises: in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in a first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in a second period are both not 0, increasing the duty cycle of the first PWM wave signal in the second period so that the duty cycle of the first PWM wave signal in the second period after the increase is equal to the duty cycle of the second PWM wave signal in the second period, wherein the second period is a next period of the first period.

[0013] In some embodiments, the duty cycle of the first PWM wave signal in the second period is increased by increasing a first comparison value corresponding to the first PWM wave signal in the second period.

[0014] In some embodiments, the first comparison value T' after the increase is T' a For example, T' = T + T

[0015] T' a = 2T a , and T' a ≤ T max ,

[0016] wherein T max is a maximum value of the counting waveform, and T a is an original first comparison value.

[0017] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal comprises: in a case that the duty cycles of the first PWM wave signal and the second PWM wave signal in a first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in a second period are both not 100%, increasing the duty cycle of the first PWM wave signal in the second period so that the increased duty cycle of the first PWM wave signal in the second period is equal to the duty cycle of the second PWM wave signal in the second period, wherein the second period is a next period of the first period.

[0018] In some embodiments, the duty cycle of the first PWM wave signal in the second period is increased by increasing a first comparison value corresponding to the first PWM wave signal in the second period.

[0019] In some embodiments, the increased first comparison value T" a is

[0020]

[0021] wherein T max is a maximum value of the counting waveform, and T a is an original first comparison value.

[0022] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal comprises: in a case that the duty cycles of the first PWM wave signal and the second PWM wave signal in a first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in a second period are both not 100%, decreasing the duty cycle of the second PWM wave signal in the second period so that the decreased duty cycle of the second PWM wave signal in the second period is equal to the duty cycle of the first PWM wave signal in the second period, wherein the second period is a next period of the first period.

[0023] In some embodiments, the duty cycle of the second PWM wave signal in the second period is decreased by increasing a second comparison value corresponding to the second PWM wave signal in the second period.

[0024] In some embodiments, the second comparison value T" after being increased is b For

[0025] T" b = 2T b , and

[0026] wherein T max is a maximum value of the count waveform, and T b is an original second comparison value.

[0027] In some embodiments, the current sharing condition is that an absolute value of a difference between the first current value and the second current value is less than or equal to a threshold value; the control method further comprises: before adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal, calculating the absolute value of the difference between the first current value and the second current value; in a case where the absolute value of the difference is greater than the threshold value, determining that the first current value and the second current value do not satisfy the current sharing condition; and in a case where the absolute value of the difference is less than or equal to the threshold value, determining that the first current value and the second current value satisfy the current sharing condition.

[0028] According to another aspect of the present disclosure, there is provided a control device for a two-path interleaved PFC circuit, wherein the two-path interleaved PFC circuit comprises a first PFC branch and a second PFC branch, the first PFC branch comprises a first switching device for receiving a first pulse width modulation (PWM) wave signal, and the second PFC branch comprises a second switching device for receiving a second PWM wave signal; the control device comprises: an acquisition unit configured to acquire a first current value of a first input current of the first PFC branch and a second current value of a second input current of the second PFC branch; and an adjustment unit configured to, in a case where the first current value and the second current value do not satisfy a current sharing condition, adjust a duty cycle of the first PWM wave signal or a duty cycle of the second PWM wave signal, so that the first current value and the second current value satisfy the current sharing condition.

[0029] According to another aspect of the present disclosure, there is provided a control device for a two-path interleaved PFC circuit, comprising: a memory; and a processor coupled to the memory, the processor being configured to perform the method as previously described based on instructions stored in the memory.

[0030] According to another aspect of the present disclosure, there is provided a two-path interleaved PFC circuit, comprising: a control device as previously described.

[0031] In some embodiments, the two-path interleaved PFC circuit further comprises: a first PFC branch comprising a first switching device configured to receive a first PWM wave signal; and a second PFC branch comprising a second switching device configured to receive a second PWM wave signal; wherein the control device is configured to output the first PWM wave signal and the second PWM wave signal according to a counting waveform.

[0032] In some embodiments, the two-path interleaved PFC circuit further comprises: a first current sensor configured to acquire a first current value of a first input current of the first PFC branch and transmit the first current value to the control device; and a second current sensor configured to acquire a second current value of a second input current of the second PFC branch and transmit the second current value to the control device.

[0033] In some embodiments, the first PFC branch further comprises: a first inductor, a first resistor and a first diode arranged in series, a first end of the first switching device being connected between the first resistor and the first diode, and a second end of the first switching device being connected to a wire; and the second PFC branch further comprises: a second inductor, a second resistor and a second diode arranged in series, a first end of the second switching device being connected between the second resistor and the second diode, and a second end of the second switching device being connected to the wire.

[0034] In some embodiments, the two-path interleaved PFC circuit further comprises: a rectifier circuit, a first output end of the rectifier circuit being electrically connected to the first inductor and the second inductor, and a second output end of the rectifier circuit being electrically connected to the wire; and a capacitor, a first end of the capacitor being electrically connected to the first diode and the second diode, and a second end of the capacitor being electrically connected to the wire.

[0035] According to another aspect of the present disclosure, there is provided a device comprising the two-path interleaved PFC circuit as described above.

[0036] According to another aspect of the present disclosure, there is provided a computer readable storage medium having stored thereon computer program instructions which, when executed by a processor, implement the method as described above.

[0037] In the above control method, a first current value of the first input current of the first PFC branch and a second current value of the second input current of the second PFC branch are obtained; and if the first current value and the second current value do not meet the current sharing condition, the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal are adjusted so that the first current value and the second current value meet the current sharing condition. This method can solve the problem of uneven current in dual-channel interleaved PFC circuits in related technologies as much as possible, and realizes current sharing between the two branches of the dual-channel interleaved PFC circuit.

[0038] Other features and advantages of this disclosure will become clear from the following detailed description of exemplary embodiments with reference to the accompanying drawings. Attached Figure Description

[0039] The accompanying drawings, which form part of this specification, illustrate embodiments of this disclosure and, together with the specification, serve to explain the principles of this disclosure.

[0040] This disclosure will become clearer with reference to the accompanying drawings and the following detailed description, wherein:

[0041] Figure 1 This is a schematic diagram showing the connection of a dual-channel interleaved PFC circuit in the related art;

[0042] Figure 2 This is a schematic diagram illustrating the principle of generating PWM waves in related technologies;

[0043] Figure 3 This is a waveform diagram showing that the first period of a PWM wave in the related technology has a zero duty cycle;

[0044] Figure 4 This is a waveform diagram showing that the first period of a PWM wave in the related technology is a full duty cycle;

[0045] Figure 5 This is a flowchart illustrating a control method for a dual-channel interleaved PFC circuit according to some embodiments of the present disclosure;

[0046] Figure 6 This is a waveform diagram illustrating the adjustment of the duty cycle of the second PWM wave signal in the second cycle according to some embodiments of the present disclosure;

[0047] Figure 7 This is a waveform diagram illustrating the adjustment of the duty cycle of the first PWM wave signal in the second cycle according to other embodiments of the present disclosure;

[0048] Figure 8 This is a waveform diagram illustrating the adjustment of the duty cycle of the first PWM wave signal in the second cycle according to other embodiments of the present disclosure;

[0049] Figure 9 is a waveform diagram illustrating adjustment of a duty cycle of a second PWM wave signal in a second cycle according to some embodiments of the present disclosure;

[0050] Figure 10 is a flow chart illustrating a control method for a two-channel interleaved PFC circuit according to some embodiments of the present disclosure;

[0051] Figure 11 is a structural block diagram schematically illustrating a control device for a two-channel interleaved PFC circuit according to some embodiments of the present disclosure;

[0052] Figure 12 is a structural block diagram schematically illustrating a control device for a two-channel interleaved PFC circuit according to some embodiments of the present disclosure;

[0053] Figure 13 is a structural block diagram schematically illustrating a control device for a two-channel interleaved PFC circuit according to some embodiments of the present disclosure;

[0054] Figure 14 is a connection diagram illustrating a two-channel interleaved PFC circuit according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0055] Various exemplary embodiments of the present disclosure will now be described in detail herein below with reference to the accompanying drawings. Note that the relative arrangement, numerical expressions, and numerical values of components and steps set forth in these embodiments are not limiting to the scope of the present disclosure unless otherwise specifically stated.

[0056] Meanwhile, it should be understood that the sizes of the various portions shown in the drawings are not drawn to scale for the sake of convenience in description.

[0057] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way limiting to the scope of the disclosure and its applications or uses.

[0058] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail herein, but should be considered as part of the description if appropriate.

[0059] In all examples shown and discussed herein, any specific values should be interpreted as merely illustrative and not as a limitation. Thus, other examples of the exemplary embodiments can have different values.

[0060] Note that like reference numerals and letters indicate like items in the following drawings and thus, once an item is defined in one drawing, it need not be discussed further in subsequent drawings.

[0061] Figure 1 is a connection diagram of a two-path interleaved PFC circuit in the related art.

[0062] As shown in Figure 1 , the two-path interleaved PFC circuit includes a first PFC branch and a second PFC branch.

[0063] The first PFC branch includes a first switching device T1, a first inductor L1, a first resistor R1, and a first diode D1. The first inductor L1, the first resistor R1, and the first diode D1 are connected in series. A first end of the first switching device T1 is connected between the first resistor R1 and the first diode D1, a second end of the first switching device T1 is connected to a wire 110, and a control end of the first switching device T1 is used to receive a first PWM wave signal PWMA.

[0064] The second PFC branch includes a second switching device T2, a second inductor L2, a second resistor R2, and a second diode D2. The second inductor L2, the second resistor R2, and the second diode D2 are connected in series. A first end of the second switching device T2 is connected between the second resistor R2 and the second diode D2, a second end of the second switching device T2 is connected to the wire 110, and a control end of the second switching device T2 is used to receive a second PWM wave signal PWMB.

[0065] As shown in Figure 1 , the two-path interleaved PFC circuit can further include a rectifier circuit 120. A first output end 121 of the rectifier circuit 120 is electrically connected to the first inductor L1 and the second inductor L2, and a second output end 122 of the rectifier circuit 120 is electrically connected to the wire 110. The rectifier is used to receive alternating current AC and output direct current. For example, the rectifier circuit is composed of four diodes.

[0066] As shown in Figure 1 , the two-path interleaved PFC circuit can further include a capacitor C. A first end of the capacitor C is electrically connected to the first diode D1 and the second diode D2, and a second end of the capacitor C is electrically connected to the wire 110.

[0067] As shown in Figure 1 , the two-path interleaved PFC circuit can further include a load 130, which is connected in parallel with the capacitor C.

[0068] Figure 2 is a principle diagram of generating a PWM wave in the related art.

[0069] Control device of two-path interleaved PFC circuit Figure 1(Not shown in the image) The first PWM wave signal PWMA and the second PWM wave signal PWMB can be generated by the rising and falling edge counting method.

[0070] like Figure 2 As shown, the first PWM wave signal PWMA changes from high to low level when the counting waveform rises from 0 to the first comparison value Ta within the normal cycle, and changes from the maximum value T when the counting waveform rises from 0 to the maximum value T. max When the voltage drops to the first comparison value Ta, it changes from low to high. That is, the first PWM wave signal PWMA is set low on the rising edge.

[0071] like Figure 2 As shown, the second PWM wave signal PWMB changes from low to high during the normal cycle when the counting waveform rises from 0 to the second comparison value Tb, and then changes from the maximum value Tb to the highest value Tb. max When the signal drops to the second comparison value Tb, it changes from high to low. That is, the second PWMB wave signal is set high on the rising edge.

[0072] Here, the sum of the first comparison value Ta and the second comparison value Tb is the maximum value T of the counting waveform. max In other words, the two branches of a dual-interleaved PFC circuit output voltages with the same duty cycle by using complementary comparison values.

[0073] Figure 3 This is a waveform diagram showing that the first period of a PWM wave in the related technology has a zero duty cycle. Figure 4 This is a waveform diagram showing the first period of a PWM wave in related technologies as having a full duty cycle. Here, T is used as... max Taking Ta=1250 and Ta=420 and Tb=830 in the second period as examples, the problems in the related technology discovered by the inventors of this disclosure are described.

[0074] The inventors of this disclosure have discovered that the following two special cases exist in the related art:

[0075] The first scenario is: (e.g.) Figure 3 As shown, when the duty cycle of two PWM wave signals is zero in the first cycle and non-zero in the second cycle, for the first PWM wave signal PWMA, no PWM wave will be generated at the rising edge of the second cycle of the counting waveform, and only at the falling edge. For the second PWM wave signal PWMB, PWM waves are generated at both the rising and falling edges of the second cycle of the counting waveform. This results in the duty cycle of the first PWM wave signal PWMA being half that of the second PWM wave signal PWMB.

[0076] The second scenario is: Figure 4As shown, when the duty cycles of the two PWM wave signals are full duty cycle (i.e., 100%) in the first period and non-full duty cycle (i.e., not 100%) in the second period, for the second PWM wave signal PWMB, the rising edge of the second period of the counting waveform will always be at high level, while the first PWM wave signal PWMA is normal in the second period, which results in that the duty cycle of the second PWM wave signal PWMB is greater than that of the first PWM wave signal PWMA.

[0077] Therefore, the two-path interleaved PFC circuit in the related art can have the phenomenon of uneven current of two paths, i.e., the currents of the two branches of the two-path interleaved PFC circuit are not equal. For example, the above two cases will occur many times when the grid is at high voltage greater than 265V or at low voltage less than 165V, resulting in the uneven current of two paths of the two-path interleaved PFC, causing damage to power components. The first period and the second period described above belong to abnormal periods.

[0078] Further, the inventor of the present disclosure finds that the direct causes of the uneven current of two paths of the two-path interleaved PFC circuit can be divided into the following two kinds:

[0079] Firstly, when the grid input voltage is relatively high, the actual bus voltage is higher than the air conditioner set bus voltage threshold, and the duty cycle of the PWM wave signal opened by the air conditioner drive controller board PFC is small, and the zero duty cycle is more. Since the first PWM wave signal PWMA adopts the mode of setting low at the rising edge, when the duty cycle of the first period of the PWM wave is zero duty cycle and the duty cycle of the second period of the PWM wave is non-zero duty cycle, the rising edge of the first PWM wave signal PWMA in this period will always be low until the comparison value Ta of the falling edge of the counting waveform is high, resulting in that the first PWM wave signal PWMA lacks half of the duty cycle compared with the expected value, as shown in Figure 3 Thus, the uneven current occurs.

[0080] Secondly, when the grid input bus voltage is relatively low, the actual bus voltage is much lower than the air conditioner set bus voltage threshold, and the duty cycle of the PWM wave signal opened by the air conditioner drive controller board PFC is large, and the full-on case is more. Since the second PWM wave signal PWMB adopts the mode of setting high at the rising edge, when the duty cycle of the first period of the PWM wave is full duty cycle and the duty cycle of the second period of the PWM wave is non-full duty cycle, the rising edge of the second PWM wave signal PWMB in this period will always be high, as shown in Figure 4 Thus, the uneven current occurs.

[0081] Therefore, the embodiments of the present disclosure provide a control method for a two-path interleaved PFC circuit to solve the problem of uneven current of two paths of the two-path interleaved PFC circuit in the related art as much as possible.

[0082] Figure 5 is a flow chart illustrating a control method for a dual interleaved PFC circuit according to some embodiments of the present disclosure. The dual interleaved PFC circuit includes a first PFC branch and a second PFC branch, the first PFC branch including a first switching device for receiving a first PWM wave signal, and the second PFC branch including a second switching device for receiving a second PWM wave signal. As shown in Figure 5 the control method includes steps S502-S504. The control method can be performed by a control device.

[0083] At step S502, a first current value of a first input current of the first PFC branch and a second current value of a second input current of the second PFC branch are obtained.

[0084] For example, as shown in Figure 1 the first input current is a current flowing through the first PFC branch when the first switching device T1 is turned on, at which time the first inductor L1 is charged; and the second input current is a current flowing through the second PFC branch when the second switching device T2 is turned on, at which time the second inductor L2 is charged.

[0085] For example, the first current value of the first input current can be collected by setting a first current sensor on the first PFC branch and transmitted to the control device, and the second current value of the second input current can be collected by setting a second current sensor on the second PFC branch and transmitted to the control device.

[0086] At step S504, in a case where the first current value and the second current value do not satisfy a current sharing condition, a duty cycle of the first PWM wave signal or a duty cycle of the second PWM wave signal is adjusted so that the first current value and the second current value satisfy the current sharing condition.

[0087] For example, the current sharing condition can be that an absolute value of a difference between the first current value and the second current value is less than or equal to a threshold value. Based on this, in some embodiments, the control method can further include, before step S504, calculating the absolute value of the difference between the first current value and the second current value; in a case where the absolute value of the difference is greater than the threshold value, determining that the first current value and the second current value do not satisfy the current sharing condition; and in a case where the absolute value of the difference is less than or equal to the threshold value, determining that the first current value and the second current value satisfy the current sharing condition.

[0088] It should be noted that the above threshold value can be set according to actual needs or actual situations. For example, the threshold value is 1A (ampere). Of course, the scope of the present disclosure is not limited to the specific value of the threshold value here.

[0089] In some embodiments, the duty cycle of the first PWM wave signal is adjusted by adjusting a first comparison value corresponding to the first PWM wave signal, or the duty cycle of the second PWM wave signal is adjusted by adjusting a second comparison value corresponding to the second PWM wave signal.

[0090] For example, the duty cycle of the first PWM wave signal in the second period can be adjusted by adjusting a first comparison value corresponding to the first PWM wave signal in the second period, or the duty cycle of the second PWM wave signal in the second period can be adjusted by adjusting a second comparison value corresponding to the second PWM wave signal in the second period.

[0091] So far, the control method for a dual-channel interleaved PFC circuit according to some embodiments of the present disclosure is provided. The dual-channel interleaved PFC circuit includes a first PFC branch and a second PFC branch, the first PFC branch includes a first switching device for receiving a first pulse width modulation (PWM) wave signal, and the second PFC branch includes a second switching device for receiving a second PWM wave signal. The control method includes: obtaining a first current value of a first input current of the first PFC branch and a second current value of a second input current of the second PFC branch; and in the case that the first current value and the second current value do not satisfy a current sharing condition, adjusting a duty cycle of the first PWM wave signal or a duty cycle of the second PWM wave signal so that the first current value and the second current value satisfy the current sharing condition. The method can solve the problem of uneven current of the dual-channel interleaved PFC circuit in the related art as much as possible, and realize current sharing of the two branches of the dual-channel interleaved PFC circuit.

[0092] In some embodiments, as shown in FIG. 1, Figure 2 The first PWM wave signal PWMA changes from a first level to a second level when the count waveform rises from 0 to a first comparison value Ta, and changes from the second level to the first level when the count waveform falls from a maximum value T max to the first comparison value Ta in a normal period, where the first level is greater than the second level. For example, the first level is a high level, and the second level is a low level.

[0093] In some embodiments, as shown in FIG. 1, Figure 2 The second PWM wave signal PWMB changes from a third level to a fourth level when the count waveform rises from 0 to a second comparison value Tb, and changes from the fourth level to the third level when the count waveform falls from a maximum value T max to the second comparison value Tb in a normal period, where the third level is less than the fourth level. For example, the third level is a low level, and the fourth level is a high level.

[0094] Here, the sum of the first comparison value Ta and the second comparison value Tb is the maximum value T maxi.e., T max = Ta+Tb.

[0095] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal comprises: in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both non-0, reducing the duty cycle of the second PWM wave signal in the second period so that the reduced duty cycle of the second PWM wave signal in the second period is equal to the duty cycle of the first PWM wave signal in the second period, wherein the second period is the next period of the first period.

[0096] As analyzed before, it is possible that the actual bus voltage is higher than the set bus voltage threshold of the air conditioner, the duty cycle of the PWM wave signal of the PFC started by the driving controller board of the air conditioner is small, and the zero duty cycle is more, thus resulting in that the duty cycle of the first period of the PWM wave is zero duty cycle, and the duty cycle of the second period of the PWM wave is non-zero duty cycle, thus, in this embodiment, by reducing the duty cycle of the second PWM wave signal in the second period so that the reduced duty cycle of the second PWM wave signal in the second period is equal to the duty cycle of the first PWM wave signal in the second period, the current sharing of the two branches of the double-channel interleaved PFC circuit can be realized, and the bus voltage can be reduced, thus realizing the adjustment of the bus voltage.

[0097] For example, the duty cycle of the second PWM wave signal in the second period can be reduced by increasing the second comparison value corresponding to the second period of the second PWM wave signal. By adjusting the second comparison value in the counting waveform, the duty cycle of the second PWM wave signal can be conveniently adjusted.

[0098] For example, in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both non-0, in the process of increasing the second comparison value corresponding to the second period of the second PWM wave signal, the increased second comparison value T' b is

[0099]

[0100] wherein T max is the maximum value of the counting waveform, T a is the original first comparison value.

[0101] Figure 6 is a waveform diagram illustrating the adjustment of the duty cycle of the second PWM wave signal in the second period according to some embodiments of the present disclosure. In this Figure 6 , in the second period, T maxThe original first comparison value Ta is 420, and the original second comparison value Tb (i.e., the second comparison value before the increase) is 830 (reference). Figure 3 Let's take an example to illustrate.

[0102] As mentioned earlier, when the duty cycles of the first PWM wave signal and the second PWM wave signal are both 0 in the first cycle and are not 0 in the second cycle, the first PWM wave signal PWMA is missing half the expected duty cycle, which also results in the duty cycle of the first PWM wave signal PWMA being half the duty cycle of the second PWM wave signal PWMB.

[0103] And in that Figure 6 In the case where the duty cycle of both the first PWM wave signal and the second PWM wave signal is 0 in the first period and the duty cycle of both in the second period is not 0, the second comparison value corresponding to the second PWM wave signal PWMB in the second period is increased, and the increased second comparison value T′ b for

[0104]

[0105] In this way, by increasing the second comparison value corresponding to the second PWM wave signal in the second cycle, the duty cycle of the second PWM wave signal in the second cycle is reduced. This makes the duty cycle of the reduced second PWM wave signal PWMB equal to the duty cycle of the first PWM wave signal PWMA in the second cycle (for example, calculations show that the duty cycles of both signals PWMB and PWMA are 16.8% in the second cycle), thereby achieving current sharing between the two branches of the dual-channel interleaved PFC circuit. Furthermore, this method can also reduce the bus voltage, achieving bus voltage regulation.

[0106] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: when the duty cycles of the first PWM wave signal and the second PWM wave signal are both 0 in the first period and both are not 0 in the second period, increasing the duty cycle of the first PWM wave signal in the second period so that the increased duty cycle of the first PWM wave signal in the second period is equal to the duty cycle of the second PWM wave signal in the second period, wherein the second period is the next period after the first period.

[0107] In this embodiment, by increasing the duty cycle of the first PWM wave signal in the second cycle, so that the duty cycle of the increased first PWM wave signal in the second cycle is equal to the duty cycle of the second PWM wave signal in the second cycle, the current sharing of the two branches of the dual-channel interleaved PFC circuit can also be achieved.

[0108] For example, the duty cycle of the first PWM wave signal in the second cycle can be increased by increasing the first comparison value corresponding to the first PWM wave signal in the second cycle.

[0109] For example, when the duty cycles of both the first PWM wave signal and the second PWM wave signal are 0 in the first period and not 0 in the second period, during the process of increasing the first comparison value corresponding to the first PWM wave signal in the second period, the increased first comparison value T′ a for

[0110] T′ a =2T a , and (2)

[0111] T′ a ≤T max (3)

[0112] Among them, T max T is the maximum value of the counting waveform. a This is the original first comparison value.

[0113] In other words, by increasing the first comparison value corresponding to the first PWM wave signal in the second period, the duty cycle of the increased first PWM wave signal in the second period can be made equal to the duty cycle of the second PWM wave signal in the second period. However, it should be noted that the increased first comparison value T′ a ≤T max That is, after determining the first comparison value T′ after the increase. a ≤T max In this case, the duty cycle of the first PWM wave signal in the second cycle can be increased by increasing the first comparison value corresponding to the first PWM wave signal in the second cycle.

[0114] Figure 7 This is a waveform diagram illustrating the adjustment of the duty cycle of a first PWM wave signal in a second cycle according to other embodiments of the present disclosure. Figure 7 In the second cycle, with T max The value is 1250, and the original first comparison value Ta (i.e., the first comparison value before the increase) is 420 (reference). Figure 3 Let's take the original second comparison value Tb as an example, which is 830.

[0115] As mentioned earlier, when the duty cycles of the first PWM wave signal and the second PWM wave signal are both 0 in the first cycle and are not 0 in the second cycle, the first PWM wave signal PWMA is missing half the expected duty cycle, which also results in the duty cycle of the first PWM wave signal PWMA being half the duty cycle of the second PWM wave signal PWMB.

[0116] And in that Figure 7 In the case where the duty cycle of both the first PWM wave signal and the second PWM wave signal is 0 in the first period and the duty cycle of both in the second period is not 0, the first comparison value corresponding to the first PWM wave signal PWMA in the second period is increased, and the increased first comparison value T′ a for

[0117] T′ a =2T a =2 × 420 = 840, and

[0118] T′ a ≤T max .

[0119] In this way, by increasing the first comparison value corresponding to the first PWM wave signal PWMA in the second cycle, the duty cycle of the first PWM wave signal in the second cycle is increased. This makes the duty cycle of the increased first PWM wave signal PWMA in the second cycle equal to the duty cycle of the second PWM wave signal PWMB in the second cycle (for example, after calculation, the duty cycles of both signals PWMA and PWMB are 33.6% in the second cycle). This enables the two branches of the dual-channel interleaved PFC circuit to achieve the effect of current sharing.

[0120] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: when the duty cycles of the first PWM wave signal and the second PWM wave signal are both 100% in the first period and neither of them has a duty cycle of 100% in the second period, increasing the duty cycle of the first PWM wave signal in the second period so that the increased duty cycle of the first PWM wave signal in the second period is equal to the duty cycle of the second PWM wave signal in the second period, wherein the second period is the period following the first period.

[0121] As analyzed above, when the grid input bus voltage is low, the actual bus voltage is lower than the set bus voltage threshold of the air conditioner. The duty cycle of the PWM wave signal activated by the PFC of the air conditioner drive controller board is large, and it is often fully open. Therefore, in this embodiment, by increasing the duty cycle of the first PWM wave signal in the second cycle, so that the duty cycle of the increased first PWM wave signal in the second cycle is equal to that of the second PWM wave signal in the second cycle, the current sharing of the two branches of the dual-path interleaved PFC circuit can be achieved, and the bus voltage can also be increased to achieve bus voltage regulation.

[0122] For example, the duty cycle of the first PWM wave signal in the second cycle can be increased by increasing the first comparison value corresponding to the first PWM wave signal in the second cycle. The duty cycle of the first PWM wave signal can be easily adjusted by regulating the first comparison value in the counting waveform.

[0123] For example, in the case where the duty cycles of the first PWM wave signal and the second PWM wave signal are both 100% in the first period and are not both 100% in the second period, in the process of increasing the first comparison value corresponding to the first PWM wave signal in the second period, the first comparison value T" after increase a For

[0124]

[0125] wherein T max is the maximum value of the count waveform, T a is the original first comparison value.

[0126] In this embodiment, since the duty cycle of the PWMA signal is less than the duty cycle of the PWMB signal (T max -Ta), and the PFC on-duty cycle is generally larger, more full-duty cycles, therefore, the duty cycle of the PWMA signal is amplified to achieve current sharing.

[0127] Figure 8 is a waveform diagram illustrating adjustment of the duty cycle of the first PWM wave signal in the second period according to another embodiment of the present disclosure. In this Figure 8 , in the second period, T max is 1250, the original first comparison value Ta (i.e., the first comparison value before increase) is 420 (see Figure 4 ), and the original second comparison value Tb is 830.

[0128] As described above, in the case where the duty cycles of the first PWM wave signal and the second PWM wave signal are both 100% in the first period and are not both 100% in the second period, the duty cycle of the second PWM wave signal PWMB is greater than the duty cycle of the first PWM wave signal PWMA.

[0129] And in this Figure 8 , in the case where the duty cycles of the first PWM wave signal and the second PWM wave signal are both 100% in the first period and are not both 100% in the second period, the first comparison value corresponding to the first PWM wave signal in the second period is increased, and the first comparison value T" after increase a For

[0130]

[0131] In this way, by increasing the first comparison value corresponding to the first PWM wave signal in the second period, the duty cycle of the first PWM wave signal in the second period is increased, which makes the duty cycle of the first PWM wave signal PWMA in the second period equal to the duty cycle of the second PWM wave signal PWMB in the second period (for example, through calculation, the duty cycles of the two signals PWMA and PWMB in the second period are both 66.8%), so that the two branches of the double-path interleaved PFC circuit achieve the current sharing effect. In addition, the method can also increase the bus voltage and realize the adjustment of the bus voltage.

[0132] In some embodiments, adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: in the case that the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 100%, reducing the duty cycle of the second PWM wave signal in the second period, so that the duty cycle of the reduced second PWM wave signal in the second period is equal to the duty cycle of the first PWM wave signal in the second period, wherein the second period is the next period of the first period.

[0133] In this embodiment, by reducing the duty cycle of the second PWM wave signal in the second period, the duty cycle of the reduced second PWM wave signal in the second period is equal to the duty cycle of the first PWM wave signal in the second period, which can achieve current sharing of the two branches of the double-path interleaved PFC circuit.

[0134] For example, the duty cycle of the second PWM wave signal in the second period can be reduced by increasing the second comparison value corresponding to the second PWM wave signal in the second period. By adjusting the second comparison value in the count waveform, the duty cycle of the second PWM wave signal can be conveniently adjusted.

[0135] For example, in the case that the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 100%, in the process of increasing the second comparison value corresponding to the second PWM wave signal in the second period, the increased second comparison value T" b For

[0136] T" b = 2T b , and (5)

[0137]

[0138] wherein T max is the maximum value of the count waveform, T b is the original second comparison value.

[0139] That is, by increasing the second comparison value corresponding to the second PWM wave signal in the second period, the duty cycle of the second PWM wave signal in the second period can be reduced to be equal to the duty cycle of the first PWM wave signal in the second period. However, it should be noted that the original second comparison value before the increase That is, in the case where the original second comparison value is determined to be less than the first comparison value, the method of increasing the second comparison value corresponding to the second PWM wave signal in the second period can be used to reduce the duty cycle of the second PWM wave signal in the second period.

[0140] Figure 9 is a waveform diagram illustrating the adjustment of the duty cycle of the second PWM wave signal in the second period according to some embodiments of the present disclosure. In this Figure 9 , in the second period, T max is 1250, the original first comparison value Ta is 800, and the original second comparison value Tb is 450. Here,

[0141] As mentioned above, in the case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 100%, the duty cycle of the second PWM wave signal PWMB is greater than the duty cycle of the first PWM wave signal PWMA.

[0142] In this Figure 9 , in the case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 100%, the second comparison value corresponding to the second PWM wave signal in the second period is increased, and the increased second comparison value T" b is

[0143] T" b = 2T b = 2 x 450 = 900, and

[0144] In this way, by increasing the second comparison value corresponding to the second PWM wave signal in the second period, the duty cycle of the second PWM wave signal in the second period is reduced, so that the duty cycle of the second PWM wave signal PWMB in the second period is equal to the duty cycle of the first PWM wave signal PWMA in the second period (for example, through calculation, the duty cycles of the two signals PWMB and PWMA in the second period are both 64%), so that the two branches of the dual interleaved PFC circuit achieve the current sharing effect.

[0145] The above is combined with Figure 6 to Figure 9The duty cycle of the first PWM wave signal in the second period is adjusted by adjusting the first comparison value corresponding to the first PWM wave signal in the second period, or the duty cycle of the second PWM wave signal in the second period is adjusted by adjusting the second comparison value corresponding to the second PWM wave signal in the second period.

[0146] It should be noted that, in the process of adjusting the first comparison value corresponding to the first PWM wave signal in the second period or adjusting the second comparison value corresponding to the second PWM wave signal in the second period, the sum of the adjusted first comparison value corresponding to the first PWM wave signal in the second period and the original second comparison value corresponding to the second PWM wave signal in the second period may not equal the maximum value of the counting waveform, or the sum of the adjusted second comparison value corresponding to the second PWM wave signal in the second period and the original first comparison value corresponding to the first PWM wave signal in the second period may not equal the maximum value of the counting waveform.

[0147] Figure 10 is a flow chart showing a control method for a dual-path interleaved PFC circuit according to some other embodiments of the present disclosure. As shown in Figure 10 , the method comprises steps S1002 to S1018.

[0148] In step S1002, the frequency converter is powered on.

[0149] In step S1004, a first current value of a first input current of a first PFC branch and a second current value of a second input current of a second PFC branch are obtained.

[0150] In step S1006, the absolute value of the difference between the first current value and the second current value is calculated.

[0151] In step S1008, it is determined whether the absolute value of the difference between the first current value and the second current value is greater than a threshold value. If yes, the process proceeds to step S1010; otherwise, the process proceeds to step S1012. Here, by sampling the input currents of the two branches, it can be determined whether to execute the current sharing judgment program by comparing the sizes of the currents of the two branches, or it can be determined whether the current sharing effect is obvious by comparing the sizes of the currents of the two branches.

[0152] In step S1010, it is determined whether the duty cycle of the PWM wave is 0 or 100%. If yes, the process proceeds to S1014; otherwise, the process proceeds to step S1016.

[0153] In step S1012, continue to monitor and do not process when current sharing.

[0154] In step S1014, in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 0, the second comparison value corresponding to the second PWM wave signal in the second period is increased; in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 100%, the first comparison value corresponding to the first PWM wave signal in the second period is increased.

[0155] Here, in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 0, the second comparison value corresponding to the second PWM wave signal in the second period is increased, so as to reduce the duty cycle of the second PWM wave signal in the second period, and the duty cycle of the second PWM wave signal in the second period after the reduction is equal to the duty cycle of the first PWM wave signal in the second period, which can not only realize current sharing of the two branches of the double-path interleaved PFC circuit, but also reduce the bus voltage and realize adjustment of the bus voltage.

[0156] In a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in the first period are both 100% and the duty cycles of the first PWM wave signal and the second PWM wave signal in the second period are both not 100%, the first comparison value corresponding to the first PWM wave signal in the second period is increased, so as to increase the duty cycle of the first PWM wave signal in the second period, and the duty cycle of the first PWM wave signal in the second period after the increase is equal to the duty cycle of the second PWM wave signal in the second period, which can not only realize current sharing of the two branches of the double-path interleaved PFC circuit, but also increase the bus voltage and realize adjustment of the bus voltage.

[0157] In step S1016, the logic judgment is exited, and no processing is performed.

[0158] In step S1018, it is judged whether the absolute value of the difference between the first current value and the second current value is less than or equal to a threshold value. If yes, the process is exited, i.e., ended; otherwise, the process returns to step S1014.

[0159] Thus far, the control method for the double-path interleaved PFC circuit according to some other embodiments of the present disclosure is provided. By adjusting the comparison value corresponding to the first PWM wave signal or the second PWM wave signal in the second period, the duty cycle of the first PWM wave signal or the second PWM wave signal in the second period is adjusted, which can not only realize current sharing of the two branches of the double-path interleaved PFC circuit, but also realize adjustment of the bus voltage and optimize the adaptability of the double-path interleaved PFC circuit under different power grid conditions.

[0160] The above method of the present disclosure can solve the problem of large heat generation of the switching tube caused by uneven current of the two-way interleaved PFC, effectively control the heat generation of the two switching tubes to be the same, and avoid the board explosion caused by the temperature rise problem. The above method is beneficial to the more stable control of the two-way interleaved PFC circuit, and tries to avoid the situation of input current not being sinusoidal and bus voltage fluctuation. In addition, the above method can effectively control the current load of the two branches to be the same, and try to avoid the problem of damaging power components caused by excessive single current.

[0161] Figure 11 is a structural block diagram of a control device for a two-way interleaved PFC circuit according to some embodiments of the present disclosure. The two-way interleaved PFC circuit includes a first PFC branch and a second PFC branch, the first PFC branch includes a first switching device for receiving a first pulse width modulation (PWM) wave signal, and the second PFC branch includes a second switching device for receiving a second PWM wave signal. As shown in Figure 11 The control device includes an acquisition unit 1110 and an adjustment unit 1120.

[0162] The acquisition unit 1110 is configured to acquire a first current value of a first input current of the first PFC branch and a second current value of a second input current of the second PFC branch.

[0163] The adjustment unit 1120 is configured to adjust a duty cycle of the first PWM wave signal or a duty cycle of the second PWM wave signal when the first current value and the second current value do not satisfy the current sharing condition, so that the first current value and the second current value satisfy the current sharing condition.

[0164] So far, a control device for a two-way interleaved PFC circuit according to some embodiments of the present disclosure has been provided. The control device can as much as possible solve the problem of uneven current of the two-way interleaved PFC circuit in the related art, and realize current sharing of the two branches of the two-way interleaved PFC circuit.

[0165] In some embodiments, the first PWM wave signal changes from a first level to a second level when the count waveform rises from 0 to a first comparison value in a normal period, and changes from the second level to the first level when the count waveform drops from a maximum value to the first comparison value, wherein the first level is greater than the second level; the second PWM wave signal changes from a third level to a fourth level when the count waveform rises from 0 to a second comparison value in a normal period, and changes from the fourth level to the third level when the count waveform drops from a maximum value to the second comparison value, wherein the third level is less than the fourth level; and the sum of the first comparison value and the second comparison value is the maximum value of the count waveform.

[0166] In some embodiments, the adjusting unit 1120 is configured to adjust the duty cycle of the first PWM wave signal by adjusting a first comparison value corresponding to the first PWM wave signal, or adjust the duty cycle of the second PWM wave signal by adjusting a second comparison value corresponding to the second PWM wave signal.

[0167] In some embodiments, the adjusting unit 1120 is configured to, in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in a first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in a second period are both not 0, decrease the duty cycle of the second PWM wave signal in the second period so that the duty cycle of the second PWM wave signal in the second period after the decrease is equal to the duty cycle of the first PWM wave signal in the second period, wherein the second period is a next period of the first period.

[0168] In some embodiments, the adjusting unit 1120 is configured to decrease the duty cycle of the second PWM wave signal in the second period by increasing a second comparison value corresponding to the second PWM wave signal in the second period.

[0169] In some embodiments, the second comparison value T' after the increase is T' b is the maximum value of the count waveform, T a is the original first comparison value.

[0170]

[0171] wherein T max is the maximum value of the count waveform, T a is the original first comparison value.

[0172] In some embodiments, the adjusting unit 1120 is configured to, in a case where the duty cycles of the first PWM wave signal and the second PWM wave signal in a first period are both 0 and the duty cycles of the first PWM wave signal and the second PWM wave signal in a second period are both not 0, increase the duty cycle of the first PWM wave signal in the second period so that the duty cycle of the first PWM wave signal in the second period after the increase is equal to the duty cycle of the second PWM wave signal in the second period, wherein the second period is a next period of the first period.

[0173] In some embodiments, the adjusting unit 1120 is configured to increase the duty cycle of the first PWM wave signal in the second period by increasing a first comparison value corresponding to the first PWM wave signal in the second period.

[0174] In some embodiments, the first comparison value T' after the increase is T' a is the maximum value of the count waveform, T

[0175] T' a = 2T a , and T' a ≤ T max ,

[0176] wherein Tmax T is the maximum value of the counting waveform. a This is the original first comparison value.

[0177] In some embodiments, the adjustment unit 1120 is used to increase the duty cycle of the first PWM wave signal in the second cycle when the duty cycle of the first PWM wave signal and the second PWM wave signal are both 100% in the first cycle and the duty cycle of the second cycle is not 100%, so that the increased duty cycle of the first PWM wave signal in the second cycle is equal to the duty cycle of the second PWM wave signal in the second cycle, wherein the second cycle is the next cycle after the first cycle.

[0178] In some embodiments, the adjustment unit 1120 is used to increase the duty cycle of the first PWM wave signal in the second period by increasing the first comparison value corresponding to the first PWM wave signal in the second period.

[0179] In some embodiments, the increased first comparison value T″ a for

[0180]

[0181] Among them, T max T is the maximum value of the counting waveform. a This is the original first comparison value.

[0182] In some embodiments, the adjustment unit 1120 is used to reduce the duty cycle of the second PWM wave signal in the second cycle when the duty cycle of the first PWM wave signal and the second PWM wave signal are both 100% in the first cycle and the duty cycle of the second cycle is not 100%, so that the duty cycle of the reduced second PWM wave signal in the second cycle is equal to the duty cycle of the first PWM wave signal in the second cycle, wherein the second cycle is the next cycle after the first cycle.

[0183] In some embodiments, the adjustment unit 1120 is used to reduce the duty cycle of the second PWM wave signal in the second period by increasing the second comparison value corresponding to the second PWM wave signal in the second period.

[0184] In some embodiments, the increased second comparison value T″ b for

[0185] T″ b =2T b ,and

[0186] Among them, T max T is the maximum value of the counting waveform. b This is the original second comparison value.

[0187] In some embodiments, the current equalization condition is that an absolute value of a difference between the first current value and the second current value is less than or equal to a threshold value.

[0188] In some embodiments, the control device further comprises a calculation unit (not shown in the figure) configured to calculate the absolute value of the difference between the first current value and the second current value.

[0189] In some embodiments, the control device further comprises a judgment unit (not shown in the figure) configured to determine that the first current value and the second current value do not satisfy the current equalization condition if the absolute value of the difference is greater than the threshold value, and determine that the first current value and the second current value satisfy the current equalization condition if the absolute value of the difference is less than or equal to the threshold value.

[0190] Figure 12 is a structural block diagram schematically showing a control device for a dual interleaved PFC circuit according to some other embodiments of the present disclosure. The control device comprises a memory 1210 and a processor 1220. Wherein:

[0191] The memory 1210 can be a disk, a flash memory or any other non-volatile storage medium. The memory is used to store Figure 5 and / or Figure 10 instructions in the corresponding embodiments.

[0192] The processor 1220 is coupled to the memory 1210 and can be implemented as one or more integrated circuits, such as a microprocessor or a microcontroller. The processor 1220 is configured to execute the instructions stored in the memory, and can solve the problem of current imbalance of the dual interleaved PFC circuit in the related art as much as possible, and achieve current equalization of the two branches of the dual interleaved PFC circuit.

[0193] In one embodiment, as shown in Figure 13 the control device 1300 comprises a memory 1310 and a processor 1320. The processor 1320 is coupled to the memory 1310 through a BUS bus 1330. The control device 1300 can also be connected to an external storage device 1350 through a storage interface 1340 to call external data, and can also be connected to a network or another computer system (not shown) through a network interface 1360, which will not be described in detail here.

[0194] In this embodiment, the data instructions are stored in the memory, and the above instructions are processed by the processor, which can solve the problem of current imbalance of the dual interleaved PFC circuit in the related art as much as possible, and achieve current equalization of the two branches of the dual interleaved PFC circuit.

[0195] Figure 14 is a connection schematic diagram of a dual interleaved PFC circuit according to some embodiments of the present disclosure. AsFigure 14 As shown, the dual-channel interleaved PFC circuit includes a control device 1440, for example... Figure 11 , Figure 12 or Figure 13 The control device shown.

[0196] like Figure 14 As shown, the dual-channel interleaved PFC circuit may further include a first PFC branch 1401. The first PFC branch 1401 includes a first switching device T1, which is used to receive a first PWM wave signal PWMA. For example, the control terminal of the first switching device T1 receives the first PWM wave signal PWMA. For example, the first switching device may include an IGBT (Insulated Gate Bipolar Transistor).

[0197] like Figure 14 As shown, the dual-channel interleaved PFC circuit may further include a second PFC branch 1402. The second PFC branch 1402 includes a second switching device T2, which receives a second PWM wave signal PWMB. For example, the control terminal of the second switching device T2 receives the second PWM wave signal PWMB. For example, the second switching device may include an IGBT.

[0198] The control device 1440 is used to output a first PWM wave signal and a second PWM wave signal according to the counting waveform.

[0199] like Figure 14 As shown, the first PFC branch 1401 may further include: a first inductor L1, a first resistor R1, and a first diode D1 connected in series. The first terminal of the first inductor L1 is electrically connected to the rectifier circuit 1420, the second terminal of the first inductor L1 is electrically connected to the first terminal of the first resistor R1, the second terminal of the first resistor R1 is electrically connected to the anode of the first diode D1, and the cathode of the first diode D1 is electrically connected to the first terminal of the capacitor C. The first terminal of the first switching device T1 is connected between the first resistor R1 and the first diode D1, and the second terminal of the first switching device T1 is connected to the wire 1410.

[0200] like Figure 14As shown, the second PFC branch 1402 can further include a second inductor L2, a second resistor R2 and a second diode D2 connected in series. A first end of the second inductor L2 is electrically connected to the rectifier circuit 1420, a second end of the second inductor L2 is electrically connected to a first end of the second resistor R2, a second end of the second resistor R2 is electrically connected to an anode of the second diode D2, a cathode of the second diode D2 is electrically connected to a first end of the capacitor C. A first end of the second switching device T2 is connected between the second resistor R2 and the second diode D2, a second end of the second switching device T2 is connected to the wire 1410.

[0201] As shown in FIG. 1, the double-interleaved PFC circuit can further include a first current sensor 1451. The first current sensor 1451 is arranged between the first resistor R1 and the first switching device T1. The first current sensor 1451 is configured to acquire a first current value of the first input current of the first PFC branch (i.e. the current flowing through the first PFC branch when the first switching device T1 is turned on), and transmit the first current value to the control device 1440. Figure 14 As shown in FIG. 1, the double-interleaved PFC circuit can further include a second current sensor 1452. The second current sensor 1452 is arranged between the second resistor R2 and the second switching device T2. The second current sensor 1452 is configured to acquire a second current value of the second input current of the second PFC branch (i.e. the current flowing through the second PFC branch when the second switching device T2 is turned on), and transmit the second current value to the control device 1440.

[0202] Figure 14 As shown in FIG. 1, the double-interleaved PFC circuit can further include a rectifier circuit 1420. A first output end 1421 of the rectifier circuit 1420 is electrically connected to the first inductor L1 and the second inductor L2, a second output end 1422 of the rectifier circuit 1420 is electrically connected to the wire 1410. The rectifier circuit is configured to receive an alternating current AC and output a direct current. For example, the rectifier circuit is composed of four diodes.

[0203] As shown in FIG. 1, the double-interleaved PFC circuit can further include a capacitor C. A first end of the capacitor C is electrically connected to the first diode D1 and the second diode D2, a second end of the capacitor C is electrically connected to the wire 1410. Figure 14 As shown in FIG. 1, the double-interleaved PFC circuit can further include a load 1430, which is connected in parallel with the capacitor C.

[0204] Figure 14 As shown in FIG. 1, the double-interleaved PFC circuit can further include a load 1430, which is connected in parallel with the capacitor C.

[0205] As shown in FIG. 1, the double-interleaved PFC circuit can further include a load 1430, which is connected in parallel with the capacitor C. Figure 14 As shown in FIG. 1, the double-interleaved PFC circuit can further include a load 1430, which is connected in parallel with the capacitor C.

[0206] ​​In some embodiments of the present disclosure, a device is also provided, which includes the dual interleaved PFC circuit as described above. For example, the device can be a frequency converter or an air conditioning device, etc.

[0207] In another embodiment, the present disclosure also provides a computer readable storage medium (for example, a non-transitory computer readable storage medium) having stored thereon computer program instructions, which when executed by a processor implement the steps of the method in the corresponding embodiment. Figure 5 and / or Figure 10 The skilled in the art should understand that the embodiments of the present disclosure can be provided as a method, device, or computer program product. Therefore, the present disclosure can take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present disclosure can take the form of a computer program product implemented on one or more computer-usable non-transitory storage media (including, but not limited to, disk storage, CD-ROMs, optical storage devices, etc.) having computer usable program code embodied therein.

[0208] The present disclosure is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems) and computer program products according to the embodiments of the present disclosure. It should be understood that each flow and / or block in the flowcharts and / or block diagrams can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce a device that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0209] These computer program instructions can also be stored in a computer readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer readable memory produce a manufactured product including instruction devices that implement the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0210] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide steps for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks Figure 1 The functions specified in one or more flows and / or blocks

[0211] So far, the present disclosure has been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein according to the above description.

[0212] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A control method for a dual-channel interleaved power factor correction (PFC) circuit, wherein, The dual-path interleaved PFC circuit includes a first PFC branch and a second PFC branch. The first PFC branch includes a first switching device, which is used to receive a first pulse width modulation (PWM) wave signal. The second PFC branch includes a second switching device, which is used to receive a second PWM wave signal. The control method includes: Obtain the first current value of the first input current of the first PFC branch and the second current value of the second input current of the second PFC branch; and If the first current value and the second current value do not meet the current sharing condition, adjust the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal so that the first current value and the second current value meet the current sharing condition. Wherein, the first PWM wave signal, within its normal cycle, changes from a first level to a second level when the counting waveform rises from 0 to a first comparison value, and changes from the second level to the first level when the counting waveform falls from its maximum value to the first comparison value, wherein the first level is greater than the second level; the second PWM wave signal, within its normal cycle, changes from a third level to a fourth level when the counting waveform rises from 0 to a second comparison value, and changes from the fourth level to the third level when the counting waveform falls from its maximum value to the second comparison value, wherein the third level is less than the fourth level; wherein the sum of the first comparison value and the second comparison value is the maximum value of the counting waveform; The duty cycle of the first PWM wave signal is adjusted by adjusting the first comparison value corresponding to the first PWM wave signal; or the duty cycle of the second PWM wave signal is adjusted by adjusting the second comparison value corresponding to the second PWM wave signal.

2. The control method according to claim 1, wherein, Adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: When both the first PWM wave signal and the second PWM wave signal have a duty cycle of 0 in the first period and a duty cycle of 0 in the second period, the duty cycle of the second PWM wave signal in the second period is reduced so that the duty cycle of the reduced second PWM wave signal in the second period is equal to the duty cycle of the first PWM wave signal in the second period, wherein the second period is the next period after the first period.

3. The control method according to claim 2, wherein, The duty cycle of the second PWM wave signal in the second period is reduced by increasing the second comparison value corresponding to the second PWM wave signal in the second period.

4. The control method according to claim 3, wherein, The increased second comparison value for ， in, The maximum value of the counting waveform. This is the original first comparison value.

5. The control method according to claim 1, wherein, Adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: When the duty cycles of the first PWM wave signal and the second PWM wave signal are both 0 in the first cycle and are not 0 in the second cycle, the duty cycle of the first PWM wave signal in the second cycle is increased so that the increased duty cycle of the first PWM wave signal in the second cycle is equal to the duty cycle of the second PWM wave signal in the second cycle, wherein the second cycle is the next cycle after the first cycle.

6. The control method according to claim 5, wherein, The duty cycle of the first PWM wave signal in the second period is increased by increasing the first comparison value corresponding to the first PWM wave signal in the second period.

7. The control method according to claim 6, wherein, The increased first comparison value for ,and , in, The maximum value of the counting waveform. This is the original first comparison value.

8. The control method according to claim 1, wherein, Adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: When both the first PWM wave signal and the second PWM wave signal have a duty cycle of 100% in the first cycle and neither has a duty cycle of 100% in the second cycle, the duty cycle of the first PWM wave signal in the second cycle is increased so that the increased duty cycle of the first PWM wave signal in the second cycle is equal to the duty cycle of the second PWM wave signal in the second cycle, wherein the second cycle is the next cycle after the first cycle.

9. The control method according to claim 8, wherein, The duty cycle of the first PWM wave signal in the second period is increased by increasing the first comparison value corresponding to the first PWM wave signal in the second period.

10. The control method according to claim 9, wherein, The increased first comparison value for ， in, The maximum value of the counting waveform. This is the original first comparison value.

11. The control method according to claim 1, wherein, Adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal includes: When both the first PWM wave signal and the second PWM wave signal have a duty cycle of 100% in the first cycle and neither has a duty cycle of 100% in the second cycle, the duty cycle of the second PWM wave signal in the second cycle is reduced so that the reduced duty cycle of the second PWM wave signal in the second cycle is equal to the duty cycle of the first PWM wave signal in the second cycle, wherein the second cycle is the next cycle after the first cycle.

12. The control method according to claim 11, wherein, The duty cycle of the second PWM wave signal in the second period is reduced by increasing the second comparison value corresponding to the second PWM wave signal in the second period.

13. The control method according to claim 12, wherein, The increased second comparison value for ,and , in, The maximum value of the counting waveform. This is the original second comparison value.

14. The control method according to claim 1, wherein: The current sharing condition is: the absolute value of the difference between the first current value and the second current value is less than or equal to a threshold. The control method further includes: Before adjusting the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal, calculate the absolute value of the difference between the first current value and the second current value; If the absolute value of the difference is greater than the threshold, it is determined that the first current value and the second current value do not meet the current sharing condition; and If the absolute value of the difference is less than or equal to the threshold, it is determined that the first current value and the second current value satisfy the current sharing condition.

15. A control device for a dual-channel interleaved PFC circuit, wherein, The dual-path interleaved PFC circuit includes a first PFC branch and a second PFC branch. The first PFC branch includes a first switching device for receiving a first PWM wave signal. The second PFC branch includes a second switching device for receiving a second PWM wave signal. The control device includes: The acquisition unit is configured to acquire a first current value of the first input current of the first PFC branch and a second current value of the second input current of the second PFC branch; and The adjustment unit is used to adjust the duty cycle of the first PWM wave signal or the duty cycle of the second PWM wave signal when the first current value and the second current value do not meet the current sharing condition, so that the first current value and the second current value meet the current sharing condition. Wherein, the first PWM wave signal, within its normal cycle, changes from a first level to a second level when the counting waveform rises from 0 to a first comparison value, and changes from the second level to the first level when the counting waveform falls from its maximum value to the first comparison value, wherein the first level is greater than the second level; the second PWM wave signal, within its normal cycle, changes from a third level to a fourth level when the counting waveform rises from 0 to a second comparison value, and changes from the fourth level to the third level when the counting waveform falls from its maximum value to the second comparison value, wherein the third level is less than the fourth level; wherein the sum of the first comparison value and the second comparison value is the maximum value of the counting waveform; The adjustment unit is used to adjust the duty cycle of the first PWM wave signal by adjusting the first comparison value corresponding to the first PWM wave signal, or to adjust the duty cycle of the second PWM wave signal by adjusting the second comparison value corresponding to the second PWM wave signal.

16. A control device for a dual-channel interleaved PFC circuit, comprising: Memory; as well as A processor coupled to the memory, the processor being configured to execute the method as described in any one of claims 1 to 14 based on instructions stored in the memory.

17. A dual-channel interleaved PFC circuit, comprising: The control device as described in claim 15 or 16.

18. The dual-channel interleaved PFC circuit according to claim 17, further comprising: The first PFC branch includes a first switching device, which is used to receive a first PWM wave signal. and The second PFC branch includes a second switching device, which is used to receive a second PWM wave signal. The control device is used to output the first PWM wave signal and the second PWM wave signal according to the counting waveform.

19. The dual-channel interleaved PFC circuit according to claim 18, further comprising: The first current sensor is used to collect the first current value of the first input current of the first PFC branch and transmit the first current value to the control device. and The second current sensor is used to acquire the second current value of the second input current of the second PFC branch and transmit the second current value to the control device.

20. The dual-channel interleaved PFC circuit according to claim 18, wherein: The first PFC branch further includes: a first inductor, a first resistor, and a first diode connected in series, a first end of the first switching device being connected between the first resistor and the first diode, and a second end of the first switching device being connected to a wire; The second PFC branch further includes: a second inductor, a second resistor, and a second diode connected in series, with the first end of the second switching device connected between the second resistor and the second diode, and the second end of the second switching device connected to the wire.

21. The dual-channel interleaved PFC circuit according to claim 20, further comprising: A rectifier circuit, wherein the first output terminal of the rectifier circuit is electrically connected to the first inductor and the second inductor, and the second output terminal of the rectifier circuit is electrically connected to the wire; and A capacitor, wherein a first end of the capacitor is electrically connected to the first diode and the second diode, and a second end of the capacitor is electrically connected to the wire.

22. An apparatus comprising: The dual-channel interleaved PFC circuit as described in any one of claims 17 to 21.

23. A computer-readable storage medium having stored thereon computer program instructions that, when executed by a processor, implement the method as claimed in any one of claims 1 to 14.

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