Composite substrate and method for manufacturing the same

Abstract

The present invention provides a composite substrate whose wafer to be bonded has a surface roughness small enough and can prevent occurrence of film peeling, and a method for manufacturing the same. A composite substrate (40) of the present invention has a silicon wafer (10), an interlayer (11), and a single-crystal silicon thin film or an oxide single-crystal thin film (20a) laminated in the listed order, and has a damage layer (12a) in a portion of the silicon wafer (10) on the side of the interlayer (11).

Description

TECHNICAL FIELD

[0001] The present application relates to a composite substrate and a method for manufacturing the same. BACKGROUND

[0002] In order to expand the range of applications of conventional functional materials such as semiconductor and oxide single crystals, development for adhesion to different kinds of substrates to obtain higher performance has been widely conducted in recent years. In the field of semiconductor, Silicon on Insulator (SOI) and the like are known, and in the field of oxide single crystals, it has been reported that by adhesion of an oxide single crystal substrate such as lithium tantalate (LiTaO3 abbreviated as LT) or lithium niobate (LiNbO3 abbreviated as LN) to sapphire or the like and by thinning the oxide single crystal substrate, the temperature characteristics of the composite substrate are improved.

[0003] There are also attempts to provide an interlayer (also referred to as "spacer" or "middle layer") between the functional thin film and the silicon wafer for separation. An insulating material such as SiO2, which is high in insulation, low in high-frequency loss (low dielectric loss), and easy to process (planarization), is generally used as a material for the interlayer. In order to satisfy the above properties, a metal oxide (such as SiON, TiO2, Al2O3, Ta2O5, Nb2O5, Y2O3, or ZrO2, in addition to SiO2) is often selected for the interlayer. A particularly commonly used material is SiO2 obtained by thermal oxidation of silicon. The SOI wafer or "oxide single-crystal on Si wafer" (hereinafter referred to as "Piezo-material on insulator (POI)") obtained thereby generally has excellent performance such as excellent high-frequency characteristics (low high-frequency loss, improvement in linearity, and reduction in crosstalk) due to its thin active layer.

[0004] Prior Art Documents

[0005] Patent Documents

[0006] Patent Document 1: US2017 / 0033764A SUMMARY

[0007] Technical Problem to be Solved by the Invention

[0008] However, the above composite substrate obtained by adhesion through the interlayer also has a disadvantage. Silicon having a high resistance is generally used as the base substrate to reduce high frequency loss, but it is known that in this case the upper layer of the silicon wafer becomes charged and causes deterioration of the characteristics of the obtained composite substrate. In order to avoid the above problem, a countermeasure is taken by providing a carrier trap layer just below the buried insulating film in SOI (commonly referred to as "trap-rich SOI") to impart a function of causing the generated carriers to disappear. Specifically, the carrier trap layer is generally formed of polysilicon, but a problem point accompanying this is that the polysilicon layer should be smoothed to the atomic level (Ra < 1 nm) at the time of adhesion in the manufacturing process of SOI or POI. From the viewpoint of time or cost, since the polishing rate of silicon is slightly different depending on the orientation, it is not a good idea to smooth the polysilicon.

[0009] In order to solve the above problem, the present inventors devised the following method. This method is to perform ion implantation on a silicon wafer to be a base substrate or a wafer on which an insulating film is formed by thermal oxidation, a CVD method, or a PVD method, and thereby form a damage layer in the upper portion of the silicon substrate by ion implantation. Patent Document 1 and the like also propose forming a damage layer by ion implantation and using the obtained substrate as a base substrate of a POI wafer. In Patent Document 1, a "damage layer" is converted into a "non-single-crystal layer" by ion implantation to obtain a carrier trap layer. This method is very advantageous because the surface roughness is not greatly deteriorated even after ion implantation, and the wafer can be directly adhered as it is. In particular, when ion implantation is performed on a substrate having a smooth surface at the atomic level such as a silicon wafer subjected to thermal oxidation, adhesion can be directly performed as it is without applying a polishing step or the like after implantation.

[0010] However, it is known that this method can cause a problem to occur. Specifically, a large number of ions used for ion implantation during the ion implantation process remain in the wafer, and these excess ions remaining in the wafer reach the adhesion interface and cause film peeling to occur in the case of heat treatment or long-term use or the like after adhesion. Therefore, in order to maintain high reliability, it is necessary to remove the excess ions before adhesion. Although heat treatment can be performed to cause the excess ions to diffuse outward in order to remove the excess remaining ions, the silicon wafer subjected to ion implantation generates bubbles called "microcavities" therein by heat treatment, deteriorates the roughness of the surface, and thereby a surface state unsuitable for adhesion can be generated.

[0011] In view of the above problem, an object of the present application is to provide a composite substrate whose wafer to be adhered has sufficiently small surface roughness and can prevent the occurrence of film peeling, and to provide a method of manufacturing a composite substrate.

[0012] Method of solving the problem

[0013] To achieve the above object, as one aspect of the present application, there is provided a method for manufacturing a composite substrate having a silicon wafer, an interlayer, a single-crystal silicon thin film or an oxide single-crystal thin film stacked in the order of listing, the method comprising the steps of: performing heat treatment after ion implantation treatment of the silicon wafer to form a damage layer in an upper portion of the silicon wafer; bonding the silicon wafer and the single-crystal silicon wafer or the oxide single-crystal silicon wafer to each other via the interlayer therebetween to obtain a bonded body; and,

[0014] thinning the single-crystal silicon wafer or the oxide single-crystal wafer of the bonded body into a single-crystal silicon thin film or an oxide single-crystal thin film.

[0015] The interlayer preferably contains SiO2, SiON, SiN, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3 or ZrO2.

[0016] The interlayer is preferably formed by thermal oxidation of the silicon wafer. Alternatively, the interlayer is preferably formed by a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method).

[0017] The ion species implanted in the above ion implantation treatment is a hydrogen atom ion (H + ) and the dose is preferably set to 2.5 x 10 16 ~ 5.0 x 10 16 atom / cm 2 . Alternatively, the ion species implanted in the above ion implantation treatment is a hydrogen molecule ion (H2 + ) and the dose is preferably set to 1.25 x 10 16 ~ 2.5 x 10 16 atom / cm 2 .

[0018] The heat treatment is preferably performed at a temperature of 400°C or higher.

[0019] The single-crystal silicon wafer or the oxide single-crystal wafer of the bonded body is preferably thinned by grinding or polishing or a combination thereof. The method of the present application can further include the step of performing ion implantation treatment of a surface to be bonded (simply referred to as "bonding surface") of the single-crystal silicon wafer or the oxide single-crystal wafer to form an ion-implanted layer in the inside of the single-crystal silicon wafer or the oxide single-crystal wafer, and the single-crystal silicon wafer or the oxide single-crystal wafer of the bonded body is preferably thinned by leaving the ion-implanted layer as a single-crystal silicon thin film or an oxide single-crystal thin film on the bonded body and peeling off the remaining portion of the single-crystal silicon wafer or the oxide single-crystal wafer from the bonded body.

[0020] In another aspect of the present application, the present application provides a composite substrate having a silicon wafer, an interlayer, and a single-crystal silicon thin film or an oxide single-crystal thin film stacked in the listed order, and further having a damage layer in a part of the silicon wafer on the side of the interlayer.

[0021] The interlayer preferably contains SiO2, SiON, SiN, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3, or ZrO2.

[0022] The oxide single-crystal thin film preferably contains lithium tantalate (LT) or lithium niobate (LN).

[0023] Effects of the Invention

[0024] Thus, the present application provides a composite substrate and a method of manufacturing a composite substrate, in which a wafer to be bonded has a surface roughness small enough to prevent occurrence of film peeling. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a schematic flowchart illustrating one embodiment of the method of manufacturing a composite substrate of the present application.

[0026] Figure 2 is a microscope photograph showing a wafer surface on which film peeling has occurred.

[0027] Figure 3 is an atomic force microscope (AFM) image showing a thermal oxide film surface on the wafer of Example 1.

[0028] Figure 4 is a transmission electron microscope (TEM) image showing a cross section of the wafer of Example 1. DETAILED DESCRIPTION

[0029] Hereinafter, an embodiment of a composite substrate of the present application and a method of manufacturing the same will be described with reference to the accompanying drawings, but the scope of the present application is not limited to these.

[0030] The method of manufacturing a composite substrate of the present embodiment, as shown in Figure 1 includes a step of preparing a silicon wafer 10 (a), a step of preparing a single-crystal silicon wafer or an oxide single-crystal wafer 20 (b), a step of forming an interlayer 11 on the silicon wafer (c), a step of performing ion implantation treatment on the side of the interlayer 11 of the silicon wafer 10 (d), and a step of performing heat treatment on the silicon wafer 10 after the ion implantation treatment (e). Figure 1 Figure 1 Figure 1 Figure 1 Figure 1 ​​​​(e) in the above-described (a) to (d), a step of bonding the silicon wafer 10 and the single-crystal silicon wafer or oxide single-crystal wafer 20 to each other via the interlayer 11 and the damage layer 12a to obtain a bonded body 30 Figure 1 (f) in the above-described (a) to (d), and a step of thinning the single-crystal silicon wafer or oxide single-crystal wafer 20 of the bonded body 30 into a single-crystal silicon thin film or oxide single-crystal thin film 20a to obtain a composite substrate 40 Figure 1 (g) in the above-described (a) to (d). Each of the steps will be described in detail below.

[0031] The silicon wafer 10 prepared in the step (a) can be a silicon wafer generally used as a support wafer of a composite substrate, and the wafer has a diameter of, for example, 2 to 12 inches and a wafer thickness (plate thickness) of 500 to 800 μm.

[0032] As the single-crystal silicon wafer or oxide single-crystal wafer 20 prepared in the step (b) (hereinafter also referred to as "second wafer 20"), a single-crystal silicon wafer generally commercially available, which is grown by a Czochralski method, for example, can be used as the single-crystal silicon wafer, and as the oxide single-crystal wafer, a piezoelectric single crystal, such as a compound composed of lithium and a metal element such as tantalum or niobium and oxygen, is preferable. Examples of such a compound include lithium tantalate (LiTaO3 abbreviated as "LT") and lithium niobate (LiNbO3 abbreviated as "LN"). The size of the second wafer 20 is not particularly limited, and can have a diameter of, for example, 2 to 8 inches and a wafer thickness of 100 to 1000 μm.

[0033] In the step (c), the interlayer 11 is formed on the surface of the silicon wafer 10 to be bonded. The material of the interlayer 11 is preferably a material having high insulation, low high-frequency loss (low dielectric loss), and easy processing (planarization). Examples of the material include, but are not limited to, SiO2, SiON, SiN, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3, or ZrO2. As a method of forming the interlayer 11, a thermal oxidation film (SiO2) can be formed by, for example, heat-treating the silicon wafer 10 in an air atmosphere at 700 to 1200°C, or a layer of SiO2or a layer of the above-described metal oxide or the like can be formed by a chemical vapor deposition method (CVD method) or a physical vapor deposition method (PVD method).

[0034] When a thermal oxidation film is formed, the silicon wafer 10 can be heat-treated in an air atmosphere at 700 to 1200°C, for example, to form a thermal oxidation film on the surface of the silicon wafer 10. Examples of the CVD method include a thermal CVD method, a plasma CVD method, and a photo CVD method, and the like. Examples of the PVD method include a vapor deposition method, an ion plating method, and a sputtering method, and the like. The interlayer 11 preferably has a thickness of, for example, 100 to 5000 nm.

[0035] In step (d), ion implantation treatment is performed on the side of the interlayer 11 of the silicon wafer 10. By this treatment, most of the ions pass through the interlayer 11 and accumulate in the upper portion of the silicon wafer 10 (in the portion on the side of the interlayer 11), thereby forming the damage layer 12. As to the conditions of the ion implantation treatment, for example, the dose (implantation amount) of hydrogen atomic ions (H + ) is preferably between 2.5 x 10 16 atom / cm 2 and 5.0 x 10 16 atom / cm 2 . When the dose is less than 2.5 x 10 16 atom / cm 2 , it is difficult to form the damage layer. When the dose exceeds 5.0 x 10 16 atom / cm 2 , the subsequent heat treatment can cause the generation of bubbles called microcavities inside the silicon wafer subjected to this ion implantation and the deterioration of the roughness of the surface of the damage layer, possibly leading to a surface state unsuitable for adhesion. The dose of hydrogen molecular ions (H2 + ) is preferably between 1.25 x 10 16 atom / cm 2 and 2.5 x 10 16 atom / cm 2 , by which effects similar to those of hydrogen atomic ions can be produced.

[0036] The surface roughness of the damage layer 12 can be expressed by, for example, the arithmetic mean roughness Ra (JIS B 0601:2013). Observation and measurement can be performed by an atomic force microscope (AFM). The arithmetic mean roughness Ra is, for example, preferably 0.3 nm or less. The RMS, also referred to as the “root mean square roughness Rq” specified in JIS B0601:2013, is, for example, preferably 0.3 nm or less. The Rmax represents the maximum height specified in JIS B 0601:2013, and is, for example, preferably 3.0 nm or less.

[0037] As to the acceleration energy of the ions, the acceleration energy of hydrogen atomic ions (H + ) is preferably 25 to 200 KeV, and the acceleration energy of hydrogen molecular ions (H2 + ) is preferably 50 to 400 KeV. By adjusting the acceleration energy, the depth of ion implantation can be changed. The thickness of the damage layer 12 is preferably adjusted to 100 nm to 500 nm.

[0038] In step (e), the silicon wafer 10 formed with the damage layer 12 is subjected to heat treatment. This makes it possible to diffuse the large amount of excess ions remaining in the silicon wafer 10 outward by ion implantation treatment. The heat treatment temperature is preferably 400°C or higher. This ensures the diffusion of the excess ions outward while enabling the formation of the damage layer 12a. The upper limit of the heat treatment temperature is not particularly limited, but is preferably, for example, 800°C or lower.

[0039] In step (f), the silicon wafer 10 and the second wafer 20 are bonded to each other via the interlayer 11 and the damage layer 12a to obtain a bonded body 30. Before the bonding, the surface to be bonded of one or both of the silicon wafer 10 and the second wafer 20 is subjected to a surface activation treatment. As the surface activation treatment, any treatment that can activate the surface to be bonded is acceptable without particular limitation. Examples include a plasma activation treatment, a vacuum ion beam method, an ozone water treatment method, a UV ozone treatment method, and the like. As the atmosphere for the surface activation treatment, an inert gas (e.g., nitrogen or argon) and oxygen can be used alone or in combination.

[0040] The bonded body 30 obtained by bonding the silicon wafer 10 and the second wafer 20 to each other via the interlayer 11 and the damage layer 12a can be subjected to heat treatment. By this treatment, the bonded body increases the bonding strength.

[0041] In step (g), the second wafer 20 in the bonded body 30 is thinned into a single-crystal silicon thin film or an oxide single-crystal thin film 20a. As a result, a composite substrate 40 formed with the single-crystal silicon thin film or the oxide single-crystal thin film 20a on the silicon wafer 10 via the damage layer 12a and the interlayer 11 can be obtained. The thickness of the single-crystal silicon thin film or the oxide single-crystal thin film 20a is preferably, for example, 0.1 to 30 μm. As the method for thinning the second wafer 20, grinding or polishing can be used, or a Smart-Cut method (Smart-Cut method) can also be used.

[0042] Specifically, the Smart-Cut method is a method that performs the following steps: an ion implantation treatment is performed in advance on the surface to be bonded of the second wafer 20, thereby forming an ion-implanted layer inside the second wafer 20, and the remaining portion of the second wafer 20 is peeled from the bonded body 30, leaving the ion-implanted layer as the single-crystal silicon thin film or the oxide single-crystal thin film 20a. The peeling can be achieved by applying a mechanical impact using a wedge-shaped blade (not shown in the figure) or by applying a prescribed heat treatment.

[0043] In the composite substrate 40 thus obtained, even after heat treatment, no bubbles called microcavities are generated therein, the surface roughness of the damage layer 12a is not deteriorated, the single-crystal silicon thin film or the oxide single-crystal thin film 20a is appropriately bonded to each other, and the excess ions in the silicon wafer 20 are also sufficiently diffused outward, so the occurrence of film peeling can be prevented even after heat treatment after the bonding or long-term use, and the like.

[0044] Example

[0045] The following description focuses on embodiments and comparative examples, but the present invention is not limited to these examples.

[0046] Example 1

[0047] A 500 nm thermal oxide film (SiO2 film) was formed on the surface of a 150 mm diameter silicon wafer using a thermal oxidation method (in a water vapor atmosphere at 1000 °C). Observation using a 10 × 10 μm atomic force microscope (AFM) revealed a surface roughness Ra of 0.16 nm. (The last sentence appears to be incomplete and possibly refers to a different process.) 16 / cm 2 The dose (injection volume) and the acceleration energy of 83 keV were used to ionize the resulting wafer with hydrogen ions (H+). + Ion implantation treatment. As observed by AFM, the surface roughness of the thermal oxide film at this time was also Ra = 0.16 nm. The thermally oxidized silicon wafer monomer obtained by thermal oxidation was heat-treated at 500°C for 12 hours in a nitrogen atmosphere.

[0048] As observed by AFM, the surface roughness of the thermal oxide film at this time was Ra = 0.16 nm, RMS = 0.20 nm, and Rmax = 1.92 nm. The AFM image of the thermal oxide film surface at this time is as follows: Figure 3 As shown. Figure 4 The image shown is a transmission electron microscope (TEM) image of the wafer cross-section at this point. Figure 4 As shown, a damage layer 61 was confirmed to be formed in the upper layer of the silicon wafer, but it is known that the interface 62 between the thermal oxide film and silicon was not roughened.

[0049] Example 2

[0050] A 500 nm thermal oxide film (SiO2 film) was formed on the surface of a first silicon wafer with a diameter of 150 mm via thermal oxidation (in a water vapor atmosphere at 1000 °C). The surface roughness Ra of the thermal oxide film was observed at 10 × 10 μm AFM, and was 0.16 nm. The dosage range shown in Table 1 is 1.5 × 10⁻⁶. 16 / cm 2 Up to 5.5×10 16 / cm 2 Accelerating energy of 83 keV is used for hydrogen ion (H2O) ionization of thermally oxidized silicon wafers obtained through thermal oxidation. + Ion implantation treatment. These ion-implanted thermal oxide silicon wafer monomers were heat-treated at temperatures ranging from 300 to 800 °C as shown in Table 1. (The retention time was 6 hours in all cases).

[0051] Next, the resulting wafer and a second silicon wafer were adhered to each other after surface activation treatment to obtain a bonded body. The resulting bonded body was heat-treated at 250°C for 24 hours, and the second silicon wafer was thinned to a thickness of 10 μm by grinding or polishing to obtain a composite substrate. The composite substrate thus obtained was heat-treated at 900°C for 10 minutes. 900°C was selected as the maximum temperature in the manufacture of a silicon device. It was investigated whether or not film peeling occurred in each test example. Further, by TEM observation of the cross section (profile) of each test example, it was investigated whether or not a damage layer was formed in the thermal oxidation film. The results regarding the formation of a damage layer and the occurrence of film peeling are shown in Table 1. Note that the values listed vertically in Table 1 are the dose of implanted hydrogen ions (x 1018 / cm2), and the values listed horizontally are the heat treatment temperature (°C) applied to the silicon wafer on which ion implantation had been completed before bonding. 16 / cm 2 / cm 16 / cm 2 / cm 16 / cm 2 / cm

[0052] Table 1

[0053]

[0054] As shown in Table 1, the dose of the test example showing the result that no film peeling occurred in the test example in which a damage layer (carrier trap layer) was formed was in the range of 2.5 x 1018 / cm2to 5.0 x 1018 / cm2. 16 / cm 2 / cm 16 / cm 2 / cm Figure 2 A microscope photograph of the wafer surface of the test example having a damage layer and having generated peripheral and internal peeling is shown in FIG. 6. As shown in FIG. 6, a plurality of film peeling 51 was generated on the silicon wafer surface 50. Figure 2

[0055] Example 3

[0056] A composite substrate was prepared in the same manner as in Example 2, except that a lithium tantalate (LT) wafer was used in place of the second silicon wafer, the LT wafer was thinned to a thickness of 5 μm by grinding or polishing, and the heat treatment of the thermal oxidation silicon wafer on which ion implantation had been performed was performed at each temperature in the range of 300°C to 600°C shown in Table 2 (600°C is the upper limit temperature from the Curie temperature of LT). The resulting composite substrate was treated at 300°C for 30 minutes to investigate whether or not a damage layer was formed and whether or not film peeling occurred. The results are shown in Table 2. The values listed vertically in Table 2 are the dose of implanted hydrogen ions (x 1018 / cm2), and the values listed horizontally are the heat treatment temperature (°C) applied to the silicon wafer on which ion implantation had been completed before bonding. 16 / cm 2 / cm

[0057] Table 2

[0058]

[0059] As shown in Table 2, in the experimental cases where a damaged layer (carrier trap layer) was formed, the dose of the experimental cases that showed no film stripping was 2.5 × 10⁻⁶. 16 / cm 2 Up to 5.0×10 16 / cm 2 The range.

[0060] Example 4

[0061] In addition to using various methods such as CVD and PVD to replace thermal oxidation in forming silicon oxide films on silicon wafers and smoothing the surface by polishing, composite substrates were prepared in the same manner as in Examples 2 and 3, and the formation of damaged layers and the occurrence of film peeling were investigated. The results were similar to those of Examples 2 and 3, indicating that the effectiveness of the present invention does not depend on the method of oxide film formation.

[0062] Example 5

[0063] In addition to using various treatment methods such as vacuum ion beam method, ozone water treatment method, and UV ozone treatment method to replace plasma activation treatment for activating the surfaces to be bonded, composite substrates were prepared in the same manner as in Examples 2 and 3, and the formation of damaged layers and the occurrence of film peeling were investigated. The results showed no significant differences due to different activation treatments. Therefore, it can be seen that the effect of the present invention does not strongly depend on the activation treatment method. Furthermore, experiments were conducted on applying activation treatment to any one wafer and on both wafers, and the results showed no significant difference.

[0064] Example 6

[0065] Besides using H2 + Replace H + The composite substrate was prepared in the same manner as in Examples 2 and 3, except that the dose was halved and the acceleration energy was doubled (to 2 times). The formation of a damaged layer and the occurrence of film peeling were investigated. The results were the same as in Examples 2 and 3.

[0066] Example 7

[0067] In addition to using various materials such as SiON, SiN, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3, or ZrO2 to replace the thermally oxidized film (SiO2) to form an interlayer, composite substrates were prepared in the same manner as in Examples 2 and 3, and the formation of damaged layers and the occurrence of film peeling were investigated. The results were the same as in Examples 2 and 3.

[0068] Example 8

[0069] A composite substrate was prepared in the same manner as in Examples 2 and 3 except that the operation of thinning the silicon wafer or LT wafer by implanting hydrogen ions in advance on the surface to be bonded of the silicon wafer or LT wafer and peeling along the interface of the implantation in the bonded body after bonding was substituted for the operation of thinning the silicon wafer or LT wafer of the bonded body by grinding or polishing, and whether or not the formation of a damage layer and whether or not the occurrence of film peeling took place were investigated. As a result, the same results as in Examples 2 and 3 were obtained.

[0070] Explanation of reference numerals

[0071] 10: silicon wafer

[0072] 11: interlayer

[0073] 12: damage layer

[0074] 20: single crystal silicon wafer or oxide single crystal wafer

[0075] 20a: single crystal silicon thin film or oxide single crystal thin film

[0076] 30: bonded body

[0077] 40: composite substrate

Claims

1. A method of manufacturing a composite substrate having a silicon wafer, an interlayer, and an oxide single-crystal thin film stacked in the listed order, the method comprising the steps of: forming an interlayer on a surface to be bonded of a silicon wafer; performing an ion implantation treatment on a side of the interlayer of the silicon wafer and then performing a heat treatment at a temperature ranging from 400°C to 600°C to form a damage layer in a portion of the side of the interlayer of the silicon wafer; bonding the silicon wafer and an oxide single-crystal wafer to each other via the interlayer to obtain a bonded body; and thinning the oxide single-crystal wafer of the bonded body to an oxide single-crystal thin film.

2. The method of manufacturing a composite substrate according to claim 1, wherein the interlayer contains SiO2, SiON, SiN, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3, or ZrO2. The interlayer is formed by thermal oxidation of the silicon wafer. The interlayer is formed by a chemical vapor deposition (CVD) method or a physical vapor deposition (PVD) method.

5. The method of manufacturing a composite substrate according to any one of claims 1 to 3, wherein the oxide single-crystal wafer of the bonded body is thinned by grinding or polishing or a combination thereof.

6. The method of manufacturing a composite substrate according to any one of claims 1 to 3, further comprising the step of: performing an ion implantation treatment on a surface to be bonded of the oxide single-crystal wafer to form an ion-implanted layer inside the oxide single-crystal wafer; The oxide single-crystal wafer of the bonded body is thinned by leaving the ion-implanted layer as an oxide single-crystal thin film on the bonded body and peeling off the remaining portion of the oxide single-crystal wafer from the bonded body. The ion species injected by the ion implantation process is hydrogen atomic ions H + and the dose is between 2.5 x 10 16 atom / cm 2 and 5.0 x 10 16 atom / cm 2 or The ion species implanted by the ion implantation process is hydrogen molecular ions H2 + and the dose is between 1.25 x 10 16 atom / cm 2 and 2.5 x 10 16 atom / cm 2 .

7. A composite substrate manufactured by the method according to claim 1, having a silicon wafer, an interlayer, and an oxide single-crystal thin film stacked in the listed order, wherein the silicon wafer has a damage layer in a portion thereof on a side of the interlayer.

3. The method of manufacturing a composite substrate according to claim 1, wherein, 8. The composite substrate according to claim 7, wherein the interlayer contains SiO2, SiON, SiN, Al2O3, TiO2, Ta2O5, Nb2O5, Y2O3, or ZrO2.

4. The method of manufacturing a composite substrate according to claim 1 or 2, wherein, 9. The composite substrate according to claim 7 or 8, wherein the oxide single-crystal thin film contains lithium tantalate (LT) or lithium niobate (LN). ​ ​ wherein, ​ ​ The damage layer is implanted with a dose of hydrogen atoms H 16 between 2.5 x 1016 2 atom / cm 16 and 5.0 x 1016 2 atom / cm + , or The damage layer is implanted with a dose of hydrogen molecular ions H2 16 between 1.25 x 1017 2 and 2.5 x 1017 16 atom / cm 2 + .​ ​ ​

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