A low-cost high-efficiency branch predictor implementation method

Abstract

The application discloses a low-cost and high-efficiency branch predictor implementation method. The branch predictor implemented by the application comprises a basic conditional branch prediction channel used for branch prediction of a first branch instruction in a fetch width; n reduced conditional branch prediction channels used for branch prediction of the rest branch instructions except the first branch instruction in the fetch width, wherein any i-th reduced conditional branch prediction channel is used for branch prediction of an (i+1)-th branch instruction in the fetch width; and a gate circuit used for selecting a prediction result output between the basic conditional branch prediction channel and the reduced conditional branch prediction channels. The application can predict multiple conditional branch instructions in the fetch width, relieve the conflict of the conditional branch instructions in a single branch predictor, improve the prediction accuracy of the branch predictor, and has the advantages of small storage overhead, simple design logic, simple modification design and implementation of the traditional branch predictor.

Description

Technical Field

[0001] This invention relates to the field of microprocessor design, and more specifically to a low-cost, high-efficiency branch predictor implementation method. Background Technology

[0002] Branch predictors are an indispensable component in modern high-performance microprocessors. They solve control-related problems by predicting the branch behavior of branch instructions, thus the prediction accuracy of branch predictors is crucial for improving microprocessor performance. Internally, branch instructions can be divided into two main categories based on the conditions under which their branch behavior occurs: unconditional branch instructions, which always result in a jump, and conditional branch instructions, whose jump behavior depends on the specific processor state and is more difficult to predict. Modern conditional branch predictors typically record historical branch instruction jump information and use this historical information to predict future branch instruction behavior.

[0003] In superscalar processors, because multiple instructions can be issued simultaneously, the front-end must provide multiple instructions per clock cycle. With a wide fetch width (FW), multiple conditional branch instructions may be fetched at once, which impacts the performance of the branch predictor. Figure 1 As shown, there are two conditional branch instructions, br0 and br1, within the fetch width (256 bits). Under a block-based prediction strategy, the branch predictor can only predict one branch instruction at a time. This multi-branch instruction prediction causes conflicts between the branch predictor and the branch target buffer (BTB). The branch predictor stores historical branch behavior information for branch instructions, while the BTB stores branch target information. These conflicts can affect the prediction performance of the branch predictor. A common approach now is to replicate the branch predictor and the BTB according to the number of instructions within the fetch width. Each individual branch predictor and BTB then predicts only the branch behavior of one instruction within the fetch width, performing instruction-based prediction at the cost of resource consumption. This greatly alleviates the conflicts that occur when there are multiple branch instructions within the fetch width. However, the resulting storage overhead of the branch prediction table and branch target cache (BTB) consumes a significant amount of hardware storage resources. Compared to block-based branch predictors, this prediction method incurs N times the storage overhead of traditional methods when the instruction fetch width is N instructions. In scenarios with limited processor resources, such as low-cost embedded systems, this storage overhead is basically unacceptable. Therefore, in embedded superscalar processors, a branch predictor with low resource overhead and suitable for multiple instruction fetch conditions is needed. SUMMARY

[0004] The present application is to solve the technical problem: in view of the above problems of the prior art, a low-cost and efficient branch predictor implementation method is provided, and the present application aims to solve the problem of the conflict of branch instructions in the branch prediction table and the branch target buffer caused by the existence of multiple conditional branch instructions within the instruction fetch width in the superscalar processor, which further affects the branch prediction accuracy. The present application can predict multiple conditional branch instructions within the instruction fetch width, relieve the conflict of conditional branch instructions in a single branch predictor, and further improve the prediction accuracy of the branch predictor, with small storage overhead, simple design logic, and simple modification design of the traditional branch predictor.

[0005] To solve the above technical problems, the technical scheme adopted by the present application is:

[0006] A low-cost and efficient branch predictor implementation method, the implemented branch predictor comprises:

[0007] A basic conditional branch prediction channel for branch prediction of a first branch instruction within the instruction fetch width;

[0008] n reduced conditional branch prediction channels for branch prediction of the remaining branch instructions except the first branch instruction within the instruction fetch width, and any ith reduced conditional branch prediction channel is used for branch prediction of an (i+1)th branch instruction within the instruction fetch width, wherein n is a natural number greater than or equal to 1, and the value range of i is [1, n];

[0009] A gate circuit for selecting and outputting the prediction results between the basic conditional branch prediction channel and each reduced conditional branch prediction channel, and only when the branch prediction results of the previous i branch instructions are all non-jump, the branch prediction result of the (i+1)th branch instruction is outputted, if the branch prediction result of any ith branch instruction is jump, the branch prediction results of all branch instructions after the ith branch instruction are not outputted.

[0010] Optionally, the basic conditional branch prediction channel and the reduced conditional branch prediction channel each comprise a branch predictor and a branch target buffer, the branch predictor uses a branch prediction table to store the branch instruction history branch behavior information, and the branch target buffer is used to store the branch target information of the branch instruction. Compared with the basic conditional branch prediction channel, the reduced conditional branch prediction channel has a shorter history length and fewer table entries of the branch prediction table, and fewer table entries of the branch target buffer.

[0011] Optionally, the field of each table entry in the branch target cache comprises a high address BA of the branch instruction, a branch offset BO, a branch type BY and a branch target address BT.

[0012] Optionally, the basic conditional branch prediction channel comprises a basic branch predictor TAGE and a basic branch target cache LBTB, the reduced conditional branch prediction channel comprises a reduced branch predictor RTAGE and a reduced branch target cache RBTB, the reduced branch predictor RTAGE and the basic branch predictor TAGE are of the same structure but have a shorter branch prediction table history length and a smaller number of table entries; the basic branch target cache LBTB and the reduced branch target cache RBTB are of the same structure but have a smaller number of table entries.

[0013] Optionally, the step of performing a prediction operation on the conditional branch instruction comprises:

[0014] S101, cropping the instruction address of the conditional branch instruction based on a fetch width FW, and then sending the instruction address into the basic conditional branch prediction channel and the reduced conditional branch prediction channel;

[0015] S102, the basic conditional branch prediction channel and the reduced conditional branch prediction channel respectively perform branch prediction on the cropped instruction address, and select and output the prediction results between the basic conditional branch prediction channel and each reduced conditional branch prediction channel through a gate circuit, and only the branch prediction result of any i+1th branch instruction depends on the branch prediction result of the previous ith branch instruction, the branch prediction result of the i+1th branch instruction is output only when the branch prediction results of the previous ith branch instruction are all not jump, if the branch prediction result of any ith branch instruction is jump, the branch prediction results of all branch instructions after the ith branch instruction are not output.

[0016] Optionally, the cropping in step S101 refers to right shifting the instruction address by log2FW bits, wherein FW is the fetch width.

[0017] Optionally, when the basic conditional branch prediction channel and the reduced conditional branch prediction channel respectively perform branch prediction on the pruned instruction address in step S102, the step of performing branch prediction by the basic conditional branch prediction channel and performing prediction operation by the reduced conditional branch prediction channel comprises: first reading the content of the table entry of the branch target buffer, if the high address in the pruned instruction address and the high address BA of the branch instruction in the content of the table entry are the same, it is determined that the basic conditional branch prediction channel hits, the pruned instruction address is left shifted by log2FW bits and then added with the branch offset BO in the content of the table entry to obtain a branch address, the branch target address BT in the content of the table entry is taken as a branch target address, and branch prediction is performed on the branch address and the branch target address and a branch prediction result is outputted; otherwise, no branch jump information is outputted and the current prediction process is ended.

[0018] Optionally, the method further comprises the step of performing update operation on the branch instruction by the branch predictor after receiving feedback that the branch instruction is executed: checking the instruction type and address of the branch instruction, if the position of the branch instruction is greater than the position of the last branch instruction on which update operation is performed and the positions of the branch instruction and the last branch instruction on which update operation is performed are within the same instruction fetch width FW, the branch instruction information of the last branch instruction on which update operation is performed is written into the branch prediction table and the branch target buffer of the basic conditional branch prediction channel, and the branch instruction information of the branch instruction is written into the branch prediction table and the branch target buffer of the reduced conditional branch prediction channel so that the same historical information is used to access the basic conditional branch prediction channel and the reduced conditional branch prediction channel when performing prediction operation.

[0019] In addition, the application further provides a superscalar processor comprising an instruction fetch component and a branch predictor connected with each other, and the branch predictor is the branch predictor realized by the low-cost and high-efficiency branch predictor implementation method.

[0020] In addition, the application further provides a computer device comprising a microprocessor and a memory connected with each other, and the microprocessor is the superscalar processor.

[0021] Compared with the prior art, the application mainly has the following advantages:

[0022] 1. The application can predict multiple conditional branch instructions within an instruction fetch width, relieve the conflict of conditional branch instructions in a single branch predictor, and further improve the prediction accuracy of the branch predictor.

[0023] 2. The application has small storage overhead, and compared with the traditional branch predictor, the storage overhead will be greatly reduced.

[0024] 3、The branch predictor of the present application has simple logic design, and the logic design is simple because the branch prediction principle of the branch predictor is basically the same as that of the conventional branch predictor. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 A schematic diagram of the prior art for taking out multiple conditional branch instructions at one time.

[0026] Figure 2 A structural schematic diagram of the branch predictor in the embodiment of the present application.

[0027] Figure 3 A structural example of the branch predictor when n=1 in the embodiment of the present application.

[0028] Figure 4 A field structure diagram of each table entry in the branch target buffer in the embodiment of the present application. DETAILED DESCRIPTION

[0029] As shown in Figure 2 , the embodiment provides a low-cost and high-efficiency branch predictor implementation method, and the branch predictor implemented by the embodiment method comprises:

[0030] a basic conditional branch prediction channel for branch prediction of a first branch instruction in the instruction fetch width;

[0031] n reduced conditional branch prediction channels (reduced conditional branch prediction channel 1 to reduced conditional branch prediction channel n) for branch prediction of the remaining branch instructions except the first branch instruction in the instruction fetch width, and any i-th reduced conditional branch prediction channel is used for branch prediction of an i+1-th branch instruction in the instruction fetch width, wherein n is a natural number greater than or equal to 1, and the value range of i is [1, n];

[0032] a gate circuit for selecting and outputting the prediction results between the basic conditional branch prediction channel and the reduced conditional branch prediction channels, and the branch prediction result of any i+1-th branch instruction in the instruction fetch width depends on the branch prediction results of the previous i branch instructions, and the branch prediction result of the i+1-th branch instruction is output only when the branch prediction results of the previous i branch instructions are all non-jump, and if the branch prediction result of any i-th branch instruction is jump, the branch prediction results of all branch instructions after the i-th branch instruction are not output.

[0033] As shown in Figure 3 , when n=1, the structural example of the branch predictor for the superscalar processor in the embodiment is shown, that is, on the basis of the basic conditional branch prediction channel, one reduced conditional branch prediction channel is added, so that the prediction can be performed for the case that there are two conditional branch instructions in the same instruction fetch width.

[0034] In the embodiment, the basic conditional branch prediction channel and the reduced conditional branch prediction channel both include a branch predictor and a branch target buffer, the branch predictor stores branch history behavior information of branch instructions by using a branch prediction table, and the branch target buffer is used to store branch target information of branch instructions. Compared with the basic conditional branch prediction channel, the reduced conditional branch prediction channel has a shorter history length of the branch prediction table, fewer table entries of the branch prediction table, and fewer table entries of the branch target buffer.

[0035] As shown in Figure 3 In the embodiment, the basic conditional branch prediction channel includes a basic branch predictor TAGE and a basic branch target buffer LBTB, and the reduced conditional branch prediction channel includes a reduced branch predictor RTAGE and a reduced branch target buffer RBTB. The reduced branch predictor RTAGE has the same structure as the basic branch predictor TAGE, but has a shorter history length of a branch prediction table and fewer table entries. The basic branch target buffer LBTB has the same structure as the reduced branch target buffer RBTB, but has fewer table entries. The reduced branch target buffer RBTB is added in pairs with the reduced branch predictor RTAGE. By adding n pairs of the reduced branch target buffer RBTB and the reduced branch predictor RTAGE, the prediction of n+1 branch instructions within the instruction fetch width can be supported.

[0036] As shown in Figure 4 Each table entry in the branch target buffer includes a high address BA of a branch instruction, a branch offset BO, a branch type BY, and a branch target address BT.

[0037] The basic conditional branch prediction path mainly faces the first conditional branch instruction encountered within the fetch width, while the reduced conditional branch prediction path faces the second conditional branch instruction encountered within the fetch width, and the two conditional branch instructions are fetched from the memory at the same time, so the prediction behavior output of the second conditional branch instruction depends on the prediction behavior of the first conditional branch instruction, if the first conditional branch instruction is predicted to jump, the prediction result of the second conditional branch instruction is not output, and if the prediction of the first conditional branch instruction is not jump, the prediction result of the second conditional branch instruction is output. This prediction principle can be extended to the case of n+1 branch instructions. When the branch predictor is updated, the update information of the current branch instruction is written into the basic branch predictor TAGE and the basic branch target buffer LBTB by default, but the update information of the two consecutive branch instructions is retained in the branch predictor, if the two consecutive branch instructions are within the same fetch width FW, and the instruction position of the current branch instruction is greater than that of the previous branch instruction, the update information of the current branch instruction is written into the reduced branch target buffer RBTB and the reduced branch predictor RTAGE. This update principle can also be extended to the case of n+1 branch instructions.

[0038] The branch predictor of the embodiment adds n reduced conditional branch prediction paths on the basis of the existing conditional branch prediction path (basic conditional branch prediction path), and selects and outputs the prediction results between the basic conditional branch prediction path and each reduced conditional branch prediction path through a gate circuit, and only the branch prediction result of any i+1 branch instruction within the fetch width depends on the branch prediction result of the previous i branch instruction, and the branch prediction result of the i+1 branch instruction is output only when the branch prediction results of the previous i branch instructions are all not jump, if the branch prediction result of any i branch instruction is jump, the branch prediction results of all branch instructions after the i branch instruction are not output, thereby effectively solving the problem of branch instruction conflict in the branch prediction table and the branch target buffer caused by the existence of multiple conditional branch instructions within the fetch width in the superscalar processor, and further affecting the branch prediction accuracy. The prediction is aimed at the case of n+1 conditional branch instructions within the same fetch width, which can effectively improve the branch prediction accuracy of the branch predictor, and can be applied to various superscalar microprocessors, and can predict two conditional branch instructions within the fetch width, relieve the conflict of conditional branch instructions in a single branch predictor, and further improve the prediction accuracy of the branch predictor. Moreover, the storage overhead of the embodiment is small, and compared with the traditional branch predictor, the storage overhead will be greatly reduced. Moreover, the logic design of the embodiment is simple, and the prediction principle of this branch predictor is basically the same as that of the traditional branch predictor, so the modified logic design is relatively simple.

[0039] As shown inFigure 3The structure of the branch predictor supporting two branch instructions is shown as an example. The actual operation of the component mainly includes prediction operation and update operation, which will be introduced respectively.(1) Prediction operation: Since the branch predictor is for multi-instruction width processor, when the branch predictor predicts the conditional branch instruction, the instruction address will be first cropped, and the low address of the cropped address will be used to access the branch target buffer BTB. The cropping method is to right shift the instruction address by log2FW. After reading the corresponding table item of the branch target buffer BTB, the table item content will be detected. If the high address of the cropped address of the instruction is the same as the high address in the table item, it means that the branch target buffer hits, which means that the current predicted instruction is a branch instruction. The prediction of the basic branch predictor TAGE and the reduced branch predictor RTAGE uses the same cropped address and historical information for prediction. When there is a condition branch instruction hit in the basic branch target buffer LBTB and the reduced branch target buffer RBTB, the following operations will be performed: 1) The branch address of the first conditional branch instruction is the cropped address left shifted by log2FW bits plus the branch offset. 2) The branch target address of the first conditional branch instruction is the branch target address BT in the reduced branch target buffer RBTB table item. 3) When the basic branch predictor TAGE branch predictor predicts no jump, continue 4) operation, otherwise output the jump prediction information of the first conditional branch instruction, and end the current prediction process. 4) When the basic branch predictor TAGE branch prediction table predicts no jump, do not output any branch prediction jump information, and end the current prediction process, otherwise output the jump prediction information of the second conditional branch instruction. 5) The jump prediction information of the second conditional branch instruction is stored in the reduced branch target buffer RBTB. The branch address of the second conditional branch instruction is the cropped address left shifted by log2FW bits plus the branch offset BO in the reduced branch target buffer RBTB table item. 6) The branch target address of the second conditional branch instruction is the branch target address BT in the reduced branch target buffer RBTB table item. When the basic branch target buffer LBTB does not hit, do not output any branch prediction jump information, and end the current prediction process. When the basic branch target buffer LBTB hits, and the reduced branch target buffer RBTB does not hit, whether to output the branch prediction jump information in the basic branch target buffer LBTB depends on the prediction behavior of the basic branch predictor TAGE branch predictor.(2) update operation: after the branch instruction is executed in the processor, the branch predictor is fed back to update the branch prediction table and the BTB, and the update information of the two consecutive branch instructions is retained in the branch predictor. First, the type and address of the branch instruction are checked. If the current branch update instruction position is greater than the previous branch update instruction position, and the positions of the two branch update instructions are in the same FW, the update information of the previous branch update instruction is written into the basic branch predictor TAGE and the basic branch target cache LBTB, and the update information of the current branch update instruction is written into the reduced branch target cache RBTB and the reduced branch predictor RTAGE. It is worth noting that when writing into the reduced branch predictor RTAGE, the history information written is the history information of the previous branch instruction, so that the same history information can be used to access the basic branch predictor TAGE and the reduced branch predictor RTAGE during prediction. Through the prediction operation and the update operation, when two conditional branch instructions exist within the instruction fetch width, and when the first conditional branch instruction does not jump, the history branch information is written into the branch predictor, and during the next prediction, whether to predict the behavior of the second conditional branch instruction is determined according to the prediction behavior of the first conditional branch instruction.

[0040] In addition, the embodiment also includes the step of performing a prediction operation on the conditional branch instruction:

[0041] S101, the instruction address of the conditional branch instruction is clipped based on the instruction fetch width FW, and then sent to the basic conditional branch prediction channel and the reduced conditional branch prediction channel;

[0042] S102, the basic conditional branch prediction channel and the reduced conditional branch prediction channel respectively perform branch prediction on the clipped instruction address, and select and output the prediction results between the basic conditional branch prediction channel and each reduced conditional branch prediction channel through a gate circuit, and only when the branch prediction results of any ith branch instruction within the instruction fetch width depend on the branch prediction results of the previous (i-1)th branch instruction, the branch prediction results of the ith branch instruction are output only when the branch prediction results of the previous (i-1)th branch instruction are all non-jump. If the branch prediction result of any ith branch instruction is jump, the branch prediction results of all branch instructions after the ith branch instruction are not output.

[0043] The clipping in step S101 of the embodiment refers to right shifting the instruction address by log2FW bits, where FW is the instruction fetch width.

[0044] In the step of performing branch prediction by the basic conditional branch prediction channel and the reduced conditional branch prediction channel on the pruned instruction address in step S102 of the embodiment, the steps of performing branch prediction by the basic conditional branch prediction channel and the prediction operation by the reduced conditional branch prediction channel include: first reading the content of the table entry of the branch target buffer, if the high address in the pruned instruction address and the high address BA of the branch instruction in the content of the table entry are the same, it is determined that the basic conditional branch prediction channel is hit, the pruned instruction address is left shifted by log2FW bits and added with the branch offset BO in the content of the table entry to obtain a branch address, the branch target address BT in the content of the table entry is taken as a branch target address, and the branch prediction is performed on the branch address and the branch target address and the branch prediction result is outputted; otherwise, no branch jump information is outputted, and the current prediction process is ended.

[0045] In addition, the embodiment further includes the step of performing an update operation on the branch instruction by the branch predictor after receiving the feedback that the branch instruction is executed: checking the instruction type and address of the branch instruction, if the position of the branch instruction is greater than the position of the branch instruction on which the last update operation is performed, and the positions of the branch instruction and the branch instruction on which the last update operation is performed are in the same instruction fetch width FW, the branch instruction information of the branch instruction on which the last update operation is performed is written into the branch prediction table and the branch target buffer of the basic conditional branch prediction channel, and the branch instruction information of the branch instruction is written into the branch prediction table and the branch target buffer of the reduced conditional branch prediction channel so that the same historical information is used to access the basic conditional branch prediction channel and the reduced conditional branch prediction channel when the prediction operation is performed.

[0046] In summary, for the case of conflict in the prediction of branch instructions in the case of multiple instruction fetch widths, the low-cost and efficient branch predictor implementation method of the embodiment is based on the original branch predictor, and the branch information of multiple branch instructions in the same instruction fetch width is stored separately by adding a branch prediction table and a branch target buffer table, the branch information of different branch instructions is isolated, the prediction of the branch predictor is more accurate, and the storage overhead is also small, which is a cost-effective branch predictor implementation method.

[0047] In addition, the embodiment further provides a superscalar processor including an instruction fetch component and a branch predictor connected to each other, and the branch predictor is the branch predictor implemented by the low-cost and efficient branch predictor implementation method.

[0048] In addition, the embodiment further provides a computer device including a microprocessor and a memory connected to each other, and the microprocessor is the superscalar processor.

[0049] Those skilled in the art will appreciate that embodiments of the application can be readily used as a method, apparatus, or computer program product. Accordingly, the application can take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the application can take the form of a computer program product on one or more computer readable storage media (including, but not limited to, disk memory, CD-ROMs, optical storage devices, etc.) embodying computer readable program code. The application is described in reference to the flow diagrams and / or block diagrams of the methods, apparatus (systems) and computer program products according to embodiments of the application illustrated in the attached drawings, which flow diagrams and / or block diagrams Figure 1 one or more functions specified in the flow or flows and / or block or blocks of the flow diagrams and / or block diagrams. Figure 1 one or more functions specified in the flow or flows and / or block or blocks of the flow diagrams and / or block diagrams. Figure 1 one or more functions specified in the flow or flows and / or block or blocks of the flow diagrams and / or block diagrams. Figure 1 one or more functions specified in the flow or flows and / or block or blocks of the flow diagrams and / or block diagrams. Figure 1 one or more functions specified in the flow or flows and / or block or blocks of the flow diagrams and / or block diagrams. Figure 1 one or more functions specified in the flow or flows and / or block or blocks of the flow diagrams and / or block diagrams.

[0050] The above description is only preferred embodiments of the application, the protection scope of the application is not limited to the above-mentioned embodiments, and any technical scheme falling within the idea of the application belongs to the protection scope of the application. It should be noted that, for ordinary skilled in the art, some improvements and refinements without departing from the principles of the application, these improvements and refinements should also be considered as the protection scope of the application.

Claims

1. A low-cost, high-efficiency branch predictor implementation method, characterized in that, The implemented branch predictor includes: A basic conditional branch prediction channel is used for branch prediction of the first branch instruction within the value width. n A reduced conditional branch prediction channel is used for branch prediction of all branch instructions within the value width except the first branch instruction. i The reduced conditional branch prediction channel is used to target the first value within the value width. i+ Branch prediction for a single branch instruction, where n For natural numbers greater than or equal to 1, i The range of values ​​for is [1, ... n ]; A gate circuit used to select and output the prediction result between the basic conditional branch prediction channel and each reduced conditional branch prediction channel, and only within any value width... i The branch prediction result of +1 branch instruction depends on the previous one. i The branch prediction result of the branch instruction is only the first one. i The branch prediction result of each branch instruction is only output when there is no jump. i The branch prediction result of +1 branch instruction, if any of the first branch... i If the branch prediction result of the branch instruction is a jump, then the branch prediction result of the branch instruction is a jump. i The branch prediction results for all branch instructions after the first branch instruction are not output; The basic conditional branch prediction channel includes a basic branch predictor TAGE and a basic branch target cache LBTB. The reduced conditional branch prediction channel includes a reduced branch predictor RTAGE and a reduced branch target cache RBTB. The reduced branch predictor RTAGE has the same structure as the basic branch predictor TAGE, but its branch prediction table history is shorter and has fewer entries. The basic branch target cache LBTB has the same structure as the reduced branch target cache RBTB, but has fewer entries. This includes the steps of performing prediction operations on conditional branch instructions: S101, based on instruction fetch width FW The instruction addresses of conditional branch instructions are trimmed and then sent to the basic conditional branch prediction channel and the reduced conditional branch prediction channel. S102, the basic conditional branch prediction channel and the reduced conditional branch prediction channel perform branch prediction on the pruned instruction address, respectively, and select the prediction result between the basic conditional branch prediction channel and each reduced conditional branch prediction channel through gate circuits and output it, and only output the prediction result at any point within the value width. i The branch prediction result of +1 branch instruction depends on the previous one. i The branch prediction result of the branch instruction is only the first one. i The branch prediction result of each branch instruction is only output when there is no jump. i The branch prediction result of +1 branch instruction, if any of the first branch... i If the branch prediction result of the branch instruction is a jump, then the branch prediction result of the branch instruction is a jump. i The branch prediction results for all branch instructions following the first branch instruction are not output.

2. The low-cost, high-efficiency branch predictor implementation method according to claim 1, characterized in that, Both the basic conditional branch prediction channel and the reduced conditional branch prediction channel include a branch predictor and a branch target cache. The branch predictor uses a branch prediction table to store historical branch behavior information of branch instructions. The branch target cache is used to store the branch target information of branch instructions. Compared with the basic conditional branch prediction channel, the reduced conditional branch prediction channel has a shorter historical length of branch prediction table and fewer entries, and the branch target cache has fewer entries.

3. The low-cost, high-efficiency branch predictor implementation method according to claim 2, characterized in that, Each entry in the branch target cache includes the high-order address of the branch instruction (BA), the branch offset (BO), the branch type (BY), and the branch target address (BT).

4. The low-cost, high-efficiency branch predictor implementation method according to claim 1, characterized in that, In step S101, pruning refers to shifting the instruction address to the right by log2. FW Position, among which FW This refers to the width of the finger.

5. The low-cost, high-efficiency branch predictor implementation method according to claim 4, characterized in that, In step S102, when the basic conditional branch prediction channel and the reduced conditional branch prediction channel perform branch prediction on the pruned instruction address, the steps of the basic conditional branch prediction channel performing branch prediction and the reduced conditional branch prediction channel performing prediction operations include: firstly, reading the entry content of the branch target cache; if the high-order address in the pruned instruction address is the same as the high-order address BA of the branch instruction in the entry content, then it is determined that the basic conditional branch prediction channel has hit, and the pruned instruction address is shifted left by log2. FW The branch offset BO in the table entry is added to the branch address, and the branch target address BT in the table entry is used as the branch target address. Branch prediction is performed on the branch address and the branch target address, and the branch prediction result is output. Otherwise, no branch jump information is output, and the current prediction process ends.

6. The low-cost, high-efficiency branch predictor implementation method according to claim 5, characterized in that, It also includes the step of the branch predictor performing an update operation on the branch instruction after receiving feedback that the branch instruction has been executed: checking the instruction type and address of the branch instruction; if the position of the branch instruction is greater than the position of the previous branch instruction that performed the update operation, and the positions of the branch instruction and the previous branch instruction that performed the update operation are within the same instruction fetch width. FW Within this process, the branch instruction information of the previous update operation is written into the branch prediction table and branch target cache of the basic conditional branch prediction channel, and the branch instruction information of that branch instruction is written into the branch prediction table and branch target cache of the reduced conditional branch prediction channel, so that the same historical information can be used to access both the basic conditional branch prediction channel and the reduced conditional branch prediction channel when performing prediction operations.

7. A superscalar processor, comprising an instruction fetching unit and a branch predictor interconnected, characterized in that, The branch predictor is a branch predictor implemented by the low-cost and high-efficiency branch predictor implementation method according to any one of claims 1 to 6.

8. A computer device comprising a microprocessor and a memory interconnected, characterized in that, The microprocessor is the superscalar processor as described in claim 7.

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