Method for manufacturing dynamic random access memory

Abstract

The application provides a manufacturing method of dynamic random access memory, comprising the following steps: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on the sidewall of the opening; forming a first barrier layer and a first conductor layer in the opening; performing a first dry etching process to partially remove the first barrier layer and the first conductor layer in a first stage; performing a first wet etching process to partially remove the first barrier layer and the first conductor layer in a second stage, and to expose the dielectric layer on the upper sidewall of the opening; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing part of the second barrier layer and part of the mask layer to expose the dielectric layer on the upper sidewall of the opening; and forming a second conductor layer in the opening.

Description

TECHNICAL FIELD

[0001] The present application relates to an integrated circuit and a manufacturing method thereof, and more particularly to a dynamic random access memory and a manufacturing method thereof. BACKGROUND

[0002] With the rapid development of technology, in order to meet the needs of consumers for small electronic devices, the size of dynamic random access memory design is continuously reduced and developed towards high integration. In recent years, buried word line dynamic random access memory (buried word line DRAM) has been developed. In the process of buried word line dynamic random access memory, as the size of the components is continuously reduced, the process margin is also reduced. When forming the buried word line, if metal, barrier layer or process by-products are left on the dielectric layer of the buried word line trench sidewall, it will cause problems of component reliability. SUMMARY

[0003] Embodiments of the present application provide a dynamic random access memory and a manufacturing method thereof, which can avoid metal, barrier layer or process by-products left on the dielectric layer of the buried word line trench sidewall, and improve the reliability of the components.

[0004] Embodiments of the present application provide a manufacturing method of a dynamic random access memory, comprising: forming a hard mask layer on a substrate; forming an opening in the hard mask layer and the substrate; forming a dielectric layer on the sidewall of the opening; forming a first barrier layer and a first conductor layer in the opening; performing a first dry etching process to partially remove the first barrier layer and the first conductor layer in a first stage; performing a first wet etching process to partially remove the first barrier layer and the first conductor layer in a second stage, and to expose the dielectric layer on the upper sidewall of the opening; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing part of the second barrier layer and part of the mask layer to expose the dielectric layer on the upper sidewall of the opening; and forming a second conductor layer in the opening.

[0005] Based on the above, embodiments of the present application use a wet etching process in the process of forming a buried word line to avoid the barrier layer left on the dielectric layer of the upper sidewall of the word line trench. Moreover, since the wet etching process is performed at low temperature, it can reduce the damage to the dielectric layer of the upper sidewall of the word line trench, avoid the damage to the dielectric layer of the upper sidewall caused by the plasma used in the dry etching process, and avoid the oxidation residues (such as WO x ) formed by the reaction of plasma and the conductor layer. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figures 1A-1Iis a cross-sectional schematic view of a manufacturing method of a dynamic random access memory according to an embodiment of the present invention.

[0007] Reference Signs List

[0008] 10: substrate

[0009] 12: hard mask layer

[0010] 14: opening

[0011] 16: dielectric layer

[0012] 18, 18a, 18b, 26, 26a, 26b: barrier layer

[0013] 20, 20a, 20b, 28: conductor layer

[0014] 30: buried word line

[0015] 32: insulating layer

[0016] 22, 24, 42, 44, 46: process

[0017] H1: depth

[0018] H2: depth

[0019] P1: first portion

[0020] P2: second portion

[0021] USW: upper sidewall

[0022] LSW: lower sidewall DETAILED DESCRIPTION

[0023] Reference will now be made in detail embodiments of the application, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used in the drawings and the description to refer to the same or like parts.

[0024] Referring to Figure 1A , a substrate 10, for example a silicon substrate, is provided. Thereafter, a hard mask layer 12 having an opening pattern is formed on the substrate 10. The formation method of the hard mask layer 12 is, for example, self-aligned double patterning (SADP). The material of the hard mask layer 12 is, for example, a combination of an inorganic film (layer) and an organic film (layer). An example of the inorganic film is, for example, silicon dioxide, and the formation method thereof is, for example, chemical vapor deposition or atomic layer deposition. An example of the organic film is, for example, a carbon film, and the formation method thereof is, for example, chemical vapor deposition or spin coating.

[0025] Thereafter, an etching process is performed using the hard mask layer 12 as a mask to partially remove the substrate 10 to form an opening 14. The organic hard mask layer can be removed by a dry ashing process, and the inorganic hard mask layer remains on the substrate 10.

[0026] The opening 14 is, for example, a trench. In the present embodiment, the opening 14 is exemplified by a buried word line trench 14, but the present application is not limited thereto. The depth Hl of the buried word line trench 14 is, for example, 110 nm to 130 nm.

[0027] Referring to Figure 1A , a dielectric layer 16 is formed on the sidewalls of the buried word line trench 14. Thereafter, a barrier layer 18 and a conductor layer (i.e., a first conductor layer) 20 are formed on the hard mask layer 12 and in the buried word line trench 14. The dielectric layer 16 is conformally formed on the inner surfaces of the buried word line trench 14. In detail, the barrier layer 18 is formed on the hard mask layer 12 and in the buried word line trench 14, and the conductor layer 20 is formed on the barrier layer 18 in the buried word line trench 14 and on the hard mask layer 12. The dielectric layer 16 can be an oxide layer, for example, silicon oxide, formed by, for example, in-situ steam generation (ISSG). The barrier layer 18 can also be referred to as an adhesion layer. The barrier layer 18 can be a single layer or a plurality of layers, and the material thereof includes a metal or a metal alloy, for example, titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The material of the conductor layer 20 includes a metal or a metal alloy, for example, tungsten.

[0028] Figure 1B With Figure 1C A two-stage etching process is performed to remove the barrier layer 18 and the conductor layer 20 on the hard mask layer 12, leaving the barrier layer 18b and the conductor layer 20b in the buried word line trench 14. In the embodiment of the present application, the two-stage etching process includes a dry etching process and a wet etching process, which are described in detail as follows.

[0029] Referring to Figure 1B , a first-stage etching process 22 is performed. The first-stage etching process 22 is a dry etching process to remove the barrier layer 18 and the conductor layer 20 on the hard mask layer 12, leaving the barrier layer 18a and the conductor layer 20a in the buried word line trench 14. The dry etching process is, for example, a reactive ion etching process. In one embodiment, the top of the barrier layer 18a is higher than the top of the conductor layer 20a.

[0030] Referring to Figure 1CThe second stage etching process 24 is a wet etching process to partially remove the barrier layer 18a and the conductor layer 20a, leaving the remaining barrier layer 18b and the conductor layer 20b on the lower sidewall LSW and the bottom of the buried word line trench 14, and exposing the dielectric layer 16 on the upper sidewall USW of the buried word line trench 14. In one embodiment, the top of the barrier layer 18b and the conductor layer 20b is flush.

[0031] An etchant used in the wet etching process is, for example, an aqueous solution of sulfuric acid and hydrogen peroxide. The volume ratio of sulfuric acid to hydrogen peroxide is, for example, 6:1. The wet etching process is performed at a low temperature. The temperature of the etchant is, for example, less than 60°C. In one embodiment, the temperature of the etchant is 40 to 50°C. The depth H2 of the remaining conductor layer 20b is, for example, about 1 / 4 to 1 / 3 of the depth Hl of the buried word line trench 14. In some embodiments, the depth H2 of the remaining conductor layer 20b is, for example, between 60 nm and 70 nm. The conductor layer 20b and the barrier layer 18b on the lower portion of the buried word line trench 14 serve as the first portion PI of the buried word line.

[0032] The use of the wet etching process 24 avoids the residual barrier layer 18a on the dielectric layer 16 on the upper sidewall USW of the buried word line trench 14. Moreover, since the wet etching process is performed at a low temperature, the damage to the dielectric layer 16 on the upper sidewall USW of the buried word line trench 14 is reduced, the damage to the dielectric layer 16 on the upper sidewall USW caused by the plasma used in the dry etching process is avoided, and the formation of oxidation residues (e.g., WO x ) by the reaction of the plasma with the conductor layer 20b is avoided. Furthermore, the use of the low temperature wet etching process facilitates the control of the depth of the remaining conductor layer 20b and the remaining barrier layer 18b, and increases the uniformity of the process.

[0033] Referring to Figure 1D A barrier layer (i.e., a second barrier layer) 26 is formed on the substrate 10. That is, the barrier layer 26 is formed on the sidewalls and the bottom of the buried word line trench 14, and the remaining conductor layer 20b and the remaining barrier layer 18b are covered by the barrier layer 26. The barrier layer 26 can be a single layer or multiple layers, and the material thereof includes a metal or a metal alloy, such as titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof. The barrier layer 26 can be formed by a physical vapor deposition method, such as a sputtering method. The thickness of the barrier layer 26 is, for example, 2 nm to 3 nm.

[0034] Referring to Figure 1EA mask layer 27 is formed on the barrier layer 26 in the buried word line trench 14. The mask layer 27 is formed in the buried word line trench 14 such that the barrier layer 26 in the buried word line trench 14 can be covered. The mask layer 27 is, for example, a bottom anti-reflective coating (BARC). The mask layer 27 is formed by, for example, a spin coating method.

[0035] Figures 1F-1H A three-stage process is performed to remove part of the barrier layer 26 and the mask layer 27, leaving the barrier layer 26b in the buried word line trench 14. In an embodiment of the present application, the three-stage etching process includes two dry etching processes and a wet etching process, which are described in detail as follows.

[0036] Referring to Figure 1F A first stage process 42 is performed with the mask layer 27 as a mask. The first stage process 42 is a dry etching process to remove the barrier layer 26 on the hard mask layer 12, leaving the barrier layer 26a in the buried word line trench 14. The dry etching process is, for example, a reactive ion etching process.

[0037] Referring to Figure 1G A second stage process 44 is performed. The second stage process 44 is a dry ashing process to remove the mask layer 27, exposing the barrier layer 26a. The second stage process and the first stage process can be performed in the same reactive ion etching machine. The barrier layer 26a covers the dielectric layer 16 of the upper sidewall USW of the buried word line trench 14 and the conductor layer 20b and the barrier layer 18b of the lower sidewall LSW and the bottom of the buried word line trench 14.

[0038] Referring to Figure 1H A third stage process 46 is performed. The third stage process 46 is a wet etching process to partially remove the barrier layer 26a, leaving the barrier layer 26b covering the conductor layer 20b and the barrier layer 18b of the lower sidewall LSW and the bottom of the buried word line trench 14 and exposing the dielectric layer 16 of the upper sidewall USW of the buried word line trench 14. The etchant used in the wet etching process is, for example, an aqueous solution of sulfuric acid and hydrogen peroxide. The volume ratio of sulfuric acid to hydrogen peroxide is, for example, 14:1. The wet etching process is performed at a low temperature. The temperature of the etchant is, for example, less than 60°C. In an embodiment, the temperature of the etchant is 40 to 50°C.

[0039] The wet etching process 46 can avoid the barrier layer 26a remaining on the dielectric layer 16 of the upper sidewall USW of the buried word line trench 14. Moreover, since the wet etching process is performed at a low temperature, the dielectric layer 16 of the upper sidewall USW of the buried word line trench 14 can be less damaged and the loss of the conductor layer 20b can be reduced.

[0040] Referring to Figure 1IA conductor layer (i.e., a second conductor layer) 28 is formed in the buried word line trench 14. The material of the conductor layer 28 is different from that of the conductor layer 20. In some embodiments, the conductor layer 20 is a metal or a metal alloy; the conductor layer 28 is doped polysilicon. The bottom surface of the conductor layer 28 covers and contacts the barrier layer 26b, and the sidewall of the conductor layer 28 contacts the dielectric layer 16. The conductor layer 28 can be formed by depositing and etching back a doped polysilicon layer. The thickness of the conductor layer 28 is, for example, 10-20 nm. The conductor layer 28 and the barrier layer 26b form a first portion P1 of the buried word line 30, and the conductor layer 20b and the barrier layer 18b form a second portion P2 of the buried word line 30. The resistance of the conductor layer 20b of the first portion P1 is lower than that of the conductor layer 28, and the conductor layer 20b is separated from the dielectric layer 16 by the barrier layer 18b. The conductor layer 28 of the second portion P2 contacts the dielectric layer 16 and is separated from the conductor layer 20b by the barrier layer 26b.

[0041] Please refer to Figure 1I An insulating layer 32 is formed in the buried word line trench 14. The material of the insulating layer 32 is, for example, silicon nitride. The insulating layer 32 can be formed by depositing and etching back an insulating material layer.

[0042] In summary, the present application can avoid the barrier layer remaining on the dielectric layer of the upper sidewall of the word line trench by using the wet etching process in forming the buried word line. Moreover, since the wet etching process is performed at low temperature, the dielectric layer of the upper sidewall of the word line trench can be less damaged, the damage to the dielectric layer of the upper sidewall caused by the plasma used in the dry etching process can be avoided, and the oxidation residue (e.g., WO x ) formed by the reaction between the plasma and the conductor layer can be avoided. In addition, the wet etching process at low temperature is easy to control the depth of the remaining first portion, and increases the uniformity of the process.

[0043] Finally, it should be noted that the above-described embodiments are merely intended to illustrate the technical solutions of the present application, and not to limit the same; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still make modifications to the technical solutions described in the foregoing embodiments, or make equivalent replacements to some or all of the technical features; and such modifications or replacements do not cause the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a dynamic random access memory, comprising: forming a hard mask layer on the substrate; forming openings in the hard mask layer and the substrate; forming a dielectric layer on sidewalls of the opening; forming a first barrier layer and a first conductor layer in the opening; After forming the first barrier layer and the first conductor layer, performing a first dry etching process to partially remove the first barrier layer and the first conductor layer in a first stage; After the first dry etching process, performing a first wet etching process to partially remove the first barrier layer and the first conductive layer in a second stage and expose the dielectric layer on the upper sidewall of the opening, wherein the temperature of the etchant used in the first wet etching process is lower than 60° C.; forming a second barrier layer in the opening; forming a mask layer in the opening to cover the second barrier layer; removing a portion of the second barrier layer and the mask layer to expose the dielectric layer on the upper sidewall of the opening; as well as A second conductor layer is formed in the opening.

2. The method for manufacturing a dynamic random access memory according to claim 1, wherein: Removing a portion of the second barrier layer and a portion of the mask layer further includes: performing a second dry etching process to partially remove the second barrier layer in the first stage; removing the mask layer; A second wet etching process is performed to partially etch the second barrier layer in a second stage to expose the dielectric layer on the upper sidewall of the opening.

3. The method for manufacturing a dynamic random access memory according to claim 1, wherein: After performing the first wet etching process, the remaining first barrier layer and the remaining first conductor layer are located on the lower sidewall and bottom of the opening. The depth of the remaining first conductor layer is 1 / 4 to 1 / 3 of the depth of the opening.

4. The method for manufacturing a dynamic random access memory according to claim 1, wherein: The etchant used in the first wet etching process includes an aqueous solution of sulfuric acid and hydrogen peroxide.

5. The method for manufacturing a dynamic random access memory according to claim 2, wherein: The temperature of the etchant used in the second wet etching process is below 60° C.

6. The method for manufacturing a dynamic random access memory according to claim 2, wherein: The etchant used in the second wet etching process includes an aqueous solution of sulfuric acid and hydrogen peroxide.

7. The method for manufacturing a dynamic random access memory according to claim 2, wherein: The first dry etching process includes a reactive ion etching process, and the second dry etching process includes a reactive ion etching process.

8. The method for manufacturing a dynamic random access memory according to claim 1, wherein: The method further includes filling an insulating layer in the opening to cover the second conductor layer.

9. The method for manufacturing a dynamic random access memory according to claim 1, wherein: The thickness of the second conductor layer is 10 nm to 20 nm.

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