Two-step high-speed ADC circuit based on single-slope and level-coded TDC

Abstract

The present invention discloses a two-step high-speed ADC circuit based on a single-slope and level-coded TDC. The circuit is characterized by comprising a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit. The output of the single-slope digital logic circuit and the output of the time-to-digital conversion TDC circuit are output through an accumulator as the analog-to-digital conversion result OUT of the entire circuit. The TDC employs a cyclic level coding scheme, automatically performing a carry function to the single-slope counting logic. Furthermore, the circuit is effectively compatible with digital correlated double sampling technology, subtracting two quantization results with non-ideal factors to obtain a more accurate quantization result.

Description

Technical Field

[0001] The invention belongs to the technical field of analog-to-digital conversion and relates to a two-step high-speed ADC circuit based on a single-slope and level-coded TDC. Background Art

[0002] CMOS image sensors have garnered significant attention due to their low power consumption and fast imaging speeds. With the widespread development of image sensors, high frame rates and resolutions are increasingly demanding in some high-speed cameras. The speed and accuracy of traditional single-slope analog-to-digital converters are no longer sufficient for practical applications. Building on this, others have proposed a traditional single-slope analog-to-digital converter with time-delayed detection (TDC) technology.

[0003] A traditional TDC encoding principle is shown in the attached Figure 1 As shown in the figure, under this encoding logic, the four flip-flops are triggered in sequence as the four clocks arrive. At different clock edges, the flip-flop outputs flip. This edge-triggered approach produces different outputs. The state transition diagram is then used to derive the transient state equations. The encoder is then used to encode the different outputs, yielding a 2-bit binary digital conversion result ranging from 00 to 11.

[0004] This TDC technology uses the edge-triggered encoding method unique to D-type flip-flops, requiring a relatively complex encoding structure. This complex encoding circuit introduces non-idealities such as signal delay, which can affect the speed of actual quantization. Furthermore, edge-triggered encoding cannot implement automatic carry, making it unsuitable for periodic correlated double sampling with a single-slope ADC. Finally, achieving 2-bit time-to-digital conversion requires a strict four-term clock in the delay-locked loop (DLL). Since the DLL's voltage-controlled delay chain uses feedback to generate a stable and correlated four-term clock, clock jitter caused by non-idealities is more pronounced and uncontrollable with a four-term clock. This TDC mode significantly reduces the ADC's quantization accuracy and speed, resulting in suboptimal conversion results.

[0005] The single-slope ADC with traditional TDC technology mentioned above shows that the actual quantization effect is not ideal. This TDC using an edge-triggered structure has significant room for improvement to further improve the quantization effect, thereby achieving higher speed and accuracy. Summary of the Invention

[0006] The present invention aims to provide a two-step high-speed ADC circuit based on a single-slope and level-coded TDC. The circuit can automatically complete the carry function to the single-slope counting logic, effectively compatible with digital correlated double sampling technology, and subtract two quantization results with non-ideal factors to obtain a more accurate quantization result.

[0007] The technical solution adopted by the present invention is a two-step high-speed ADC circuit based on a single-slope and level-coded TDC, including a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit. The output of the single-slope digital logic circuit and the output of the time-to-digital conversion TDC circuit are output through an accumulator to output the analog-to-digital conversion result OUT of the entire circuit.

[0008] The present invention is also characterized in that:

[0009] The single-slope digital logic ADC circuit includes a comparator CMP1 , an output terminal C of the comparator CMP1 is connected to the digital logic circuit, and another output terminal START of the comparator CMP1 is connected to the time-to-digital conversion TDC circuit.

[0010] The digital logic circuit includes a trigger DFF1, a D terminal of the trigger DFF1 is connected to a control signal clk_sam, and a CLK terminal of the trigger DFF1 is connected to an output terminal C of the comparator CMP1;

[0011] It also includes an inverter inv1, an input end of the inverter inv1 is connected to the control signal ramp_L, an output end of the inverter inv1 and a Q end of the trigger DFF1 are commonly connected to an input end of an AND gate AND, an output end of the AND gate AND is connected to an input end of a counter COUNTER, and an output N2 of the counter COUNTER outputs an actual conversion result after the single-slope digital logic ADC circuit performs correlated double sampling.

[0012] The time-to-digital conversion (TDC) circuit includes a DLL capable of generating delayed clocks CLK1 and CLK2. CLK1 and CLK2 are connected to the input of an exclusive-OR gate XOR. The output of XOR is connected to the input of an inverter inv2. The output of inverter inv2 is connected to the input D of a flip-flop DFF2. The output Y0 of the flip-flop DFF2 serves as the lowest bit of the correlated double sampling counting logic. The CLK terminal of the flip-flop DFF2 is connected to the output START of the comparator CMP1.

[0013] CLK1 is connected to the input of inverter inv3, the output of inverter inv3 is connected to the input D of trigger DFF3, the CLK of trigger DFF3 is connected to the output START of comparator CMP1; the output Y1 of trigger DFF3 serves as the second lowest bit of the correlated double sampling counting logic.

[0014] The output N2 of the counter COUNTER, the output Y0 of the flip-flop DFF2, and the output Y1 of the flip-flop DFF3 are output through the accumulator as the analog-to-digital conversion result OUT of the entire circuit.

[0015] The beneficial effects of the present invention are as follows:

[0016] 1. This structure only requires the DLL to provide two clocks, and uses the levels of the two clocks for digital encoding. Under this encoding method, the TDC's demand for the DLL is more effectively released, while breaking the bottleneck of low quantization accuracy caused by the DLL's clock jitter.

[0017] 2. While traditional edge coding requires complex encoding logic, the TDC structure in this invention is simpler, resulting in less latency between input and output and faster quantization. This invention achieves high-speed analog-to-time-to-digital conversion while maintaining quantization accuracy, providing an effective solution for high-performance CMOS image sensors. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 This is a schematic diagram of the traditional clock compression TDC encoding principle;

[0019] Figure 2 A schematic diagram of the structure of a two-step high-speed ADC circuit based on a single-slope and level-coded TDC according to the present invention;

[0020] Figure 3 A schematic diagram of converting a ramp signal into an actual signal in a single-slope digital logic ADC circuit in a two-step high-speed ADC circuit based on a single-slope and level-coded TDC according to the present invention;

[0021] Figure 4 The figure is a schematic diagram showing the principle of the level coding method in the two-step high-speed ADC circuit based on the single-slope and level-coded TDC of the present invention. DETAILED DESCRIPTION

[0022] The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0023] The present invention is based on a two-step high-speed ADC circuit of single slope and level coding TDC, such as Figure 2 As shown, it includes a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit;

[0024] The single-slope digital logic ADC circuit includes a comparator CMP1 and a digital logic circuit connected to an output C of the comparator CMP1, which together constitute the single-slope digital logic ADC circuit.

[0025] The digital logic circuit includes an inverter inv1, an AND gate AND, a counter COUNTER with a configurable initial value function, and control signals clk_sam and ramp_L for cooperating with digital correlated double sampling.

[0026] clk_sam is connected to the D terminal of flip-flop DFF1, ramp_L is connected to the input of inverter inv1, and ramp_H is the reset terminal of the counter. The Q terminal of DFF1 and the output of inverter inv1 are connected to the input of AND gate AND. The output of AND gate AND is connected to counter COUNTER. Counter COUNTER's output N2 is the actual conversion result after correlated double sampling by the single-slope digital logic ADC circuit. Ramp_H is the reset terminal of COUNTER.

[0027] The present invention uses a digital logic circuit to shape the comparator output and coordinates the control signals clk_sam and ramp_L of digital correlated double sampling to achieve analog-to-time-to-digital conversion in a single-slope architecture. The other output terminal, START, of the comparator CMP1 is connected to a time-controlled digital converter (TDC) circuit. The TDC encoding logic completes time-to-digital conversion compatible with single-slope ADC correlated double sampling within the last clock cycle of the A / D conversion. Finally, an accumulator sums the digital conversion results, achieving high-speed, high-precision analog-to-digital conversion.

[0028] The time-to-digital conversion (TDC) circuit for achieving correlated double sampling compatibility includes D flip-flops DFF2 and DFF3, an exclusive-OR gate (XOR), inverters inv2 and inv3, and a delay-locked loop (DLL) for generating stable delayed clocks CLK1 and CLK2. CLK1 and CLK2 are connected to the inputs of the exclusive-OR gate (XOR), the output of which is connected to the input of inverter inv2. The output of inv2 is connected to the D input of flip-flop DFF2, and DFF2's output, Y0, serves as the least significant bit of the correlated double sampling (CDS) counter logic.

[0029] CLK1 is also connected to the input of inverter inv3. The output of inv3 is connected to the input D of DFF3. DFF3's output Y1 serves as the second-lowest bit of the correlated double sampling counter logic. Y0, Y1, and the output N2 of the counter COUNTER are added to the accumulator to produce the analog-to-digital conversion result OUT.

[0030] The ADC's correlated double sampling operating cycle is divided into common-mode signal conversion and actual signal conversion. The common-mode signal conversion is achieved by the small slope in the ramp signal, and the actual signal conversion is achieved by the main slope of the ramp signal. Figure 3As shown, the input signal Vsig and the ramp signal Vramp are connected to the ADC. It is worth noting that VIN and Vcm are the actual quantization signal and common-mode signal contained in Vsig. Before quantization begins, the ramp_H signal resets the counter, which, in conjunction with the initial value port, resets the counter and sets the initial value. The ramp signal then begins operation. Within the timing constraints of the three signals, the comparator flips twice. The comparator logic integrates the pulse width, which is then quantized by the counter. This double quantization completes a digital correlated double sampling (DCDS) operation. Simultaneously, the comparator's two input ports are set near the common-mode level Vcm during the comparison. This achieves correlated double sampling while eliminating the impact of comparator offset voltage on quantization. During the DCDS operation, the initial state of the counter is set to quantize the time period between the two actual comparator flips, avoiding the additional computation required for subtraction in the digital domain.

[0031] The time difference quantization technology proposed in the present invention abandons the traditional clock edge encoding method using four clocks and adopts a new level encoding method. The principle diagram of the level encoding method is shown in FIG. Figure 4 As shown:

[0032] The delay-locked loop (DLL) provides two clocks, CLK1 and CLK2. Utilizing the phase difference between these two clocks, CLK1 and CLK2 have different high and low level combinations at different quantization moments within a clock cycle. These are then encoded through a level encoding circuit consisting of DFF2, DFF3, inv2, inv3, and XOR. Within a clock cycle, the 2-bit binary digital conversion results Y0 and Y1, ranging from 00 to 11, are output.

[0033] The present invention combines ADC with time sharing technology and TDC technology, greatly compressing the quantization time consumption of a single-slope analog-to-digital conversion circuit, and providing a solution for high-speed and high-precision column-level quantization of high-performance CMOS image sensors.

Claims

1. A two-step high-speed ADC circuit based on a single-slope and level-coded TDC, characterized by: It includes a single-slope digital logic ADC circuit and a time-to-digital conversion TDC circuit. The output of the single-slope digital logic circuit and the output of the time-to-digital conversion TDC circuit are output as an analog-to-digital conversion result OUT of the entire circuit through an accumulator. The single-slope digital logic ADC circuit includes a comparator CMP1, an output terminal C of the comparator CMP1 is connected to the digital logic circuit, and another output terminal START of the comparator CMP1 is connected to the time-to-digital conversion TDC circuit; The digital logic circuit includes a trigger DFF1, a D terminal of the trigger DFF1 is connected to a control signal clk_sam, and a CLK terminal of the trigger DFF1 is connected to an output terminal C of a comparator CMP1; The inverter inv1 is further provided with an input terminal connected to a control signal ramp_L, an output terminal of the inverter inv1 and a Q terminal of a flip-flop DFF1 are connected to an input terminal of an AND gate AND, an output terminal of the AND gate AND is connected to an input terminal of a counter COUNTER, and an output N2 of the counter COUNTER outputs an actual conversion result after double sampling by a single-slope digital logic ADC circuit; The time-to-digital conversion (TDC) circuit includes a DLL capable of generating delayed clocks CLK1 and CLK2. CLK1 and CLK2 are connected to the input of an exclusive-OR gate XOR. The output of XOR is connected to the input of an inverter inv2. The output of the inverter inv2 is connected to the input D of a flip-flop DFF2. The output Y0 of the flip-flop DFF2 serves as the lowest bit of the correlated double sampling counting logic. The CLK terminal of the flip-flop DFF2 is connected to the output START of the comparator CMP1. The CLK1 is connected to the input of the inverter inv3, the output of the inverter inv3 is connected to the input D of the trigger DFF3, and the CLK terminal of the trigger DFF3 is connected to the output START of the comparator CMP1; the output Y1 of the trigger DFF3 is used as the second lowest bit of the correlated double sampling counting logic; The output N2 of the counter COUNTER, the output Y0 of the flip-flop DFF2 and the output Y1 of the flip-flop DFF3 are output through the accumulator as the result OUT of analog-to-digital conversion of the entire circuit.

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