Composite wiring board, semiconductor device, and manufacturing method of composite wiring board

Abstract

This invention provides a composite wiring substrate capable of suppressing cracks near a bonding material, a semiconductor device, and a method for manufacturing the composite wiring substrate. The composite wiring substrate comprises: a first wiring substrate having a first connection terminal, a second wiring substrate having a second connection terminal opposite to the first connection terminal, and a bonding material for bonding the first connection terminal and the second connection terminal. In plan view, a first profile of the first connection terminal is located inside a second profile of the second connection terminal. The bonding material comprises: a first portion formed of an intermetallic compound of Cu and Sn in contact with both the first and second connection terminals; and a second portion formed of an alloy of Bi and Sn, including the portion between the first and second profiles in plan view. The second portion contains Bi at a high concentration compared to the eutectic composition of the SnBi alloy. The second portion is separate from the second connection terminal.

Description

Technical Field

[0001] This disclosure relates to composite wiring substrates, semiconductor devices, and methods for manufacturing composite wiring substrates. Background Technology

[0002] A composite wiring board with an interposer mounted on a multilayer substrate has been disclosed (Patent Document 1). Furthermore, tin-bismuth (SnBi) alloys are known as solders (Patent Documents 2 and 3).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: Japanese Patent Application Publication No. 2020-205331

[0006] Patent Document 2: Japanese Patent Application Publication No. 2010-3878

[0007] Patent Document 3: Japanese Patent Application Publication No. 2011-96900 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] While the composite wiring substrate described in Patent Document 1 achieves the desired purpose, there is a concern that cracks may occur near the bonding material between the laminated substrate and the interposer.

[0010] The purpose of this disclosure is to provide a composite wiring substrate, a semiconductor device, and a method for manufacturing the composite wiring substrate, which can suppress cracks near the bonding material.

[0011] Methods for solving problems

[0012] According to one aspect of this disclosure, a composite wiring substrate is provided, comprising: a first wiring substrate having a first connection terminal, a second wiring substrate having a second connection terminal opposite to the first connection terminal, and a bonding material for joining the first connection terminal and the second connection terminal. In plan view, a first profile of the first connection terminal is located inside a second profile of the second connection terminal. The bonding material comprises: a first portion formed of an intermetallic compound of Cu and Sn that contacts both the first and second connection terminals; and a second portion formed of an alloy of Bi and Sn, including the portion between the first and second profiles in plan view. The second portion contains Bi at a high concentration compared to the eutectic composition of the SnBi alloy. The second portion is separate from the second connection terminal.

[0013] The effects of the invention

[0014] According to the disclosed technology, it is possible to suppress cracks near the bonding material. Attached Figure Description

[0015] Figure 1 This is a cross-sectional view showing the composite wiring substrate according to the first embodiment.

[0016] Figure 2 This is a diagram showing the positional relationship between the electrode pads, bonding material, and electrode pads in the first embodiment.

[0017] Figure 3 A cross-sectional view (1) showing the manufacturing method of the composite wiring board according to the first embodiment.

[0018] Figure 4 A cross-sectional view (2) showing the manufacturing method of the composite wiring board according to the first embodiment.

[0019] Figure 5 This is a cross-sectional view (3) showing the manufacturing method of the composite wiring board according to the first embodiment.

[0020] Figure 6 This is a cross-sectional view (4) showing the manufacturing method of the composite wiring board according to the first embodiment.

[0021] Figure 7 A cross-sectional view (5) showing the manufacturing method of the composite wiring board according to the first embodiment.

[0022] Figure 8 This is a diagram showing the positional relationship between the electrode pads, bonding material, and electrode pads in a modified example of the first embodiment.

[0023] Figure 9 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0024] Explanation of reference numerals in the attached figures:

[0025] 1 Composite wiring board

[0026] 2 Semiconductor devices

[0027] 20 Semiconductor chips

[0028] 100 build-up substrate

[0029] 124 electrode pads

[0030] 124A Outline

[0031] 200 interpolators

[0032] 211 Electrode pad

[0033] 211A Outline

[0034] 300 bonding material

[0035] 310 Part 1

[0036] 311, 313 Cu3Sn layers

[0037] 312 Cu6Sn5 layer

[0038] 314 particles

[0039] 320 Part 2 Detailed Implementation

[0040] Hereinafter, the implementation method will be described with reference to the appendix. Figure 1 The following details will be provided. Furthermore, in this specification and accompanying drawings, elements that substantially have the same function are sometimes referred to by the same symbol to omit repetitive descriptions.

[0041] (First Embodiment)

[0042] The first embodiment relates to a composite wiring substrate and a method for manufacturing the same.

[0043] [Structure of Composite Wiring Board]

[0044] First, the structure of the composite wiring substrate according to the first embodiment will be described. Figure 1 This is a cross-sectional view showing the composite wiring substrate according to the first embodiment.

[0045] The composite wiring board 1 according to the first embodiment includes a multilayer substrate 100, an inserter 200, and a bonding material 300. In this disclosure, for convenience, the direction in which the inserter 200 is located when viewed from the multilayer substrate 100 is defined as upward, and the opposite direction is defined as downward. Furthermore, "top view" refers to viewing an object from a direction perpendicular to the top surface of the multilayer substrate 100. However, the composite wiring board can be used in an upside-down state, and also in any orientation.

[0046] For example, the multilayer substrate 100 has a core layer 110, a multilayer layer 120 disposed on top of the core layer 110, and a multilayer layer 130 disposed below the core layer 110. The multilayer substrate 100 is an example of a first wiring substrate.

[0047] The core layer 110 has an insulating substrate 111 with through holes 111x, a through conductive hole 112 formed on the inner wall of the through hole 111x, and a filler material 113 filling the inner side of the through conductive hole 112.

[0048] The multilayer 120 includes an insulating layer 121, a wiring layer 122, and a solder resist layer 123. The wiring layer 122 includes electrode pads 124 on top of the insulating layer 121. The wiring layer 122 is made of a conductor, such as copper. The electrode pads 124 are used as connection terminals when the multilayer substrate 100 is bonded to the interposer 200. The electrode pads 124 are an example of a first connection terminal.

[0049] The multilayer 130 includes an insulating layer 131, a wiring layer 132, and a solder resist layer 133. The wiring layer 132 includes electrode pads 134 beneath the insulating layer 131. The wiring layer 132 is made of a conductive material such as copper. The electrode pads 134 serve as connection terminals when the multilayer substrate 100 is bonded to external components such as a motherboard.

[0050] Electrode pads 124 and 134 are electrically connected via wiring layer 122, through-hole via 112, and wiring layer 132. The number of insulating layers 121 and wiring layers 122 included in the stacked layer 120 and the number of insulating layers 131 and wiring layers 132 included in the stacked layer 130 are not particularly limited.

[0051] The interposer 200, for example, has a first wiring structure 210 and a second wiring structure 220 disposed on the first wiring structure 210. The interposer 200 is an example of a second wiring substrate.

[0052] The first wiring structure 210 has electrode pads 211, an insulating layer 212, and conductive vias 213.

[0053] Electrode pads 211 are embedded in insulating layer 212. The underside of insulating layer 212 is planar with the underside of electrode pads 211. The sides of electrode pads 211 are covered by insulating layer 212. Through-holes 212x are formed in insulating layer 212, extending from the top of insulating layer 212 to the top of electrode pads 211. Conductive vias 213 are disposed within through-holes 212x. Conductive vias 213 contact electrode pads 211. The top surface of insulating layer 212 is planar with the top surface of conductive vias 213. The electrode pads 211 and conductive vias 213 are made of conductive materials such as copper. Electrode pads 211 are used as connection terminals when interposers 200 are bonded to multilayer substrates 100. Electrode pads 211 are an example of a second connection terminal.

[0054] The second wiring structure 220 has an insulating layer 221 and a wiring layer 222. A portion of the wiring layer 222 is in contact with a conductive via 213. The wiring layer 222 includes electrode pads 224 on top of the insulating layer 221. The insulating layer 221 is made of, for example, an organic resin. The wiring layer 222 is made of, for example, a conductor such as copper. The electrode pads 224 are used as connection terminals when mounting semiconductor chips. The number of insulating layers 221 and wiring layers 222 included in the second wiring structure 220 is not particularly limited.

[0055] The bonding material 300 bonds the electrode pads 124 of the multilayer substrate 100 to the electrode pads 211 of the interposer 200. Here, the configuration of the bonding material 300 will be described in detail. Figure 2 A diagram showing the positional relationship between electrode pad 124, bonding material 300, and electrode pad 211. Figure 2 (a) is a view of electrode pad 124, bonding material 300 and electrode pad 211 from below. Figure 2 (b) is a cross-sectional view showing electrode pad 124, bonding material 300 and electrode pad 211. Figure 2 (b) is equivalent to Figure 1 A magnified view of region R in the image.

[0056] For example, electrode pad 124 has a circular planar shape with a diameter of 90 μm, and electrode pad 211 has a circular planar shape with a diameter of 150 μm. When viewed from above, the center of electrode pad 211 is approximately aligned with the center of electrode pad 124. Therefore, when viewed from above, the outline 124A of electrode pad 124 becomes the inner side of the outline 211A of electrode pad 211. Outline 124A is an example of a first outline, and outline 211A is an example of a second outline.

[0057] The bonding material 300 has a first part 310 formed of an intermetallic compound of Cu and Sn and a second part 320 formed of an alloy of Bi and Sn.

[0058] Part 310 is in contact with both the electrode pads 124 of the multilayer substrate 100 and the electrode pads 211 of the interposer 200. Part 310, for example, has a Cu3Sn layer 311, a Cu6Sn5 layer 312, and a Cu3Sn layer 313. The Cu3Sn layer 311 covers the surface of the electrode pad 124, and the Cu3Sn layer 313 covers the surface of the electrode pad 211. The Cu6Sn5 layer 312 is located between the Cu3Sn layer 311 and the Cu3Sn layer 313. The Cu6Sn5 layer 312 is formed such that it covers the side (bottom) of the multilayer substrate 100 on which the Cu3Sn layer 313 is located. The Cu6Sn5 layer 312 can be in contact with the multilayer layer 120. Bi particles 314 can be dispersed in the Cu6Sn5 layer 312. The first part 310 can be connected to the top of the insulating layer 121, the Cu3Sn layer 311 can cover the top and sides of the electrode pad 124, the Cu3Sn layer 313 can cover the bottom of the electrode pad 211, and the Cu6Sn5 layer 312 can be connected to the insulating layer 121.

[0059] The second portion 320 includes the portion between the outline 124A of the electrode pad 124 and the outline 211A of the electrode pad 211 when viewed from above. The second portion 320 is formed circumferentially around the electrode pad 124. The second portion 320 has a first portion 310 between the second portion 320 and the electrode pad 124. The second portion 320 contains Bi at a high concentration compared to the eutectic composition of the SnBi alloy (eutectic SnBi alloy). For example, the proportion of Bi in the second portion 320 is 30% by mass or more and 85% by mass or less, preferably 40% by mass or more and 75% by mass or less. For example, the melting point of the second portion 320 is lower than the temperature of the second portion 320 when the semiconductor chip is mounted on the interposer 200. The melting point of the second portion 320 is preferably 240°C or less, more preferably 230°C or less, and even more preferably 220°C or less. The second portion 320 may contain unavoidable impurities. The second portion 320 is in contact with the Cu6Sn5 layer 312. The second portion 320 is separated from the electrode pad 211 by the first portion 310, and the second portion 320 does not directly contact the electrode pad 211. Furthermore, the second portion 320 is also separated from the electrode pad 124 by the first portion 310, and the second portion 320 does not directly contact the electrode pad 124. The first portion 310 is located between the second portion 320 and the side of the electrode pad 124, and the second portion 320 is connected to the top of the insulating layer 121.

[0060] An adhesive layer 400 is provided between the multilayer substrate 100 and the inserter 200 to bond the multilayer substrate 100 and the inserter 200 to each other. The adhesive layer 400 uses, for example, epoxy resin as the main agent. The adhesive layer 400 may cover a portion of the side surface of the inserter 200.

[0061] In the composite wiring substrate 1 according to the first embodiment, the bonding material 300 includes a first portion 310 formed of an intermetallic compound of Cu and Sn. Therefore, the first portion 310 has excellent rigidity. Furthermore, the melting point of the Cu3Sn layer 311 and Cu3Sn layer 313 included in the first portion 310 is 676°C, and the melting point of the Cu6Sn5 layer 312 included in the first portion 310 is 435°C. A semiconductor chip is mounted on the interposer 200, but the temperature of the bonding material 300 during mounting is set to about 250°C, which is more than 100°C lower than the melting point of the first portion 310. Therefore, the first portion 310 is thermally stable during mounting. That is, the bonding material 300 can also stably maintain high rigidity through heating during mounting.

[0062] Furthermore, the bonding material 300 comprises a second portion 320 formed of an alloy of Bi and Sn (a non-eutectic alloy) with a high concentration of Bi compared to the eutectic composition of a SnBi alloy. Therefore, the second portion 320 exhibits excellent toughness. Additionally, the second portion 320 includes the portion between the outline 124A of the electrode pad 124 and the outline 211A of the electrode pad 211. As described above, if the temperature of the bonding material 300 during semiconductor chip mounting is set to approximately 250°C, the second portion 320 melts or softens. Therefore, during mounting, when stress is applied to the bonding material 300, the second portion 320 preferentially undergoes elastic deformation, mitigating the stress concentration in the first portion 310.

[0063] Therefore, according to the first embodiment, cracks near the bonding material 300 can be suppressed.

[0064] Furthermore, during the mounting of semiconductor chips, there is a significant difference in the amount of thermal deformation between the multilayer substrate 100 and the interposer 200 in the direction perpendicular to the thickness direction (in-plane direction), but the thermal stress associated with this difference can be mitigated by the second part 320.

[0065] Furthermore, the second portion 320, formed of an alloy of Bi and Sn, is separate from and does not contact the electrode pad 211. Near the electrode pad 211, a first portion 310, formed of a thermally stable intermetallic compound of Cu and Sn, is formed. Therefore, while the electrode pad 211 is significantly affected by heat during semiconductor chip mounting, the bonding material 300 maintains excellent thermal stability.

[0066] Furthermore, the distance between electrode pad 124 and electrode pad 211 is preferably 6 μm or less. This is because if the distance exceeds 6 μm, there is a concern that it may be difficult to make contact between the first portion 310 and either electrode pad 124 or electrode pad 211. Moreover, this distance is more preferably 3 μm or less. If this distance is 3 μm or less, almost the entire portion of the bonding material 300 located inside the outline 124A of the electrode pad 124 when viewed from above can be constituted by the first portion 310, which can achieve particularly excellent thermal stability. For example, in the portion of the bonding material 300 located inside the outline 124A of the electrode pad 124 when viewed from above, the proportion of Bi is preferably 5% by mass or less, more preferably 3% by mass or less, and even more preferably 1% by mass or less.

[0067] Furthermore, the volume of the portion of the bonding material 300 located inside the outline 124A of the electrode pad 124 when viewed from above is preferably 50% or less, more preferably 40% or less, and even more preferably 30% or less.

[0068] [Manufacturing method of composite wiring board]

[0069] Next, the manufacturing method of the composite wiring board 1 according to the first embodiment will be described. Figures 3-7 This is a cross-sectional view showing the manufacturing method of the composite wiring board 1 according to the first embodiment.

[0070] First, such as Figure 3 As shown in (a), SnBi solder material 350 is disposed below the electrode pad 211 of the interposer 200. For example, the height of SnBi solder material 350 is about 15 μm to 20 μm. As the material of SnBi solder material 350, it is preferable to use a SnBi alloy with a lower proportion of Bi compared to the eutectic composition of the SnBi alloy. For example, the proportion of Bi in SnBi solder material 350 is 30% to 58% by mass, preferably 30% to 45% by mass. The melting point of SnBi solder material 350 is, for example, about 140°C. SnBi solder material 350 is an example of a first bonding material.

[0071] Next, as Figure 3 As shown in (b), an adhesive 410 coated with SnBi solder material 350 is formed on the underside of the insert 200. As the adhesive 410, NCF (non-conductive film) with epoxy resin as the main component can be used, for example.

[0072] In addition, such as Figure 4 As shown, separately prepare a multilayer substrate 100.

[0073] Moreover, such as Figure 5 As shown, while aligning electrode pads 211 and 124, the inserter 200, to which adhesive 410 is formed, is placed on the multilayer substrate 100. At this time, the temperature of the SnBi solder 350 is lower than its melting point. For example, the temperature of the SnBi solder 350 is approximately 60°C to 80°C. Furthermore, by applying a load of less than 0.1 MPa between the multilayer substrate 100 and the inserter 200, the inserter 200 is temporarily fixed to the multilayer substrate 100. The load application time is set to, for example, approximately 2 seconds.

[0074] Next, as Figure 6 As shown, the interposer 200 is temporarily pressed onto the multilayer substrate 100. Specifically, a load of approximately 10 MPa to 20 MPa is applied between the multilayer substrate 100 and the interposer 200, thereby compressing and deforming the SnBi solder material 350. At this time, in order to make the SnBi solder material 350 easy to soften and deform, the temperature of the SnBi solder material 350 is set to a relatively high temperature that is below its melting point. For example, the temperature of the SnBi solder material 350 is set to approximately 100°C to 120°C. For example, the distance between the electrode pad 124 and the electrode pad 211 after temporary pressing is preferably 6 μm or less, more preferably 3 μm or less. Due to the compression and deformation of the SnBi solder material 350, the distance between the multilayer substrate 100 and the interposer 200 decreases, and the adhesive 410 overflows to the outside of the interposer 200 when viewed from above. The overflowing adhesive 410 climbs up the side of the inserter 200 due to surface tension, covering a portion of the side of the inserter 200. The load is applied for, for example, about 60 seconds.

[0075] Then, as Figure 7As shown, the interposer 200 is formally pressed onto the multilayer substrate 100. Specifically, while applying a load of approximately 0.2 MPa to 0.6 MPa between the multilayer substrate 100 and the interposer 200, the temperature of the SnBi solder 350 is increased to a temperature higher than its melting point. For example, the temperature of the SnBi solder 350 is approximately 180°C. As a result, the SnBi solder 350 melts. Furthermore, the Sn contained in the SnBi solder 350 reacts with the Cu contained in the electrode pads 124 and 211, and a first portion 310 containing a Cu3Sn layer 311, a Cu6Sn5 layer 312, and a Cu3Sn layer 313 is formed near the electrode pads 124 and 211. Furthermore, along with the formation of Cu3Sn layer 311, Cu6Sn5 layer 312, and Cu3Sn layer 313, a second portion 320 with a higher Bi content compared to SnBi solder material 350 is formed, separating from electrode pads 124 and 211. Further, during the actual pressing process, the adhesive 410 is also heated and cured to form adhesive layer 400. The load application time is set to, for example, approximately 180 seconds.

[0076] Then, the application of load and heating are stopped. As a result, part 1 310 and part 2 320 solidify to form the joint 300.

[0077] This operation enables the manufacture of the composite wiring substrate 1 according to the first embodiment.

[0078] In addition, such as Figure 8 As shown, the portion between the electrode pad 124 of the first part 310 and the second part 320 can be extremely thin compared to the portion between the electrode pad 211 of the first part 310 and the second part 320. For example, when a surface treatment including Ni plating is performed on the surface of the electrode pad 124, the portion between the electrode pad 124 of the first part 310 and the second part 320 is easily thinned. Figure 8 A cross-sectional view showing the positional relationship between electrode pad 124, bonding material 300 and electrode pad 211 in a modified example of the first embodiment.

[0079] (Second Implementation)

[0080] Next, the second embodiment will be described. The second embodiment relates to a semiconductor device. Figure 9 This is a cross-sectional view showing the semiconductor device according to the second embodiment.

[0081] In the semiconductor device 2 according to the second embodiment, a semiconductor chip 20 is mounted on the inserter 200 of the composite wiring substrate 1 according to the first embodiment. That is, the connection terminals (not shown) provided on the semiconductor chip 20 are connected to the electrode pads 224 by bonding materials (not shown) such as solder. The semiconductor chip 20 is mounted, for example, by reflow at a temperature of 250°C. During mounting, the semiconductor chip 20 can be pressurized toward the composite wiring substrate 1.

[0082] The preferred embodiments have been described in detail above, but are not limited to the above embodiments. Various modifications and substitutions can be made to the above embodiments without departing from the scope of the claims.

Claims

1. A composite wiring board, characterized in that, have: A first wiring board having a first connection terminal, A second wiring board having a second connection terminal opposite to the first connection terminal, and A bonding material for joining the first connecting terminal and the second connecting terminal. Viewed from above, the first contour of the first connecting terminal is located inside the second contour of the second connecting terminal. The bonding material has: Part 1, which contacts both the first and second connecting terminals, is formed of an intermetallic compound of Cu and Sn. Part 2, which includes the portion between the first profile and the second profile when viewed from above, is formed of an alloy of Bi and Sn. The second part contains Bi at a high concentration compared to the eutectic composition of the SnBi alloy. The second part is separate from the second connecting terminal.

2. The composite wiring substrate according to claim 1, characterized in that, The first wiring substrate is a multilayer substrate. The second wiring board is an interposer.

3. The composite wiring substrate according to claim 1 or 2, characterized in that, The entire surface of the second connecting terminal opposite the first connecting terminal is covered by the first portion.

4. The composite wiring substrate according to claim 1 or 2, characterized in that, The proportion of Bi in the second part is higher than the proportion of Bi in the eutectic composition of the SnBi alloy, and is less than 75% by mass.

5. The composite wiring substrate according to claim 1 or 2, characterized in that, The distance between the first connecting terminal and the second connecting terminal is less than 6 μm.

6. The composite wiring substrate according to claim 5, characterized in that, The distance between the first connecting terminal and the second connecting terminal is less than 3 μm.

7. The composite wiring board according to claim 1 or 2, characterized in that, The volume of the portion of the bonding material located inside the first contour when viewed from above is: The portion of the bonding material located outside the first profile in a top view comprises less than 50% of its volume.

8. The composite wiring substrate according to claim 1 or 2, characterized in that, The second portion is formed in a ring around the first connection terminal.

9. The composite wiring substrate according to claim 1 or 2, characterized in that, The second wiring board has an insulating layer covering the side of the second connection terminal.

10. The composite wiring substrate according to claim 1 or 2, characterized in that, The melting point of the second part is below 240°C.

11. The composite wiring substrate according to claim 1 or 2, characterized in that, In the portion of the bonding material located inside the first profile when viewed from above, the proportion of Bi is less than 5% by mass.

12. The composite wiring substrate according to claim 1 or 2, characterized in that, The first connection terminal is located on the side of the first wiring board that faces the second wiring board. The bonding material is electrically connected to the first connecting terminal and the second connecting terminal, and is in contact with the surface of the first wiring substrate that is opposite to the second wiring substrate.

13. The composite wiring substrate according to claim 1 or 2, characterized in that, The first part is located between the second part and the first connecting terminal to cover the side of the first connecting terminal.

14. A semiconductor device, characterized in that, have: The composite wiring substrate according to any one of claims 1 to 13, and Semiconductor chips mounted on the second wiring substrate.

15. A method for manufacturing a composite wiring board, characterized in that, It has the following processes: The process of preparing a first wiring board having a first connection terminal containing Cu. The process of preparing a second wiring board having a second connection terminal containing Cu. The process of setting a first bonding material containing Bi and Sn on the second connecting terminal. The process involves arranging the first wiring substrate and the second wiring substrate such that the second connecting terminal is opposite to the first connecting terminal, and the first bonding material is in contact with the first connecting terminal; heating the first bonding material to a temperature lower than its melting point; and simultaneously applying pressure between the first and second wiring substrates to compress and deform the first bonding material. A process involves heating the first bonding material to a temperature higher than its melting point while simultaneously applying a pressure weaker than that used in a process that compresses and deforms the first bonding material between the first wiring substrate and the second wiring substrate. This causes the first bonding material to react with the first and second connecting terminals, forming a bonding material that joins the first and second connecting terminals. Viewed from above, the first contour of the first connecting terminal is located inside the second contour of the second connecting terminal. The bonding material has: Part 1, which contacts both the first and second connecting terminals, is formed of an intermetallic compound of Cu and Sn. Part 2, which includes the portion between the first profile and the second profile when viewed from above, is formed of an alloy of Bi and Sn. The second part contains Bi at a high concentration compared to the eutectic composition of the SnBi alloy. The second part is separate from the second connecting terminal.

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