Enhanced semiconductor laser with spontaneous emission blocking

Abstract

A device and method for producing an enhanced laser (ATLAS) comprising a bistable resistor system (BRS) integrated in series with a semiconductor laser. By utilizing the abrupt resistance switch of the BRS, the laser exhibits a reduction / suppression of spontaneous emission (SE) below the laser threshold. The laser system comprises a semiconductor laser and a BRS operated as a reversible switch. The BRS operates in a high-resistance state, where the semiconductor laser is below the laser threshold and emits in a reduced spontaneous emission mechanism, and in a low-resistance state, where the semiconductor laser is above or equal to the laser threshold and emits in a stimulated emission mechanism. The BRS operated as a reversible switch is electrically connected in series across two separate chips or on a single wafer. The BRS is formed using an insulator-metal transition (IMT) material or is formed using a threshold switch selector (TSS).

Description

Technical Field

[0001] The present invention relates generally to semiconductor lasers and, more particularly, to semiconductor lasers having spontaneous emissions blockage. Background Art

[0002] Semiconductor lasers, such as conventional edge-emitting lasers, also called laser diodes or vertical-cavity surface-emitting lasers (VCSELs), are used commercially for a very wide range of applications: displays and lighting, data storage, communications, data reading, data recording, defense, laser printing, medical and cosmetic applications, material processing such as surface treatment, optical pump sources, etc.

[0003] When the electrical power is increased, a typical semiconductor laser will th ) to transition between two different states:

[0004] Spontaneous emission states occurring below threshold to produce coherent emission, random polarization, random phase, random emission direction, wide beamwidth; and

[0005] Stimulated emission regime occurring above a power threshold to produce laser operation characterized by coherent emission of light with identical photon energy, narrow linewidth, identical photon direction, identical photon phase or temporal coherence, and identical photon polarization or coherent polarized light. Summary of the invention

[0006] In one embodiment, a device and method for producing an enhanced laser (ATLAS) comprising a bistable resistor system (BRS) integrated in series with a semiconductor laser is shown. The ATLAS exhibits reduction / suppression of spontaneous emission (SE) below the laser threshold by utilizing abrupt resistance switching of the BRS.

[0007] In one embodiment, a laser system includes a semiconductor laser and a bistable resistance system (BRS) operated as a reversible switch. The BRS is electrically connected in series with the semiconductor laser. The BRS operates in a high-resistance state, where the semiconductor laser is below the laser threshold and emits with a spontaneous emission mechanism, and the BRS operates in a low-resistance state, where the semiconductor laser is above or equal to the laser threshold and emits with a stimulated emission mechanism. The BRS operated as a reversible switch is electrically connected in series across two independent chips or on a single wafer. The BRS is formed using an insulator-metal transition (IMT) material or is formed using a threshold switch selector (TSS).

[0008] In another embodiment, a vertical waveguide laser semiconductor device includes a semiconductor substrate and a layer structure formed thereon, wherein a quantization axis of an active dielectric layer is parallel to a vertical axis of an optical cavity. The layer structure includes: a first waveguide layer having a first doping type disposed above the semiconductor substrate, an active dielectric layer disposed above the first waveguide layer, and a second waveguide layer having a second doping type and an oxide layer disposed above the active dielectric layer. A mesa structure having a top surface and sidewalls is formed by the first waveguide layer. The active dielectric layer and the second waveguide layer and a hole formed in the second waveguide layer. A bistable resistor system (BRS) is: i) formed on the first waveguide layer around the mesa structure, or ii) formed on the top surface of the mesa structure.

[0009] In one embodiment, the layer structure is a vertical cavity surface emitting laser (VSCEL) and the BRS is formed using an insulator-metal transition (IMT) material or is formed using a threshold switch selector.

[0010] In another embodiment, a vertical waveguide laser semiconductor device includes a semiconductor substrate and a layer structure formed thereon, wherein the quantization axis of the active dielectric layer is parallel to the vertical axis of the optical cavity. The layer structure includes: a first waveguide layer having a first doping type disposed above the semiconductor substrate, an active dielectric layer disposed above the first waveguide layer, and a second waveguide layer having a second doping type and an oxide layer disposed above the active dielectric layer. A mesa-type structure having a top surface and a sidewall is formed by the first waveguide layer, the active dielectric layer, and the second waveguide layer, and a hole is formed in the second waveguide layer. A bistable resistor system (BRS) formed on the back side of a semiconductor substrate, wherein a first contact layer is formed above the bistable resistor system; and a second contact layer is formed above the second waveguide layer and has an opening above the hole, and the second contact layer is electrically isolated from the first contact layer. The bistable resistor system is formed using an insulator-metal transition (IMT) material or a threshold switch selector (TSS).

[0011] An edge emitting laser semiconductor device includes a semiconductor substrate and a layer structure formed thereon. The layer structure includes a first cladding layer having a first doping type disposed above the top side of the semiconductor substrate; a first waveguide layer disposed above the first cladding layer, an active dielectric layer having a plurality of quantum wells disposed above the first waveguide layer, a second waveguide layer disposed above the active dielectric layer, and a second cladding layer having a second doping type disposed above the second waveguide layer. A mesa structure having a top surface and sidewalls is formed by the second cladding layer. An oxide layer is formed on either side of the mesa structure. A bistable resistor system (BRS) is i) formed on the top surface of the mesa structure, wherein a first contact layer is formed on the bistable resistor system and a second contact layer is formed on the bottom side of the semiconductor substrate, or ii) formed on the back side of the semiconductor substrate, wherein a first contact layer is formed on the bistable resistor system and a second contact layer is formed on the top surface of the mesa structure. The bistable resistor system is formed using an insulator-metal transition (IMT) material or a threshold switch selector (TSS).

[0012] In another embodiment, a vertical waveguide laser semiconductor device includes a semiconductor substrate and a layer structure formed thereon, wherein the quantization axis of the active dielectric layer is parallel to the vertical axis of the optical cavity. The layer structure includes: a first waveguide layer having a first doping type disposed above the semiconductor substrate, an active dielectric layer disposed above the first waveguide layer, and a second waveguide layer having a second doping type and an oxide layer disposed above the active dielectric layer, wherein at least one layer of a bistable resistor system (BRS) is i) formed in the active dielectric layer, or ii) formed in the second waveguide layer; a mesa structure having a top surface and a sidewall is formed by the first waveguide layer, the active dielectric layer, and the second waveguide layer, and a hole is formed in the second waveguide layer. The bistable resistor system is formed using an insulator-metal transition (IMT) material or a threshold switch selector (TSS). In one example, the vertical waveguide laser is a vertical cavity surface emitting laser (VSCEL), and the bistable resistor system is formed using an insulator-metal transition (IMT) material or a threshold switch selector (TSS). BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The accompanying drawings are used to further illustrate various embodiments and to explain various principles and advantages according to the present invention, wherein like reference numerals represent the same or functionally similar elements throughout the individual views, and are incorporated into and form a part of the specification together with the following detailed description, wherein:

[0014] Figure 1 It shows that according to the prior art Figure 1 The basic operation of the laser is plotted against the pump current;

[0015] Figure 2 A graph showing current and voltage characteristics of a bistable resistor system according to the prior art;

[0016] Figure 3 is a graph of the output optical power and pump current of a classical laser according to the prior art;

[0017] Figure 4 is a graph of output optical power and pump current of an enhanced laser using a bistable system according to an embodiment of the present invention;

[0018] Figure 5A and Figure 5B is a diagrammatic representation of an enhanced laser reversibly switchable between an off-state and an on-state, respectively, associated with a high resistance state (HRS) and a low resistance state (LRS) of a bistable resistor system, respectively, according to one embodiment of the present invention;

[0019] Figure 6 is a series of graphs of output optical power versus pump current for various configurations of an enhanced laser having a bistable resistor system according to an embodiment of the present invention;

[0020] Figure 7 is a series of graphs of output optical power versus pump current for various configurations of an enhanced laser having a bi-stable resistor system according to an embodiment of the present invention, and Figure 6 This configuration exhibits small or nonexistent hysteresis compared to the hysteresis in ;

[0021] Figure 8 is a side view showing an initial stage of formation of a vertical cavity surface emitting laser semiconductor device with an integrated bistable resistor system according to one embodiment of the present invention;

[0022] Fig.9A is a top perspective view and Fig. 9B is a corresponding cross-sectional view taken along line XX', showing a formation of an embodiment according to the present invention Figure 8 A later stage of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated on a buried bottom contact;

[0023] Fig.10 is a cross-sectional view taken along line XX', showing a formation of an embodiment according to the present invention Figure 8 A later stage of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated on a top contact;

[0024] Fig.11 is a cross-sectional view taken along line XX', showing a formation of an embodiment according to the present invention Figure 8A later stage of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated on a back side contact;

[0025] Fig.12 is a flow chart illustrating one example of a process for forming a vertical cavity surface emitting laser semiconductor device with an integrated bistable resistor system according to one embodiment of the present invention;

[0026] Fig.13A It is a top perspective and Fig. 13B is a corresponding cross-sectional view taken along line XX', illustrating an initial stage of forming an edge-emitting semiconductor laser or diode device with an integrated bistable resistor system according to one embodiment of the present invention;

[0027] Fig.14A and Fig. 14B are schematic cross-sectional views taken along lines XX' and YY', respectively, showing a formation of a Fig. 13B A late stage of an edge emitting semiconductor laser or diode device having a bistable resistor system integrated on a top contact;

[0028] Fig.15 is a schematic cross-sectional view showing a formation method according to an embodiment of the present invention. Fig. 13B A late stage of an edge emitting semiconductor laser or diode device having a bistable resistor system integrated on a back side contact;

[0029] Fig.16 is a schematic side view showing a semiconductor laser device having a bistable resistor system integrated within the active medium of the laser according to one embodiment of the present invention;

[0030] Fig.17 is a schematic cross-sectional view taken along line XX', illustrating the formation of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated within the active medium of the device according to one embodiment of the present invention;

[0031] Fig.18 is a schematic side view showing a semiconductor laser device having a bistable resistor system integrated within a waveguide of a laser optical cavity according to one embodiment of the present invention;

[0032] Fig.19 is a schematic cross-sectional view taken along line XX', illustrating formation of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated within a waveguide of a laser optical cavity according to one embodiment of the present invention; and

[0033] Fig. 20is a flow chart illustrating one example of a process for forming a laser semiconductor device having a bistable resistor system within the active medium or waveguide of the laser according to one embodiment of the present invention. DETAILED DESCRIPTION

[0034] Non-limiting review of semiconductor device descriptions

[0035] It should be understood that the various layers and / or regions shown in the drawings are not drawn to scale, and one or more layers and / or regions of a type commonly used in laser semiconductors and / or other semiconductor devices may not be explicitly shown in a given drawing. This does not mean that layers and / or regions that are not explicitly shown are omitted from the actual device. In addition, when the explanation does not necessarily focus on the omitted elements, certain elements may be omitted from a particular view for clarity and / or simplicity. In addition, the same or similar reference numerals used in all drawings are used to represent the same or similar features, elements, or structures, and therefore a detailed explanation of the same or similar features, elements, or structures will not be repeated for each drawing.

[0036] Semiconductor devices and methods of forming the same according to various embodiments of the present invention may be used in applications, hardware, and / or electronic systems. Suitable hardware and systems for implementing embodiments of the present invention may include, but are not limited to, personal computers, communication networks, e-commerce systems, portable communication devices (e.g., cellular phones and smart phones), solid-state media storage devices, functional circuit systems, etc. Systems and hardware incorporating semiconductor devices are contemplated embodiments of the present invention. Given the teachings of the embodiments of the present invention provided herein, one of ordinary skill in the art will be able to envision other implementations and applications of embodiments of the present invention.

[0037] As used herein, "vertical" refers to a direction perpendicular to the substrate in the view herein. As used herein, "horizontal" refers to a direction parallel to the view of the substrate in the present invention. As used herein, "thickness" refers to the dimension of an element (e.g., a layer, a groove, a hole, etc.) in a cross-sectional view measured from the bottom surface to the top surface of the element or from the left surface to the right surface, and / or the dimension measured relative to the surface on which the element is directly located.

[0038] Unless otherwise indicated, as used herein, "height" or "height above the substrate" refers to the vertical dimension of an element (e.g., a layer, a groove, a hole, etc.) in a cross-sectional view measured from the top surface of the substrate to the top surface of the element. If the element is directly on the substrate, the thickness of the element can be equal to the height of the element. As used herein, "lateral", "lateral edge", "lateral surface", etc. refer to the side surface of an element (e.g., a layer, an opening, a fin, etc.), such as the left side surface or the right side surface in a cross-sectional view herein.

[0039] As used herein, the term "width" or "width value" or the like refers to the distance from a starting point on a first structure to an end point on the same structure in a critical dimension. The vertical width (eg, thickness) of a structure or the horizontal width of a structure may be specified.

[0040] It should also be understood that when an element such as a layer, region or substrate is referred to as being "on" or "above" another element, it can be directly on another element, or there can also be an intermediate element. For an element such as a layer, region or substrate that is referred to as being "under" or "below" another element, similar but opposite meanings will be understood. It can be directly under other elements, or there can also be an intermediate element. On the contrary, when an element is referred to as being "directly on another element" or "directly above another element" or alternatively referred to as being "directly under another element" or "directly below another element", there is no intermediate element. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to another element, or there can be an intermediate element. On the contrary, when an element is referred to as being "directly connected" or "directly coupled" to another element, there is no intermediate element.

[0041] The present invention may include a design for an integrated circuit chip, which may be created in a graphical computer programming language and stored in a computer storage medium (such as a disk, tape, physical hard drive, or a virtual hard drive such as in a storage access network). If the designer does not manufacture the chip or the photolithography masks used to manufacture the chip, the designer may transmit the resulting design to such an entity directly or indirectly by physical means (e.g., by providing a copy of the storage medium storing the design) or electronically (e.g., via the Internet). The stored design is then converted to an appropriate format (e.g., GDSII) for manufacturing photolithography masks, which typically include multiple copies of the chip design in question to be formed on a wafer. Photolithography masks are used to define areas of the wafer (and / or layers thereon) to be etched or otherwise processed.

[0042] The method as described herein can be used for the manufacture of integrated circuit chips. The manufacturer can distribute the obtained integrated circuit chips in raw wafer form (i.e., as a single wafer with multiple unpackaged chips), as a bare chip, or in a packaged form. In the latter case, the chip is mounted in a single chip package (such as a plastic carrier with leads fixed to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with one or both of surface interconnects or buried interconnects). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of (a) an intermediate product (such as a motherboard) or (b) a final product. The final product can be any product including an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products with displays, keyboards or other input devices and central processing units.

[0043] References in the specification to "one embodiment" or "an embodiment" and other variations of the present principles mean that a particular feature, structure, characteristic, etc. described in connection with the embodiment is included in at least one embodiment of the present principles. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" and any other variations in various places throughout the specification are not necessarily all referring to the same embodiment.

[0044] It should be understood that the various layers and / or regions shown in the drawings are not drawn to scale, and one or more layers and / or regions of the semiconductor laser may not be explicitly shown in a given drawing. This does not mean that layers and / or regions that are not explicitly shown are omitted from the actual device. In addition, when the explanation does not necessarily focus on the omitted elements, certain elements may be omitted from a particular view for clarity and / or simplicity. In addition, the same or similar reference numerals used in all drawings are used to represent the same or similar features, elements or structures, and therefore the detailed explanation of the same or similar features, elements or structures will not be repeated for each drawing.

[0045] Deposition can be any process that transfers material to a wafer by growth, coating or other means. Available techniques include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE) and, more recently, atomic layer deposition (ALD).

[0046] The term "epitaxial growth" and its variations refer to the growth of a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has the same crystal properties as the semiconductor material of the deposition surface. In an epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set so that the deposited atoms arrive at the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Thus, the epitaxial semiconductor material has the same crystal properties as the deposition surface formed thereon. For example, an epitaxial semiconductor material deposited on a {100} crystal surface will exhibit a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is selective for formation on a semiconductor surface, and does not deposit material on a dielectric surface (such as a silicon dioxide or silicon nitride surface).

[0047] Examples of various epitaxial growth process equipment suitable for one or more embodiments include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE). Many different sources can be used for the deposition of the various layers discussed herein. For example, the gas source for the deposition of epitaxial semiconductor materials may include a silicon-containing gas source, a germanium-containing gas source, a combination thereof, and / or the like. Examples of silicon-containing gas sources are silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, and combinations thereof. Examples of germanium-containing gas sources are germane, digermane, halogenated germanes, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof.

[0048] Removal may be by any process that removes material from the wafer; examples include etching processes (wet or dry), reactive ion etching (RIE), and chemical mechanical planarization (CMP).

[0049] Patterning refers to the shaping or altering of deposited materials, and can often be referred to as photolithography by applying a patterned mask. For example, in conventional photolithography, a wafer is coated with a chemical called a photoresist; a machine called a stepper then focuses, aligns, and moves the mask, exposing selected portions of the wafer underneath to short-wavelength light; the exposed areas are washed away with a developer solution. After etching or other processing, the remaining photoresist can be removed by plasma ashing.

[0050] Changes in electrical properties have historically required doping the transistor source and drain (initially by diffusion furnaces and subsequently by ion implantation). These doping processes are followed by furnace annealing or rapid thermal annealing (RTA) in advanced equipment; annealing is used to activate the implanted dopants. Changes in electrical properties now also extend to the reduction of the dielectric constant of materials in low-k insulator trenches exposed to ultraviolet light in UV processes (UVP). Changes are usually achieved by oxidation, such as in local oxidation of silicon (LOCOS), which can be performed to produce a semiconductor-insulator junction to make metal oxide field effect transistors.

[0051] Overview of the reduction of spontaneous emission (SE)

[0052] As acknowledged by others including S. Noda et al., "SE control by photonic crystals and nanocavities," Nature Photonics 1, 449 (2007), spontaneous emission in lasers is problematic for several reasons.

[0053] The first reason is that spontaneous emission in lasers limits the performance of photonic devices in applications including lighting, displays, optical communications, solar energy, and quantum information systems.

[0054] The second reason why spontaneous emission in lasers as coherent light sources is problematic is noise. Spontaneous emission (SE) that is not coupled to the laser mode will increase the laser threshold and become unwanted noise. Therefore, there is a strong motivation to achieve control of SE and suppress it when it is not desired, or alternatively concentrate it into a useful form. In fact, controlling SE can be considered one of the most important goals in current photonics research. Controlling SE can bring important and significant improvements in device performance.

[0055] Various embodiments will now be discussed in more detail with respect to semiconductor devices and methods of fabricating the same, and in particular, with respect to fabrication methods and structures that use a bistable resistor system (BRS) to reduce or suppress spontaneous emission below the lasing threshold in semiconductor lasers.

[0056] The presently claimed invention exploits the unique properties of any system that exhibits a reversible and electrically triggered resistive switch between two stable resistive states with a single polar abrupt change.

[0057] The BRS used in the present invention includes:

[0058] i) Insulator-metal transition (IMT) materials such as relaxed, strained, 3D-bulk, thin film, 2D-nanosheet, 1D-nanowire based on: VO2, NbO2, Ca2RuO4, LaCoO3, Ti2O3, Ti3O5, SmNiO3, NdNiO3, V2O3, V4O7, Fe3O4 and any oxide of the form ABO3;

[0059] ii) Threshold Switch Selectors (TSS) are based on a combination of thin insulator layers and metals, such as: Ag / HfO2, Cu / HfO2, Ag / TiO2, CuxS, Ag / a-Si, AgTe / TiNTiO2 / TiN; and

[0060] iii) Any other material or combination of materials used in magnetic or resistive memory such as spin transfer torque structure (STT-MRAM), phase change memory (PCM), resistive memory (ReRAM) and equivalents.

[0061] BRS is integrated in series with semiconductor lasers (such as edge emitting lasers or laser diodes) and vertical cavity surface emitting lasers (VCSELs). BRS helps reduce / suppress SE below the laser threshold.

[0062] As described below, BRS can be integrated in various embodiments, including:

[0063] i) Electrically: through the electrical connection between the first circuit of the integrated BRS and the second circuit of the integrated semiconductor laser. This integration can be between the electrical connection of two independent chips with external wiring, or it can be the electrical connection of two chips integrated on the same wafer with integrated interconnection;

[0064] ii) Monolithic: e.g. on semiconductor lasers: inside contact vias, as part of a distributed Bragg reflector (DBR) or waveguide adjacent to the active medium, etc.

[0065] iii) Monolithic intracavity: in a node of static electromagnetic field to minimize light absorption (eg in VCSELs).

[0066] Basic Laser Operation Review

[0067] Figure 1 The basic operation of a laser according to the prior art is shown in a graph with respect to the pump current. A typical output optical power versus pump current (I) characteristic and the corresponding output spectrum of a laser diode. The threshold current I th It can be defined as the pump current level at which the output of the laser is dominated by stimulated emission rather than spontaneous emission. In a typical PI characteristic, the threshold current Ith It corresponds to the intersection of the extension of the coherent radiation output characteristic and the I axis.

[0068] A laser (light amplification by stimulated emission of radiation) system comprising an active medium placed in an optical resonant cavity (cavity). Energy is supplied to the laser medium by a pumping system. This energy is stored in the form of electrons trapped in metastable energy levels. The pumping must produce a population inversion, i.e., more atoms in the metastable state than in the ground state, before laser operation can occur.

[0069] When population inversion is achieved, a chain reaction begins with the spontaneous decay of some electrons from metastable levels to lower energy levels. This corresponds to Figure 1 The spontaneous emission portion 102 of the graph in corresponds to the graph of optical power versus wavelength 112 as shown.

[0070] Increasing the current moves the laser into the simulated multimode emission portion 104 and as shown, a graph of optical power versus wavelength 114 is plotted. The spontaneously emitted photons will strike (without being absorbed) other atoms and excite their electrons to transition from metastable levels to lower energy levels.

[0071] Further increasing the current in the analog multimode transmit section 104 results in Figure 1 The optical power is completely single-mode emission, and the emitted photons have exactly the same wavelength, phase and direction. A corresponding curve 116 of optical power versus wavelength is shown.

[0072] This action takes place in the optical cavity. When the photons that decay in the direction of the mirror (mostly lost) reach the end of the laser material, they are reflected back into the material, where the chain reaction continues and the number of photons increases. When the photons reach the partial reflector, only a portion will be reflected back into the cavity, and the rest will emerge as a laser beam.

[0073] Figure 2 A graph of current and voltage of a bistable resistor system (BRS) according to the prior art is shown. As shown, the BRS exhibits a reversible and electrically triggered resistor switch of a single polar mutation, or simply a reversible switch. The construction of the BRS system is as described above and includes IMT materials, TSS and other systems used in magnetic or resistive memory.

[0074] The horizontal axis represents the voltages V1 and V2 at the switching voltage thresholds. The vertical axis represents the current, where I OFF and I ON is the current level. The high resistivity insulation state (HRS) at V1 reduces the pump current (I OFF ), while the sudden resistance at V2 switching to the low resistivity metallic state (LRS) causes the on-state pump current (I ON) is negligible.

[0075] Figure 3 According to the above Figure 1 The output optical power and pump current of a conventional laser of the prior art are shown in FIG. Figure 3 The adjacent Figure 4 , which is a graph of output optical power versus pump current for an enhanced laser using BRS according to one embodiment of the claimed invention. Note that Figure 4 The slope of the curve is almost flat in the spontaneous emission region 402 until the BRS threshold current (I IMT ).and Figure 3 Compared to the slope of the curve in the spontaneous emission region 302, this corresponds to the off state of the enhanced laser, where the BRS is in an insulating high resistance state (i.e., HRS). In the off state, due to the large insulation resistance, the effective voltage across the laser is reduced due to the potential drop across the BRS. This reduces the effective pump current reaching the active medium of the laser, thereby reducing the voltage below the laser threshold (I th ) is the effective spontaneous emission. Figure 3 This mechanism results in a much smaller spontaneous emission region 402 than in a classical laser in FIG. As shown, the present invention significantly reduces or eliminates the spontaneous emission region 402. An optimal or properly designed enhanced laser design requires that the insulator-metal transition threshold current (I IMT ) is greater than the laser threshold current (I th ). Once the pump current reaches I IMT value, the BRS suddenly switches to a low resistance state (i.e., LRS), thereby suddenly increasing to reach the laser threshold (I th ) above the effective pump current of the active medium. The enhanced laser suddenly switches from the residual spontaneous emission mechanism (402) to the stimulated emission mechanism (406). The mechanism transition region (404) with no output optical power (OOP) originates from the abrupt resistance switch of the BRS and is the region where the laser cannot operate efficiently. Similarly, when the pump current is reduced back to I MIT When the value is reached, BRS suddenly switches back to the high impedance state (i.e. HRS), thereby suddenly decreasing to reach the laser threshold (I th ) below the effective pump current of the active medium. The enhanced laser abruptly switches from the stimulated emission mechanism (406) back to the residual spontaneous emission mechanism (402) when transitioning through the mechanism transition region (404). Figure 5A and Figure 5B The operating principle is further explained.

[0076] Figure 5A and Figure 5Bis a schematic diagram showing an enhanced laser device consisting of a BRS electrically integrated in series with a laser diode, which can be reversibly switched between an off state and an on state. Figure 5A In the off state, when the BRS is in the insulated high resistance state (HRS), the effective voltage across the laser (V LASER ) is reduced due to the potential drop across BRS, making V LASER =V BA -V BRS The large insulation resistance causes a potential drop across the BRS. This reduces the effective pump current reaching the active medium of the laser, thereby significantly reducing or eliminating the period below the laser threshold (I th )'s spontaneous emission.

[0077] refer to Figure 5B , the on state is when BRS is in the metal low resistance state (LRS), and the effective gate voltage of the laser is V LASER ≈V BA , because the potential drop across the BRS becomes negligible when the metallic state has multiple orders of magnitude lower resistance. Therefore, the on-state pumping current loss is negligible. A reversible resistive switch from HRS to LRS can be electrically triggered for both positive and negative voltage polarities.

[0078] Various configurations of laser current with BRS

[0079] Figure 6 is a series of graphs of output optical power versus pump current for various configurations of an enhanced laser having a bistable resistor system according to an embodiment of the present invention. More specifically, Figure 6 Four configurations are shown: i) optimal configuration; ii) suitable configuration; iii) suboptimal configuration; and iv) unsuitable configuration, as follows:

[0080] i) optimal configuration, where;

[0081] Optimize the BRS switching current relative to the laser threshold voltage;

[0082] The spontaneous emission region is suppressed for all pump currents.

[0083] Minimize the mechanism transition area;

[0084] The stimulated emission region is maximized and close to the lasing threshold; and

[0085] In this case, I MIT =I th IMT , where I th is the laser threshold current for lasing, I IMT ​is the insulator-metal current and I MIT is the metal-insulator current.

[0086] ii) a suitable configuration, wherein:

[0087] The spontaneous emission region is suppressed for all pump currents.

[0088] The mechanism transition area is large;

[0089] The stimulated emission region is not very close to the lasing threshold;

[0090] · requiring more energy to switch the BRS than is optimal; and

[0091] In this case I th <I MIT <I IMT .

[0092] iii) Suboptimal configuration, where:

[0093] Reduced accessible spontaneous emission area compared to conventional lasers;

[0094] When the laser is turned off, the stimulated emission regime is not completely suppressed: part of it is available for pump currents close to and below the lasing threshold; and

[0095] · partially exploit the benefits of BRS integration; and

[0096] In this case I MIT <I th <I IMT .

[0097] iv) unsuitable configuration, where

[0098] The accessible spontaneous emission area is not significantly reduced compared to conventional lasers;

[0099] Not taking advantage of the benefits of BRS integration; and

[0100] In this case I MIT <I IMT <I th .

[0101] Figure 7 is a series of graphs of output optical power versus pump current for various configurations of an enhanced laser having a bi-stable resistor system according to an embodiment of the present invention, and Figure 6 This configuration has less or no hysteresis compared to the hysteresis in . More specifically, Figure 7 Three configurations are shown: i) optimal configuration; ii) suitable configuration; and iii) unsuitable configuration, as follows:

[0102] i) Optimal configuration, where:

[0103] Optimize the BRS switching current relative to the laser threshold voltage;

[0104] The spontaneous emission region is suppressed for all pump currents.

[0105] Minimize the mechanism transition area;

[0106] The stimulated emission region is maximized and close to the lasing threshold; and

[0107] I IMT ≈I MIT =I th .

[0108] ii) Optimal configuration, where:

[0109] The spontaneous emission region is suppressed for all pump currents.

[0110] The mechanism transition area is large;

[0111] The stimulated emission region is not very close to the lasing threshold;

[0112] More energy is required to switch the BRS; and

[0113] In this case I th <I IMT ~I MIT .

[0114] iii) Unsuitable configuration, where:

[0115] The accessible spontaneous emission area is not significantly reduced compared to conventional lasers;

[0116] Not taking advantage of the benefits of BRS integration; and

[0117] In this case I IMT ≈I MIT <I th .

[0118] Example 1: Vertical waveguide semiconductor device with BRS having buried bottom contact

[0119] Figure 8 1 is a side view showing the initial stages of formation of a vertical cavity surface emitting laser (VCSEL) semiconductor device using a bistable resistor system (BRS) with a buried bottom contact according to one embodiment of the present invention. In this embodiment, a GaAs-based VCSEL with emission at about λ-980nm is given, however, other structures operating at different wavelengths are possible.

[0120] refer to Figure 8 , a VCSEL device is shown, which includes an n-type GaAs (n-GaAs) substrate 802, and a layer structure formed thereon by an epitaxial growth process, such as molecular beam epitaxy (MBE) and / or metal organic chemical vapor deposition (MOCVD). From the GaAs substrate 802, the layer structure continuously includes an n-type lower distributed Bragg reflector (DBR) layer or waveguide layer 804, an active layer or active medium layer 806 that may include a plurality of quantum wells, and a p-type upper DBR layer 810. The p-type upper DBR 810 includes an oxide layer 808. For simplicity, other optional layers such as cladding layers between the active medium 806 and the DBR layers 804 and 808 are not shown. The active medium 806 emits light by recombination of positive holes and electrons injected from the p-side electrode (shown) and the n-side electrode (not shown), respectively.

[0121] The n-type DBR layer 804 and the p-type DBR layer 810 include a plurality of layer pairs, each of which includes Al as a high reflectivity layer. x11 Ga 1-x11 and Al as a low reflectivity layer x12 Ga 1-x12 , where, for example, 0≤x11<1, 0<x12≤1, x11<x12, x11<x13<x12. The layer pair of DBR layers 804 and 810 allows the laser light (3-10x (InGaAs / GaAsP) generated in the active layer 806 to be emitted between the DBR layers 804 and 810 and pass through the upper DBR layer 810 as a laser beam with a desired output power. The upper DBR layer 810 has a top surface 812 as shown. The n-type DBR layer 804 may include dopants of GaAs: instead of As: Te, S and instead of Ga: Sn, Si, Ge, where mx (n-GaAs / n-AlAs). The p-type DBR layer 810 may include dopants of GaAs p-type dopants: instead of As: Si, Ge and instead of Ga: Zn, Cn and nx (p-GaAs / p-AlAs). Generally, m>n, so that the reflectivity of the bottom DBR layer 804 is close to 100%, while the reflectivity of the top DBR layer 810 is less than 100%.

[0122] Fig.9A is a top perspective view and Fig. 9B is a corresponding cross-sectional view taken along line XX', showing a formation of an embodiment according to the present invention Figure 8 A later stage of a vertical cavity surface emitting laser semiconductor device with a bistable resistor system integrated on a buried bottom contact.

[0123] exist Fig. 9BIn the figure, a combination of photolithography, anisotropic etching, and an organic planarization layer (OPL) (not shown) is used to selectively etch the p-type DBR layer 810, the active dielectric layer 806, the oxide layer 808, and the n-type DBR 804 to form a mesa structure 920 as shown.

[0124] As shown, a selective oxidation process is used to form holes 922 by forming oxide 924 in oxide layer 808. A dielectric layer 950, such as silicon boron carbon nitride (SiBCN), is conformally deposited over the top surface and sides of mesa structure 920 and over n-type DBR 804. A bottom contact layer well 960 is formed using OPL (not shown), photolithographic patterning, and anisotropic etching.

[0125] The OPL is removed using an ashing process (not shown). A conformal multilayer BRS 952 is deposited, followed by photolithography and dielectric etch back to form the structure as shown on the dielectric layer 952 and the contact layer well 960. In this example, the BRS is a threshold switch selector (TSS), such as, for example: Ag / HfO2, Cu / HfO2, Ag / TiO2. It is important to note that although the integration of a multilayer TSS is described, an insulator-metal transition (IMT) material or other bistable resistor system may be implemented instead.

[0126] A bottom contact layer 954 such as Ti / Au is formed using a metal deposition technique on top of the vertical and horizontal portions of the BRS layer 952 included within the contact layer well 960. Next, after TSS chamfering using the formed bottom metal contact layer, a selective recess of the bottom metal contact layer is performed.

[0127] An upper metal contact layer 926 is formed over the top horizontal portion of the p-type top DBR layer 810 using sequential metal deposition, photolithographic patterning, and metal etching techniques. A SiN layer 956 is formed on the sidewalls of the mesa structure 920 and over the bottom contact layer 954 using conformal dielectric deposition. As shown, after the dielectric layer 950 is formed, a portion of the bottom contact layer farthest from the mesa structure 920 is exposed. Photolithographic patterning (not shown) using OPL and a selective dielectric etch back as shown are used to form the structure.

[0128] A top contact layer 958 is formed over the upper contact layer 926 using sequential metal deposition, photolithography patterning, and metal etching techniques. As shown, after the dielectric layer 950 is formed, a portion of the bottom contact layer 954 and the dielectric layer 950 farthest from the mesa structure 920 are exposed. The top contact layer 958 is electrically isolated from the bottom contact layer 954. The quantization axis 980 is shown parallel to the optical cavity defined by the mesa structure 920.

[0129] Example 2: Vertical waveguide semiconductor device with top-contacted BRS

[0130] Fig.10 is a side view showing a vertical cavity surface emitting laser semiconductor device using a bistable resistor system integrated on a top contact according to another embodiment of the present invention. Figures 8 to 9A The process flow is such that the BRS layer 952 is no longer formed.

[0131] In this embodiment, a BRS layer 982 is formed using sequential metal deposition, photolithography patterning, and etching techniques prior to forming the top contact layer 958 and the upper contact layer 926 to form the structure as shown. The BRS layer 982 is formed above the top horizontal portion of the p-type top DBR layer 810. In this example, the BRS is a threshold switch selector (TSS), such as, for example: Ag / HfO2, Cu / HfO2, Ag / TiO2. It is important to note that although the integration of multilayer TSS is described, an insulator-metal transition (IMT) material or other bistable resistor system may be implemented alternatively. The quantization axis 1080 is shown as parallel to the optical cavity defined by the mesa structure 920.

[0132] Example 3: Vertical waveguide semiconductor device with bottom-contacted BRS

[0133] Fig.11 is a side view showing a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated on a backside contact according to another embodiment of the present invention. Figures 8 to 9A The process flow is such that the BRS layer 952 and the well 960 are no longer formed.

[0134] In this embodiment, a BRS layer 992 is horizontally deposited on the back side of the substrate 802, followed by a bottom metal contact layer 994, such as Ti / Au as shown. In this example, the BRS is a threshold switch selector (TSS), such as, for example: Ag / HfO2, Cu / HfO2, Ag / TiO2. It is important to note that although the integration of multiple layers of TSS is described, an insulator-metal transition (IMT) material or other bistable resistor system can be implemented instead. The quantization axis 1180 is shown as perpendicular to the hole 922.

[0135] Vertical waveguide semiconductor device with BRS integrated on buried bottom contact or top contact or backside contact Flowchart

[0136] Fig.12 FIG. 1 is a flow chart showing an example of a process for forming a vertical cavity surface emitting laser semiconductor device having a bistable resistor system according to an embodiment of the present invention. Figures 8 to 11Each step shown is discussed in more detail. The process begins at step 1202 and immediately proceeds to step 1204. In step 1204, a vertical waveguide, such as a vertical cavity surface emitting laser (VCSEL), is formed. The vertical waveguide includes a first waveguide layer 804 having a first doping type disposed above a semiconductor substrate 802, an active dielectric layer 806 disposed above the first waveguide layer 804, and a second waveguide layer 810 having a second doping type and an oxide layer 808 disposed above the active dielectric layer 806. In one example, the active dielectric layer 806 includes a plurality of quantum wells. The process continues to step 1206.

[0137] In step 1206, the first waveguide layer, the active dielectric layer 806, and the second waveguide layer 810 are selectively etched to form a mesa structure 920 having a top surface 812 and sidewalls, such as Fig. 9B , Fig.10 and Fig.11 The process continues to step 1208 .

[0138] In step 1208 is an optional step in which a wet oxidation process is used to form a hole 922 in the oxide layer 806 of the second waveguide layer 810. The process continues down one of the three paths represented by the dashed lines to form i) a buried bottom contact (step 1210 to step 1216) or ii) a top contact (step 1218 to step 1224) or iii) a backside contact (step 1226 to step 1230).

[0139] In case of a buried bottom contact, the process continues to step 1210. In step 1210, a well 960 is etched in the first waveguide layer 804 around the mesa structure 920. The process continues to step 1212. In step 1212, a bistable resistor system 952 is deposited. The process continues to step 1214. In step 1214, the BRS is selectively removed from above the top surface 812 of the second waveguide 810, as well as a portion of the sidewall closest to the top surface 852 of the mesa structure 920. A top contact layer 958 is formed in step 1216. The processes for forming the bottom contact layer 954, the dielectric layer 950, the upper contact layer 926, and the top contact layer 958 are as described above.

[0140] In the case of a top contact, the process continues to step 1218. First, a bottom contact layer 954 is formed in step 1218. Next, in step 1220, a bistable resistor system is deposited. The process continues to step 1222. In step 1222, a top contact 958 is formed. The process continues to step 1224. In step 1224, the bistable resistor system 982 is removed, leaving a portion above the top surface of the mesa structure 920 with an opening above the optional hole 922. The process for forming the upper contact layer 926 and the top contact layer 958 is as described above.

[0141] In case of backside contact, the process continues to step 1226. A bottom contact layer 954 is formed in step 1226. Next in step 1228, a bistable resistor system 992 is deposited over the bottom surface of the substrate 802. The process continues to step 1230. In step 1230, a metal contact layer 994 is formed over the BRS.

[0142] Example 4: Fabrication of an edge emitting laser diode semiconductor device with a BRS integrated on a top contact

[0143] Fig.13A and Fig. 13B is a schematic cross-sectional view showing the initial stages of forming an edge-emitting semiconductor laser or diode device with an integrated bi-stable resistor system in accordance with one embodiment of the present invention.

[0144] Go to Fig. 13B , the laser diode is constructed on a substrate 1302 of n-type GaAs with an n-type layer 1304 thereon, such as GaAsP having a composition denoted as GaAsyP1-y, wherein the layer 1302 is formed by a molecular beam epitaxy (MBE) and / or metal organic chemical vapor deposition (MOCVD) process. The growth process of the layer 1304 is well established, and a smooth surface is achieved by optimizing the composition gradient.

[0145] Next, an n-type cladding layer 1304 (such as n-type AlGaInAsP), a first waveguide layer 1306, an undoped active or active medium (such as InGaAsP) having a multi-quantum well layer 1308, a second waveguide layer 1310, a p-type cladding layer 1312 (such as p-type AlGaInAsP), and a cap layer 1314 of p-type GaAs are formed by an epitaxial process.

[0146] Fig.14A and Fig. 14B is a schematic cross-sectional view illustrating a later stage in the formation of an edge emitting semiconductor laser or diode device having a bi-stable resistor system integrated on a top contact 1420 in accordance with one embodiment of the present invention.

[0147] The p-type cladding layer 1312 and cap layer 1314 are patterned using photolithography techniques and etched to form a mesa-type structure 1420 as shown. Next, a dielectric isolation layer is formed using sequential oxide deposition, planarization, photolithography patterning, and etching techniques to define a top contact region.

[0148] The oxide layer 1430 is formed by depositing a capping oxide on top of the p-type cladding layer 1312 including the top and sidewalls of the mesa structure 1420. Oxide planarization is then used. A combination of an organic planarization layer (OPL) (not shown) is performed, followed by photolithography patterning and oxide etching. The OPL is then removed using an ashing process. The cap layer 1314 is removed and the top p-type cladding layer 1312 is selectively etched.

[0149] Next, as shown, a bistable resistor system (BRS) layer 1432 is formed over the oxide layer 1430 and the top of the mesa structure 1420. In this example, the BRS 1432 is a threshold switch selector (TSS), such as, for example: Ag / HfO2, Cu / HfO2, Ag / TiO2. It is important to note that although the integration of multi-layer TSS is described, an insulator-metal transition (IMT) material or other bistable resistor system may be implemented alternatively.

[0150] Finally, a top contact layer 1434 is formed over the BRS layer 1432. Next, a backside contact layer 1436, such as Ti / Au, is deposited on the bottom horizontal surface of the substrate 1302 as shown.

[0151] Example 5: Fabrication of an edge emitting laser diode semiconductor device with a BRS integrated on a backside contact

[0152] Fig.15 is a schematic cross-sectional view showing a later stage in the formation of an edge emitting semiconductor laser or diode device having a bistable resistor system integrated on a backside contact in accordance with one embodiment of the present invention.

[0153] Revise Figure 13A-13B to Figure 14A-14B The process flow is such that the BRS layer is no longer integrated above the top contact area 1420 and the top oxide layer 1430.

[0154] In this embodiment, a BRS layer 1536 is deposited on the back side of the doped substrate 1302 prior to forming the bottom contact layer 1436, followed by a back side metal contact layer 1538, such as Ti / Au as shown.

[0155] Example 6: BRS integration in the active medium of an intracavity laser

[0156] Fig.161 is a schematic side view showing a semiconductor laser device with a bistable resistance system integrated in the active medium of the laser according to one embodiment of the present invention. A first distributed Bragg reflector (DBR) or waveguide 1602, an active layer or active medium 1604 are shown. In one example, the active medium includes a multi-quantum well formed by a series of barriers 1614 and quantum wells 1616 known in the art. A second DBR 1608 is also shown. A bistable resistance system (BRS) layer 1614 is formed. A static electromagnetic field 1620 is depicted. The BRS layer 1614 is in-situ deposited at a node 1622 of the static electromagnetic field 1620 oscillating inside the optical cavity during the epitaxial process to minimize potential light absorption. The BRS layer can also act as a barrier. The maximum amplitude 1624 of the static electromagnetic field 1620 is selected to maximize the interaction with the quantum well. Note that this design is effective for both vertical cavity and side-emitting semiconductor laser devices.

[0157] Fig.17 is a schematic cross-sectional view illustrating the formation of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated within the active medium of the device according to one embodiment of the present invention. Figures 8 to 9A The process flow makes Fig.17 A BRS layer 1752 is shown deposited within the optical cavity. A quantization axis 980 is shown parallel to the optical cavity defined by the mesa-type structure 920.

[0158] Example 7: BRS integration in one of the waveguides constituting the laser cavity

[0159] Fig.18 is a schematic side view showing a semiconductor laser device having a bistable resistor system integrated within a waveguide of a laser optical cavity according to one embodiment of the present invention.

[0160] A first distributed Bragg reflector (DBR) or waveguide 1602, an active layer or active medium 1604 is shown. In one example, the active medium includes a multiple quantum well formed by a series of barriers 1614 and quantum wells 1616 as known in the art. A second DBR 1608 is also shown. As shown, a bistable resistance system (BRS) layer 1814 is created within the waveguide 1602. A static electromagnetic field 1620 is depicted. The BRS layer 1614 is deposited in situ at the nodes 1624 of the static electromagnetic field 1620 oscillating inside the optical cavity during the epitaxial process to minimize potential light absorption. The maximum amplitude 1624 of the static electromagnetic field 1620 is selected to maximize the interaction with the quantum well. Note that this design is effective for both vertical cavity and side-emitting semiconductor laser devices. The BRS can be integrated in either of the waveguides 1602 or 1608.

[0161] Fig.19is a schematic cross-sectional view showing the formation of a vertical cavity surface emitting laser semiconductor device having a bistable resistor system integrated within a waveguide of a laser optical cavity according to one embodiment of the present invention. Figures 8 to 9A In this example, the BRS layer 1952 is formed in the optical cavity, rather than Fig.18 The formed BRS layer 1814 is shown. An example of an epitaxially compatible threshold switch selector is taught by K. Fu et al. in IEEE Electron Device Letters, Vol. 40, No. 3, March 2019, pp. 375-378, "Threshold Switching and Memory Behaviors of Epitaxially Regrown GaN-on-GaN Vertical pn Diodes With High Temperature Stability". The quantization axis 1980 is shown to be parallel to the optical cavity defined by the mesa structure 920.

[0162] Flowchart for integration of active components or laser cavities in waveguides

[0163] Fig. 20 FIG. 1 is a flow chart showing an example of a process for forming a laser semiconductor device having a bistable resistor system in the active medium or waveguide of the laser according to an embodiment of the present invention. Fig.19 Discussed in more detail Fig. 20 2002 and immediately proceed to step 2004. In step 2004, a vertical waveguide, such as a vertical cavity surface emitting laser (VCSEL), is formed. The vertical waveguide includes a first waveguide layer 804 having a first doping type disposed above a semiconductor substrate 802, an active dielectric layer 806 disposed above the first waveguide layer 804, and a second waveguide layer 810 having a second doping type and an oxide layer 808 disposed above the active dielectric layer 806. In one example, a bistable resistor system layer 1614 is formed within the active dielectric. In another example, a bistable resistor system layer 1814 is formed within the second waveguide layer 810. The active dielectric layer 806 may include a plurality of quantum wells. The process continues to step 2006.

[0164] In step 2006, the first waveguide layer 804, the active dielectric layer 806, and the second waveguide layer 810 form a mesa-type structure 920 having a top surface and sidewalls as shown above. The process continues to step 2008.

[0165] In step 2008 is an optional step in which holes 922 are formed in the oxide layer of the second waveguide layer 810. The process is completed in step 2010.

Claims

1. A laser system, comprising: at least one semiconductor laser; as well as At least one bistable resistor system operating as a reversible switch is electrically connected in series with the at least one semiconductor laser, wherein the at least one bistable resistor system operates in the following two states: a high impedance state in which at least one semiconductor laser is below the lasing threshold and emits by a spontaneous emission mechanism, and A low-resistance state in which at least one semiconductor laser is above or equal to the lasing threshold and emits by a stimulated emission mechanism.

2. The laser system according to claim 1, wherein: The at least one bi-stable resistance system operating as a reversible switch is electrically connected in series across two separate chips.

3. The laser system of claim 1, wherein: The at least one bi-stable resistance system operating as a reversible switch is electrically connected in series on a single die.

4. The laser system of claim 1, wherein: The at least one bistable resistance system is formed using an insulator-metal transition material.

5. The laser system of claim 1, wherein: The at least one bi-stable resistance system is formed using a threshold switch selector.

6. A vertical waveguide laser semiconductor device, comprising: A semiconductor substrate and a layer structure formed on the semiconductor substrate, wherein the quantization axis of the active medium layer is parallel to the vertical axis of the optical cavity, and the layer structure comprises a first waveguide layer having a first doping type disposed above the semiconductor substrate, an active dielectric layer disposed above the first waveguide layer, and a second waveguide layer having a second doping type; a mesa structure having a top surface and sidewalls, formed by the first waveguide layer, the active medium layer, and the second waveguide layer; as well as A bistable resistor system (BRS) is formed i) around the mesa structure or adjacent to the first waveguide layer of the mesa structure, or ii) on a top surface of the mesa structure.

7. The vertical waveguide laser semiconductor device according to claim 6, wherein: The layer structure is a vertical cavity surface emitting laser (VSCEL).

8. The vertical waveguide laser semiconductor device according to claim 6, wherein: The bistable resistor system is formed using an insulator-metal transition material.

9. The vertical waveguide laser semiconductor device according to claim 6, wherein: The bistable resistor system is formed using a threshold switch selector.

10. The vertical waveguide laser semiconductor device according to claim 6, when the bistable resistor system is formed around the mesa structure or adjacent to the first waveguide layer of the mesa structure, further comprising: a first contact layer formed over the bistable resistor system; an aperture formed in said second waveguide layer; as well as A second contact layer is formed over the second waveguide layer and has an opening over the hole, the second contact layer being electrically isolated from the first contact layer.

11. A vertical waveguide laser semiconductor device, comprising: A semiconductor substrate and a layer structure formed on the semiconductor substrate, wherein the quantization axis of the active medium layer is parallel to the vertical axis of the optical cavity, and the layer structure comprises a first waveguide layer having a first doping type disposed above the semiconductor substrate, an active dielectric layer disposed above the first waveguide layer, and a second waveguide layer having a second doping type; as well as a mesa structure having a top surface and sidewalls, formed by the first waveguide layer, the active medium layer, and the second waveguide layer; a bistable resistor system (BRS) formed on a bottom side of the semiconductor substrate; a first contact layer formed over the bistable resistor system; as well as A second contact layer is formed over the second waveguide layer, the second contact layer being electrically isolated from the first contact layer.

12. The vertical waveguide laser semiconductor device according to claim 11, wherein: The bistable resistor system is formed using an insulator-metal transition material.

13. The vertical waveguide laser semiconductor device according to claim 11, wherein: The bistable resistor system is formed using a threshold switch selector.

14. An edge emitting laser semiconductor device, the edge emitting laser semiconductor device comprising: A semiconductor substrate and a layer structure formed on the semiconductor substrate, the layer structure comprising a first cladding layer having a first doping type disposed over the top side of the semiconductor substrate; a first waveguide layer disposed above the first cladding layer, an active dielectric layer disposed above the first waveguide layer, a second waveguide layer disposed above the active medium layer, and a second cladding layer having a second doping type disposed over the second waveguide layer; a mesa-type structure having a top surface and sidewalls, formed by the second cladding layer and an oxide layer formed on either side of the mesa-type structure; as well as Bistable Resistor System (BRS) i) forming a first contact layer on the top surface of the mesa structure, wherein a first contact layer is formed on the bistable resistor system; and forming a second contact layer on the bottom side of the semiconductor substrate, or ii) Forming on the bottom side of the semiconductor substrate, wherein a first contact layer is formed on the bistable resistor system and a second contact layer is formed on the top surface of the mesa structure.

15. The edge emitting laser semiconductor device according to claim 14, wherein: The bistable resistor system is formed using an insulator-metal transition material.

16. The edge emitting laser semiconductor device according to claim 15, wherein: The bistable resistor system is formed using a threshold switch selector.

17. A vertical waveguide laser semiconductor device, comprising: A semiconductor substrate and a layer structure formed on the semiconductor substrate, wherein the quantization axis of the active medium layer is parallel to the vertical axis of the optical cavity, and the layer structure comprises a first waveguide layer having a first doping type disposed above the semiconductor substrate, an active dielectric layer disposed above the first waveguide layer, and a second waveguide layer having a second doping type, wherein at least one layer of a bistable resistor system (BRS) is formed i) within the active dielectric layer or ii) within one of the first waveguide layer and the second waveguide layer; as well as A mesa structure having a top surface and side walls is formed by the first waveguide layer, the active medium layer and the second waveguide layer.

18. The vertical waveguide laser semiconductor device according to claim 17, further comprising: a first contact layer formed over the first waveguide layer; as well as A second contact layer is formed over the second waveguide layer and has an opening over the hole in the second waveguide layer, the second contact layer being electrically isolated from the first contact layer.

19. The vertical waveguide laser semiconductor device according to claim 17, wherein: The layer structure is a vertical cavity surface emitting laser (VSCEL).

20. The vertical waveguide laser semiconductor device according to claim 17, wherein: The bistable resistor system is formed using an insulator-metal transition material.

21. The vertical waveguide laser semiconductor device according to claim 17, wherein: The bistable resistor system is formed using a threshold switch selector.

22. The vertical waveguide laser semiconductor device according to claim 17, wherein: At least one layer of a bistable resistor system (BRS) is formed at a node of a static electromagnetic field oscillating in the optical cavity within the active dielectric layer to minimize light absorption.

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