Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The application provides a semiconductor structure preparation method and a semiconductor structure, and relates to the technical field of semiconductors. The semiconductor structure preparation method comprises the following steps: providing a substrate, the substrate having a plurality of grooves arranged at intervals; forming an initial barrier layer in each groove; removing part of the initial barrier layer to form a first intermediate barrier layer; and removing part of the first intermediate barrier layer to form a barrier layer, the width of the barrier layer being equal in a direction perpendicular to the substrate. The top surface of the first intermediate barrier layer is micro-convex, so that the top surface of the barrier layer obtained by continuing to etch the first intermediate barrier layer is a plane. Compared with the prior art in which the top surface of the barrier layer is concave, the barrier layer does not wrap the conductive layer, the work function at the conductive layer is reduced, the risk of gate-induced drain leakage current is reduced, and the performance of the semiconductor structure is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] Dynamic random access memory (DRAM) is a semiconductor memory that allows for high-speed, random writing and reading of data and is widely used in data storage devices or apparatuses.

[0003] Dynamic random access memory (DRAM) consists of multiple repeating memory cells. Each memory cell typically includes a capacitor structure and a transistor. The gate of the transistor is connected to the word line, the drain is connected to the bit line, and the source is connected to the capacitor structure. The voltage signal on the word line can control the transistor to turn on or off, thereby reading the data information stored in the capacitor structure through the bit line, or writing the data information into the capacitor structure for storage through the bit line.

[0004] As the integration density of dynamic random access memory (DRAM) increases, the word line width becomes smaller, which easily leads to gate-induced drain leakage (GIDL) and degrades the performance of the semiconductor structure. Summary of the Invention

[0005] In view of the above problems, embodiments of the present invention provide a method for preparing a semiconductor structure and a semiconductor structure, which are used to reduce gate-induced drain leakage current and improve the performance of the semiconductor structure.

[0006] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0007] A first aspect of this invention provides a method for fabricating a semiconductor structure, comprising:

[0008] A substrate is provided, the substrate having a plurality of grooves spaced apart, the area between adjacent grooves forming a protrusion, and the plurality of grooves and the plurality of protrusions being alternately arranged along a first direction;

[0009] An initial barrier layer is formed within each of the trenches, the initial barrier layer extending outside the trenches and covering the protrusions;

[0010] A portion of the initial barrier layer and a portion of the protrusions are removed, as well as a portion of the initial barrier layer located within the trench. The initial barrier layer remaining within the trench constitutes a first intermediate barrier layer. The top surface of the first intermediate barrier layer is an arc-shaped surface, which is slightly convex and higher than the top surface of the retained protrusions.

[0011] The portion of the first intermediate barrier layer located within each of the trenches is removed, and the remaining first intermediate barrier layer within each of the trenches constitutes a barrier layer, the width of which is equal everywhere along a direction perpendicular to the substrate;

[0012] A conductive layer is formed on each of the barrier layers, and the barrier layers and the conductive layer located in the same trench constitute a word line.

[0013] The semiconductor structure fabrication method described above, wherein the steps of removing a portion of the initial barrier layer and a portion of the protrusions, and removing a portion of the initial barrier layer located within the trench, include:

[0014] The initial blocking layer located on the protrusion is removed, the initial blocking layer located above the groove is removed, and a portion of the initial blocking layer located in the groove is removed. The initial blocking layer remaining in the groove constitutes a second intermediate blocking layer. The top surface of the second intermediate blocking layer is recessed downwards to form a groove in the second intermediate blocking layer.

[0015] The protrusion with a portion of its thickness removed and the groove wall of the top groove of the second intermediate barrier layer removed, the remaining second intermediate barrier layer constitutes the first intermediate barrier layer, the top surface of the first intermediate barrier layer being higher than the top surface of the protrusion with the remaining thickness removed.

[0016] In the semiconductor structure fabrication method described above, the second intermediate barrier layer includes a second strip structure extending along a second direction, the top surface of the second strip structure being recessed toward the substrate to form the groove;

[0017] The second direction intersects with the first direction.

[0018] In the semiconductor structure fabrication method described above, the first intermediate barrier layer includes a first strip structure extending along the second direction, the top surface of the first strip structure protruding in a direction away from the substrate, so that the top surface of the first strip structure forms an arc-shaped surface.

[0019] In the semiconductor structure fabrication method described above, the height difference between the highest point of the top surface of the first intermediate barrier layer and the top surface of the retained protrusion is 3 to 5 nm.

[0020] The method for fabricating a semiconductor structure as described above, wherein the step of removing a portion of the first intermediate barrier layer located within the trench and retaining the first intermediate barrier layer within the trench to form a barrier layer includes:

[0021] The barrier layer includes a strip structure extending along a second direction, with a longitudinal section perpendicular to the substrate, and the longitudinal section of the strip structure is rectangular.

[0022] The method for fabricating a semiconductor structure as described above, wherein the step of providing the substrate includes:

[0023] A substrate is provided having a plurality of active regions therein and an isolation structure for separating each of the active regions;

[0024] An insulating layer is formed on the substrate;

[0025] A plurality of trenches are formed at intervals on the insulating layer, each trench extending into the substrate and each trench exposing the active region.

[0026] The method for fabricating a semiconductor structure as described above, wherein the step of forming a conductive layer on each of the barrier layers includes:

[0027] The barrier layer and the substrate form a first intermediate groove, and an initial conductive layer is formed in the first intermediate groove, the initial conductive layer filling the first intermediate groove.

[0028] The portion of the initial conductive layer located within the first intermediate groove is removed, and the initial conductive layer remaining within the first intermediate groove constitutes a conductive layer, which, together with the substrate, forms a second intermediate groove.

[0029] The semiconductor structure fabrication method described above, after the step of removing a portion of the initial conductive layer located within the first intermediate trench, further includes:

[0030] A dielectric layer is formed within the second intermediate groove, the dielectric layer extending outside the second intermediate groove and covering the substrate.

[0031] The semiconductor structure fabrication method described above, wherein the step of forming a dielectric layer within the second intermediate trench includes:

[0032] A first dielectric layer is formed in the second intermediate groove, the top surface of the first dielectric layer being lower than the top surface of the retained insulating layer;

[0033] Remove the remaining insulating layer so that the top surface of the first dielectric layer is flush with the top surface of the substrate;

[0034] A second dielectric layer and a third dielectric layer are formed sequentially on the substrate, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer constitute the dielectric layer.

[0035] The semiconductor structure fabrication method described above, wherein the step of forming a first dielectric layer within the second intermediate trench includes:

[0036] A first initial dielectric layer is formed within the second intermediate groove, the first initial dielectric layer extending outside the second intermediate groove and covering the retained insulating layer;

[0037] A portion of the first initial dielectric layer is removed, and the remaining first initial dielectric layer constitutes the first dielectric layer.

[0038] In the semiconductor structure fabrication method described above, the barrier layer is made of titanium nitride.

[0039] In the semiconductor structure fabrication method described above, the insulating layer and the second dielectric layer are made of the same material, both comprising silicon oxide;

[0040] The first dielectric layer and the third dielectric layer are made of the same material, both including silicon nitride.

[0041] In the semiconductor structure fabrication method described above, the conductive layer is made of polycrystalline silicon.

[0042] A second aspect of the present invention provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described above.

[0043] In the semiconductor structure fabrication method and semiconductor structure provided in this embodiment of the invention, by controlling the etching energy and etching gas of dry etching, the top surface of the first intermediate barrier layer is made to be slightly convex. By continuing to etch the first intermediate barrier layer, the top surface of the barrier layer is made to be planar. Compared with the related technology in which the top surface of the barrier layer is concave, the barrier layer does not cover the conductive layer, which reduces the work function at the conductive layer, reduces the risk of gate-induced drain leakage current, and improves the performance of the semiconductor structure.

[0044] In addition to the technical problems solved by the embodiments of the present invention, the technical features constituting the technical solutions, and the beneficial effects brought about by the technical features of these technical solutions described above, the semiconductor structure preparation method and semiconductor structure provided by the embodiments of the present invention, other technical problems that can be solved by the semiconductor structure, other technical features included in the technical solutions, and the beneficial effects brought about by these technical features will be further explained in detail in the specific embodiments. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram of the barrier layer formed in a semiconductor structure fabrication method provided in related technologies.

[0047] Figure 2 This is a schematic diagram of the structure in which a conductive layer is formed in a semiconductor structure fabrication method provided in related technologies.

[0048] Figure 3 A process flow diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0049] Figure 4 This is a schematic diagram of the substrate structure in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0050] Figure 5 This is a schematic diagram of the structure forming trenches in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0051] Figure 6 This is a schematic diagram of the structure forming the initial barrier layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0052] Figure 7 This is a schematic diagram of the structure for forming the second intermediate barrier layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0053] Figure 8 This is a schematic diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention, in which part of the protrusion is removed;

[0054] Figure 9 This is a schematic diagram of the structure for forming the first intermediate barrier layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0055] Figure 10 This is a schematic diagram of the structure forming the barrier layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0056] Figure 11 This is a schematic diagram of the structure forming the initial conductive layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0057] Figure 12 This is a schematic diagram of the structure forming the conductive layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0058] Figure 13 This is a schematic diagram of the structure for forming the first initial dielectric layer in the semiconductor structure fabrication method provided in the embodiments of the present invention;

[0059] Figure 14 A schematic diagram of the structure for forming the first dielectric layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 1 ;

[0060] Figure 15 A schematic diagram of the structure for forming the first dielectric layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 2 ;

[0061] Figure 16 A schematic diagram of the structure for forming the first dielectric layer in the semiconductor structure fabrication method provided in this embodiment of the invention. Figure 3 ;

[0062] Figure 17 This is a schematic diagram of the semiconductor structure fabrication method provided in the embodiments of the present invention, in which a second dielectric layer and a third dielectric layer are formed.

[0063] Figure label:

[0064] 10: Base; 11: Trench;

[0065] 12: Protrusion; 13: Substrate;

[0066] 14: Isolation structure; 15: Insulation layer;

[0067] 20: Initial barrier layer; 21: First intermediate barrier layer;

[0068] 22: Second intermediate barrier layer; 23: Barrier layer;

[0069] 30: Initial conductive layer; 31: Conductive layer;

[0070] 40: First intermediate groove; 50: Second intermediate groove;

[0071] 60: Dielectric layer; 61: First initial dielectric layer;

[0072] 62: First dielectric layer; 63: Second dielectric layer;

[0073] 64: Third dielectric layer. Detailed Implementation

[0074] like Figure 1 and Figure 2As shown, in the related technology, when preparing a semiconductor structure, a trench is usually formed in the substrate first, and then a barrier layer 23 and a conductive layer 31 are formed in sequence in the trench. However, when forming the barrier layer 23, the top surface of the barrier layer 23 is easily recessed, which causes the barrier layer 23 to wrap around the conductive layer 31, increasing the work function at the location of the conductive layer, increasing the gate-induced drain leakage current, and reducing the performance of the semiconductor structure.

[0075] Existing semiconductor structures also have gate-induced drain leakage current. In order to reduce gate-induced drain leakage current, the oxide layer on the inner wall of the trench is usually improved. However, other causes of gate-induced drain leakage current have not been explored in depth. After analysis and research, the inventors found that gate-induced drain leakage current is caused by increasing the work function at the location of the conductive layer, which ultimately leads to gate-induced drain leakage current and reduces the performance of the semiconductor structure.

[0076] Therefore, by controlling the etching energy and etching gas of dry etching, the inventors made the top surface of the first intermediate barrier layer slightly convex. By continuing to etch the first intermediate barrier layer, the top surface of the resulting barrier layer is flat. Compared with the related technology where the top surface of the barrier layer is concave, the barrier layer does not cover the conductive layer, which reduces the work function at the conductive layer, reduces the risk of gate-induced drain leakage current, and improves the performance of the semiconductor structure.

[0077] To make the above-mentioned objectives, features, and advantages of the embodiments of the present invention more apparent and understandable, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0078] Figure 3 This is a flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention. Figures 4-17 The diagram below illustrates the various stages of semiconductor structure fabrication. Figures 3-17 The methods for fabricating semiconductor structures are described in detail.

[0079] This embodiment does not limit the semiconductor structure. The following description will take dynamic random access memory (DRAM) as an example, but this embodiment is not limited to this. Other semiconductor structures are also possible in this embodiment.

[0080] like Figure 3 As shown in the figure, an embodiment of the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0081] Step S100: Provide a substrate having a plurality of grooves spaced apart, the area between adjacent grooves forming a protrusion, and the plurality of grooves and the plurality of protrusions being alternately arranged along a first direction.

[0082] For example, such as Figure 4 As shown, the substrate 10 serves as a support component for the memory, supporting other components disposed thereon. The substrate 10 may be made of a semiconductor material, which may be one or more of silicon, germanium, silicon-germanium compounds, and silicon-carbon compounds.

[0083] It should be noted that the substrate 10 can be a single-layer structure or a multilayer structure. When the substrate 10 is a multilayer structure, the substrate 10 can include a substrate 13 and an insulating layer 15 disposed on the substrate 13. The substrate 13 is provided with an isolation structure 14, which is used to isolate multiple active regions that are spaced apart. The multiple active regions can be arranged in an array. Furthermore, the insulating layer 15 can be made of silicon oxide.

[0084] like Figure 5 As shown, a patterned substrate 10 is formed within the substrate 10 to form a plurality of trenches 11 for forming word lines. The plurality of trenches 11 are spaced apart along a first direction, that is, the plurality of trenches 11 are spaced apart along the X direction shown in the figure. Each trench 11 is used to expose the active region of the substrate to enable electrical connection between the word lines subsequently formed in the trench and the active region.

[0085] The area between adjacent grooves forms a protrusion 12. Multiple grooves 11 and multiple protrusions 12 are alternately arranged along a first direction. The protrusions 12 are arranged to achieve electrical isolation of each character line.

[0086] It should be noted that when the substrate is a multilayer structure, the insulating layer 15 can be patterned, and multiple trenches are formed in the insulating layer 15 at intervals. Each trench extends into the substrate, and each trench exposes an active region.

[0087] Step S200: An initial barrier layer is formed in each trench, the initial barrier layer extends outside the trench and covers the protrusion.

[0088] like Figure 6 As shown, an initial barrier layer 20 is deposited in each trench 11 by chemical vapor deposition or physical vapor deposition. The initial barrier layer 20 extends outside the trench 11 and covers the top surface of the protrusion 12. Due to the limitations of the deposition process, the top surface of the initial barrier layer 20 is not flat, but uneven, and the position above the trench 11 is recessed.

[0089] The initial barrier layer 20 is typically made of titanium nitride. Titanium nitride can prevent the conductive material formed in the trench 11 from penetrating into the substrate, while also being conductive, thus ensuring the performance of the semiconductor structure.

[0090] Step S300: Remove part of the initial barrier layer and part of the protrusion, and remove part of the initial barrier layer located in the trench. The initial barrier layer retained in the trench constitutes the first intermediate barrier layer. The top surface of the first intermediate barrier layer is an arc-shaped surface with a slight convex shape, and the arc-shaped surface is higher than the top surface of the retained protrusion.

[0091] For example, such as Figure 7 As shown, by using dry etching, the initial barrier layer 20 located on the protrusion 12, the initial barrier layer 20 located above the trench 11, and a portion of the initial barrier layer 20 located in the trench 11 are removed. The initial barrier layer 20 remaining in the trench 11 forms a second intermediate barrier layer 22. The top surface of the second intermediate barrier layer 22 is recessed downwards to form a groove 221 in the second intermediate barrier layer 22.

[0092] Because the top surface of the initial barrier layer 20 is uneven, that is, the top surface of the initial barrier layer 20 is wavy, and the trough of the initial barrier layer 20 is located above the trench 11, when the initial barrier layer is dry-etched, under the same etching rate, part of the initial barrier 20 located in the trench will be etched, so that the top surface of the initial barrier layer 20 located in the trench 11 is recessed downward to form a groove 221. For the convenience of the subsequent description of the initial barrier layer retained in the trench 11, this embodiment refers to the initial barrier layer 20 retained in the trench 11 as the second intermediate barrier layer 22.

[0093] In this embodiment, the second intermediate barrier layer 22 includes a second strip structure extending along a second direction. The top surface of the second strip structure is recessed toward the substrate 10 to form a groove 221. The second direction intersects with the first direction, that is, the second direction is a direction perpendicular to the paper and pointing inward.

[0094] After the second intermediate barrier layer is formed, such as Figure 8 and Figure 9 As shown, a high-selectivity etching gas is used to continue etching the protrusion 12 and the second intermediate barrier layer 22, removing a portion of the thickness of the protrusion 12 and the groove wall of the groove 221 at the top of the second intermediate barrier layer 22. The remaining second intermediate barrier layer 22 forms the first intermediate barrier layer 21. The top surface of the first intermediate barrier layer 21 is higher than the top surface of the remaining protrusion 12, and the top surface of the first intermediate barrier is a novel arc-shaped surface with a slight convexity, that is, the curvature of the arc-shaped surface is away from the substrate 10.

[0095] In this embodiment, a gas with a high etching ratio is selected to etch the protrusion and the second intermediate barrier layer, so that the etching rate of the protrusion is greater than that of the second intermediate barrier layer, and the etching amount of the protrusion is greater than that of the second intermediate barrier layer, thereby making the top surface of the first intermediate barrier layer higher than the top surface of the retained protrusion.

[0096] Furthermore, during the dry etching process, the top edges of the second intermediate barrier layer gradually become rounded under the bombardment of high-energy plasma, so that the top surface of the first intermediate barrier layer formed at the end is arc-shaped, thus making the top surface of the barrier layer formed subsequently flattened.

[0097] In this embodiment, the etching gas for dry etching may include any one of CF4, Ar and He, and the pressure of dry etching is 3-6mt, the source power of dry etching is 200-400W, and the bias power of dry etching is 600-1000V.

[0098] In this embodiment, the first intermediate barrier layer includes a first strip structure extending along a second direction, the top surface of the first strip structure protruding in a direction away from the substrate 10, so that the top surface of the first strip structure forms an arc-shaped surface.

[0099] In this embodiment, the height difference between the highest point of the top surface of the first intermediate barrier layer 21 and the top surface of the retained protrusion is 3-5 nm. If the height difference between the highest point of the top surface of the first intermediate barrier layer 21 and the top surface of the retained protrusion is less than 3 nm, the top surface of the barrier layer formed by subsequent etching of the first intermediate barrier layer will still form a concave shape, making it impossible to avoid the barrier layer wrapping the subsequently formed conductive layer and making it difficult to reduce the work function at the conductive layer. If the height difference between the highest point of the top surface of the first intermediate barrier layer 21 and the top surface of the retained protrusion is greater than 5 nm, the substrate will be over-etched during subsequent etching of the first intermediate barrier layer, causing damage to the substrate. Therefore, this embodiment limits the height difference between the highest point of the top surface of the first intermediate barrier layer 21 and the top surface of the retained protrusion to reduce the work function at the conductive layer while ensuring the performance of the semiconductor structure.

[0100] Step S400: Remove a portion of the first intermediate barrier layer located in each trench, leaving the first intermediate barrier layer in each trench to form a barrier layer, with the width of the barrier layer being equal everywhere along the direction perpendicular to the substrate.

[0101] like Figure 10 As shown, dry etching is continued to etch a portion of the first intermediate barrier layer 21 located in each trench 11. The first intermediate barrier layer 21 retained in each trench forms a barrier layer 23, and the barrier layer 23 and the protrusion 12 form a first intermediate groove 40.

[0102] Along the direction perpendicular to the base 10, the width of the barrier layer 23 is equal everywhere. In other words, with the longitudinal section perpendicular to the base 10, the longitudinal section of the barrier layer 23 is rectangular, making the top surface of the barrier layer 23 flat.

[0103] Step S500: A conductive layer is formed on each barrier layer, and the barrier layers and conductive layers located in the same trench form a word line.

[0104] like Figure 11 As shown, an initial conductive layer 30 is formed in the first intermediate tank 40 using a chemical vapor deposition process or a physical vapor deposition process. The initial conductive layer 30 fills the first intermediate tank 40 and extends to the outside of the first intermediate tank 40, covering the top surface of the substrate 10.

[0105] After the initial conductive layer is formed, such as Figure 12 As shown, the initial conductive layer 30 located on the top surface of the substrate 10 and a portion of the initial conductive layer 30 located in the first intermediate trench 40 are removed by etching gas or etching liquid. The initial conductive layer remaining in the first intermediate trench 40 constitutes the conductive layer 31, and the conductive layer 31 and the substrate 10 form a second intermediate trench 50.

[0106] The conductive layer can be made of conductive materials such as polycrystalline silicon.

[0107] This embodiment divides the process of etching the initial barrier layer to form the barrier layer into three steps. By controlling the etching energy and etching gas of the dry etching process, the top surface of the first intermediate barrier layer is made slightly convex. By continuing to etch the first intermediate barrier layer, the top surface of the resulting barrier layer is planar. Compared with the related technology where the top surface of the barrier layer is concave, the barrier layer does not cover the conductive layer, which reduces the work function at the location of the conductive layer, reduces the risk of gate-induced drain leakage current, and improves the performance of the semiconductor structure.

[0108] After the conductive layer is formed, the method for preparing the semiconductor structure provided in this embodiment of the invention further includes:

[0109] like Figures 13 to 17 As shown, a dielectric layer 60 is formed in the second intermediate groove 50, and the dielectric layer 60 extends outside the second intermediate groove 50 and covers the substrate 10.

[0110] For example, a first dielectric layer 62 is formed in the second intermediate groove, and the top surface of the first dielectric layer 62 is lower than the top surface of the retained insulating layer 15.

[0111] like Figure 13As shown, physical vapor deposition and chemical vapor deposition processes can be used to deposit a first initial dielectric layer 61 in the second intermediate tank 50. The first initial dielectric layer 61 extends to the outside of the first intermediate tank 40 and covers the top surface of the retained insulating layer. In other words, the first initial dielectric layer 61 covers the top surface of the retained protrusion.

[0112] Then, as Figure 14 As shown, the first initial dielectric layer 61 located on the top surface of the retained protrusion and the first initial dielectric layer 61 located above the second intermediate groove are removed, and the top surface of the retained first initial dielectric layer 61 is flush with the top surface of the retained protrusion.

[0113] like Figure 15 As shown, the first initial dielectric layer 61 located in the second intermediate groove is removed, and the retained first initial dielectric layer 61 constitutes the first dielectric layer 62.

[0114] After the first dielectric layer 62 is formed, as follows Figure 16 As shown, the remaining insulating layer is removed using an etching solution or etching gas so that the top surface of the first dielectric layer 62 is flush with the top surface of the substrate 13.

[0115] After that, as Figure 17 As shown, by continuing the deposition process, a second dielectric layer 63 and a third dielectric layer 64 are formed on the substrate 13 in sequence. The first dielectric layer 62, the second dielectric layer 63 and the third dielectric layer 64 constitute the dielectric layer 60.

[0116] The insulating layer 15 and the second dielectric layer 63 are made of the same material, both including silicon oxide; the first dielectric layer 62 and the third dielectric layer 64 are made of the same material, both including silicon nitride.

[0117] This invention also provides a semiconductor structure, which is prepared by the semiconductor structure preparation method described in the above embodiments. Therefore, the semiconductor structure can reduce the work function of the region where the conductive layer is located, avoid the generation of gate-induced drain leakage current in the semiconductor structure, and improve the performance of the semiconductor structure.

[0118] The various embodiments or implementation methods described in this specification are presented in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the embodiments can be referred to each other.

[0119] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with an embodiment or example that are included in at least one embodiment or example of the present invention.

[0120] In this specification, the illustrative expressions of the terms used do not necessarily refer to the same implementation or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more implementations or examples.

[0121] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, The steps include the following: A substrate is provided, the substrate having a plurality of grooves spaced apart, the area between adjacent grooves forming a protrusion, and the plurality of grooves and the plurality of protrusions being alternately arranged along a first direction; An initial barrier layer is formed within each of the trenches, the initial barrier layer extending outside the trench and covering the protrusion; A portion of the initial barrier layer and a portion of the protrusions are removed, as well as a portion of the initial barrier layer located within the trench. The initial barrier layer remaining within the trench constitutes a first intermediate barrier layer. The top surface of the first intermediate barrier layer is an arc-shaped surface, which is slightly convex and higher than the top surface of the retained protrusions. The portion of the first intermediate barrier layer located within each of the trenches is removed, and the remaining first intermediate barrier layer within each of the trenches constitutes a barrier layer, the width of which is equal everywhere along a direction perpendicular to the substrate; A conductive layer is formed on each of the barrier layers, and the barrier layers and the conductive layer located in the same trench constitute a word line.

2. The method for preparing a semiconductor structure according to claim 1, characterized in that, The steps of removing a portion of the initial barrier layer and a portion of the protrusion, and removing a portion of the initial barrier layer located within the trench, include: The initial blocking layer located on the protrusion is removed, the initial blocking layer located above the groove is removed, and a portion of the initial blocking layer located in the groove is removed. The initial blocking layer remaining in the groove constitutes a second intermediate blocking layer. The top surface of the second intermediate blocking layer is recessed downwards to form a groove in the second intermediate blocking layer. The protrusion with a portion of its thickness removed and the groove wall of the top groove of the second intermediate barrier layer removed, the remaining second intermediate barrier layer constitutes the first intermediate barrier layer, the top surface of the first intermediate barrier layer being higher than the top surface of the protrusion with the remaining thickness removed.

3. The method for preparing a semiconductor structure according to claim 2, characterized in that, The second intermediate barrier layer includes a second strip structure extending along a second direction, the top surface of the second strip structure being recessed toward the substrate to form the groove; The second direction intersects with the first direction.

4. The method for preparing a semiconductor structure according to claim 3, characterized in that, The first intermediate barrier layer includes a first strip structure extending along the second direction, the top surface of the first strip structure protruding in a direction away from the substrate, so that the top surface of the first strip structure forms an arc-shaped surface.

5. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The height difference between the highest point of the top surface of the first intermediate barrier layer and the top surface of the retained protrusion is 3 to 5 nm.

6. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The step of removing a portion of the first intermediate barrier layer located within the trench, while retaining the first intermediate barrier layer within the trench to form a barrier layer, includes: The barrier layer includes a strip structure extending along a second direction, with a longitudinal section perpendicular to the substrate, and the longitudinal section of the strip structure is rectangular.

7. The method for preparing a semiconductor structure according to any one of claims 1-4, characterized in that, The step of providing the substrate includes: A substrate is provided having a plurality of active regions therein and an isolation structure for separating each of the active regions; An insulating layer is formed on the substrate; A plurality of trenches are formed at intervals within the insulating layer, each trench extending into the substrate and each trench exposing the active region.

8. The method for preparing a semiconductor structure according to claim 7, characterized in that, The step of forming a conductive layer on each of the barrier layers includes: The barrier layer and the substrate form a first intermediate groove, and an initial conductive layer is formed in the first intermediate groove, the initial conductive layer filling the first intermediate groove. The portion of the initial conductive layer located within the first intermediate groove is removed, and the initial conductive layer remaining within the first intermediate groove constitutes a conductive layer, which, together with the substrate, forms a second intermediate groove.

9. The method for preparing a semiconductor structure according to claim 8, characterized in that, After the step of removing a portion of the initial conductive layer located within the first intermediate trench, the fabrication method further includes: A dielectric layer is formed within the second intermediate groove, the dielectric layer extending outside the second intermediate groove and covering the substrate.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that, The step of forming a dielectric layer in the second intermediate trench includes: A first dielectric layer is formed in the second intermediate groove, the top surface of the first dielectric layer being lower than the top surface of the retained insulating layer; Remove the remaining insulating layer so that the top surface of the first dielectric layer is flush with the top surface of the substrate; A second dielectric layer and a third dielectric layer are formed sequentially on the substrate, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer constitute the dielectric layer.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that, The step of forming the first dielectric layer in the second intermediate trench includes: A first initial dielectric layer is formed within the second intermediate groove, the first initial dielectric layer extending outside the second intermediate groove and covering the retained insulating layer; A portion of the first initial dielectric layer is removed, and the remaining first initial dielectric layer constitutes the first dielectric layer.

12. The method for preparing a semiconductor structure according to claim 1, characterized in that, The barrier layer is made of titanium nitride.

13. The method for preparing a semiconductor structure according to claim 11, characterized in that, The insulating layer and the second dielectric layer are made of the same material, both including silicon oxide; The first dielectric layer and the third dielectric layer are made of the same material, both including silicon nitride.

14. The method for preparing a semiconductor structure according to claim 8, characterized in that, The conductive layer is made of polycrystalline silicon.

15. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method for preparing a semiconductor structure as described in any one of claims 1-14.

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