Dynamic random access memory and manufacturing method thereof
By adopting a multi-layer gate dielectric layer and air gap design in dynamic random access memory, the problem of improving the efficiency of dynamic random access memory is solved, and higher on-current and lower Leakage current improves the overall performance of the memory.
Patent Information
- Application Number
- CN202110522769.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2021-05-13
- Publication Date
- 2024-12-27
- Estimated Expiration
- 2041-05-13
AI Technical Summary
As the design size of dynamic random access memory is reduced, how to improve its performance has become an urgent problem, especially in terms of write recovery time and refresh performance.
The embedded word line structure with a multi-layer gate dielectric layer structure and an air gap design is adopted. By forming an isolation structure and a word line trench in the substrate, multiple active areas are built, and the first and first and The second gate dielectric layer, the second gate dielectric layer has a higher dielectric constant than the first layer, forming an air gap to increase the conduction current and reduce the leakage current.
Improve the reliability and conduction current of the gate dielectric layer, reduce leakage current, improve memory efficiency, and avoid the risk of increasing manufacturing costs.
Smart Images
Figure CN115346982B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a dynamic random access memory and a manufacturing method thereof. Background Art
[0002] The capacity of DRAM directly affects the access speed and performance of the memory, such as write recovery time (tWR) and refresh performance. However, as the size of DRAM design continues to shrink and semiconductor devices continue to develop towards higher integration, how to improve the performance of DRAM has become an urgent problem to be solved in the field. Summary of the invention
[0003] The present invention is directed to a state random access memory with improved performance.
[0004] According to an embodiment of the present invention, a dynamic random access memory includes: a substrate; an isolation structure located in the substrate, the isolation structure defining a plurality of active areas; a buried word line structure located in a word line trench of the substrate, the word line trench passing through the plurality of active areas and the isolation structure, the buried word line structure including: a gate conductor layer located in the word line trench; a first gate dielectric layer located on the sidewalls and bottom surface of the word line trench; and a second gate dielectric layer located between the first gate dielectric layer and the gate conductor layer, wherein the top surface of the second gate dielectric layer is lower than the top surface of the gate conductor layer.
[0005] According to an embodiment of the present invention, a method for manufacturing a dynamic random access memory includes: providing a substrate; forming an isolation structure in the substrate, wherein the isolation structure defines a plurality of active regions; forming a word line trench in the substrate and the isolation structure, wherein the word line trench passes through the plurality of active regions and the isolation structure; and forming a buried word line structure in the word line trench. Forming the buried word line structure in the word line trench includes: forming a first gate dielectric layer, a second gate dielectric layer, and a gate conductor layer above the substrate and in the word line trench, wherein the dielectric constant of the second gate dielectric layer is greater than the dielectric constant of the first gate dielectric layer; removing a portion of the gate conductor layer outside the word line trench and in the word line trench; removing a portion of the second gate dielectric layer outside the word line trench and in the word line trench, so that the top surface of the remaining second gate dielectric layer is lower than the top surface of the remaining gate conductor layer; and forming a cap in the word line trench to cover the top surface of the remaining gate conductor layer.
[0006] Based on the above, the dynamic random access memory in the embodiment of the present invention has multiple gate dielectric layers and air gaps, which can not only improve the reliability of the gate dielectric layer and the on-current, but also reduce various leakage currents.
[0007] In addition, the manufacturing method of the dynamic random access memory of the embodiment of the present invention can flexibly adjust the materials and thicknesses of the first gate dielectric layer and the second gate dielectric layer and the depth of the air gap according to the electrical properties or characteristics of the required components. In the manufacturing process of the present invention, no additional photomask is required to pattern the first gate dielectric layer and / or the second gate dielectric layer, so the manufacturing cost will not be excessively increased. BRIEF DESCRIPTION OF THE DRAWINGS
[0008] Figures 1A to 1G A top view showing various stages of a method for manufacturing a DRAM according to an embodiment of the present invention,
[0009] Figures 2A to 2G Show Figures 1A to 1G The cross-sectional view of line A-A',
[0010] Figures 3A to 3G Show Figures 1A to 1G The cross-sectional view of line B-B',
[0011] Figure 4 A cross-sectional view of a DRAM according to another embodiment of the present invention is shown. DETAILED DESCRIPTION
[0012] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.
[0013] Figures 1A to 1G A top view showing various stages of a DRAM manufacturing method. Figures 2A to 2G Show Figures 1A to 1G A cross-sectional view along line A-A'. Figures 3A to 3G Show Figures 1A to 1G Cross-sectional view along line BB'.
[0014] Please refer to Figure 1A , Figure 2A and Figure 3A , providing a substrate 10. The substrate 10 may be a semiconductor substrate, such as a silicon substrate. An isolation structure 12 is formed in the substrate 10 to define a plurality of active areas AA. In some embodiments, the material of the isolation structure 12 includes silicon oxide, silicon nitride, high density plasma (HDP) oxide, spin-on silicon oxide, low dielectric constant (low-k) dielectric material, or a combination thereof. The isolation structure 12 may be a shallow trench isolation (STI) structure, a deep trench isolation (DTI) structure, or a combination thereof.
[0015] The isolation structure 12 defines a plurality of active areas AA in the substrate 10. The active areas AA are strip-shaped. Each active area AA has a long side L1 and a short side L2. In some embodiments, the long side L1 extends along the W direction; the short side L2 extends along the Y direction, but the present invention is not limited thereto. The W direction and the X direction include an angle θ. The angle θ can be 15° to 50°. In some embodiments, in the W direction, a plurality of active areas AA are arranged in a row; in the Y direction, a plurality of active areas AA are staggered with each other.
[0016] A hard mask layer 14 is formed on the substrate 10. The hard mask layer 14 may be a single layer or a multilayer material. The hard mask layer 14 may be formed by, for example, first forming a blanket hard mask layer on the substrate 10. Then, the hard mask layer is patterned by photolithography and etching processes. The material of the hard mask layer 14 may be, for example, silicon oxide, silicon nitride, or silicon oxynitride.
[0017] Please refer to Figure 1B , Figure 2B as well as Figure 3B , the substrate 10 is etched using the hard mask layer 14 as a mask to form a plurality of buried word line trenches 20. Each buried word line trench 20 extends along the Y direction and passes through the substrate 10 and the isolation structure 12 of the active area AA. The plurality of buried word line trenches 20 are arranged along the X direction. Due to the different etching rates, the depth of the plurality of buried word line trenches 20 in the isolation structure 12 is deeper, while the depth of the plurality of buried word line trenches 20 in the substrate 10 is shallower.
[0018] Please refer to Figure 1C , Figure 2C as well as Figure 3C, a gate dielectric structure 22 and a gate conductor layer 34 are formed on the hard mask layer 14 and in the multiple buried word line trenches 20. The gate dielectric structure 22 includes a first gate dielectric layer 24 and a second gate dielectric layer 26. The first gate dielectric layer 24 is, for example, a conformal layer, which conformally covers the hard mask layer 14 and the exposed hard mask layer 14, the isolation structure 12 and the substrate 10 on the sidewalls and bottom surfaces of the multiple buried word line trenches 20. The second gate dielectric layer 26 is, for example, a conformal layer, which conformally covers the first gate dielectric layer 24. The first gate dielectric layer 24 and the second gate dielectric layer 26 are dielectric materials with different dielectric constants. The dielectric constant of the second gate dielectric layer 26 is higher than the dielectric constant of the first gate dielectric layer 24. The first gate dielectric layer 24 is, for example, silicon oxide. The second gate dielectric layer 26 is, for example, silicon nitride or a high dielectric constant material. The high dielectric constant material can be a dielectric material with a dielectric constant greater than 7. The high dielectric constant material is, for example, HfAlO, HfO2, ZrO2, Ta2O5, Al2O3, Si3N4 or a combination thereof. In one embodiment, the first gate dielectric layer 24 is formed by in-situ steam oxidation technology and the isolation structure 12 is an oxide. Since the oxide of the isolation structure 12 cannot be oxidized, the isolation structure 12 exposed on the surface of the buried word line trench 20 will not form the first gate dielectric layer 24. Figure 4 shown.
[0019] The gate conductor layer 34 covers the second gate dielectric layer 26. The material of the gate conductor layer 34 includes metal or metal alloy, such as doped polysilicon, tungsten, tungsten silicide, etc. In some embodiments, a barrier layer 32 located between the second gate dielectric layer 26 and the gate conductor layer 34 may also be included. The barrier layer 32 may also be called an adhesion material layer. The barrier layer 32 may be a single layer or a multilayer, and its material includes metal or metal nitride, such as titanium, titanium nitride, tantalum, tantalum nitride or a combination thereof.
[0020] Please refer to Figure 1D , Figure 2D as well as Figure 3D , an etching process or a chemical mechanical polishing process is performed to remove a portion of the barrier layer 32 and a portion of the gate conductor layer 34 above the hard mask layer 14 and in the plurality of buried word line trenches 20, so as to form a gate conductor layer 34a and a barrier layer 32a in the plurality of buried word line trenches 20. The top surfaces of the gate conductor layer 34a and the barrier layer 32a are lower than the bottom surface of the hard mask layer 14, and the second gate dielectric layer 26 is exposed.
[0021] Please refer to Figure 1E , Figure 2E as well as Figure 3E, an etch-back process is performed to remove the second gate dielectric layer 26 above the hard mask layer 14 and in the plurality of buried word line trenches 20 to form a second gate dielectric layer 26a. The top surface of the second gate dielectric layer 26a is lower than the top surfaces of the gate conductor layer 34a and the barrier layer 32a. There is a gap G between the first gate dielectric layer 24 and the barrier layer 32a and above the second gate dielectric layer 26a. In some embodiments where the second gate dielectric layer 26 is silicon nitride, phosphoric acid may be used to perform a wet etching process. In some embodiments, the height of the top surface of the second gate dielectric layer 26a is higher than the height of the bottom surface of the source and drain regions 50 formed subsequently to avoid causing a drop in the on-state current (Ion Drop).
[0022] Please refer to Figure 1F , Figure 2F as well as Figure 3F , a cap layer 40 is filled in the multiple buried word line trenches 20. The cap layer 40 covers the top surfaces of the gate conductor layer 34a and the barrier layer 32a. The cap layer 40 does not fill in the gap G or does not fill the gap G completely, so an air gap (Air Gap) AG is formed between the first gate dielectric layer 24 and the barrier layer 32a and above the second gate dielectric layer 26a. The material of the cap layer 40 is, for example, silicon nitride. The method of forming the cap layer 40 is, for example, to form a cap material layer covering the first gate dielectric layer 24 and filling the multiple buried word line trenches 20 by chemical vapor deposition, and then remove the cap material layer covering the first gate dielectric layer 24 by etching back or chemical mechanical polishing.
[0023] The first gate dielectric layer 24 , the second gate dielectric layer 26 a , the barrier layer 32 a , and the gate conductor layer 34 a form a buried word line structure WL having an air gap AG.
[0024] Please refer to Figure 1G , Figure 2G as well as Figure 3G , source and drain regions 50 are formed in the substrate 10 in the active area AA on both sides of the buried word line structure WL.
[0025] The subsequent process includes forming a dielectric layer 60, a bit line contact window CA, a bit line BL, a capacitor contact window CC and a capacitor C on the substrate 10. The dielectric layer 60 may be multi-layered or formed in stages.
[0026] In some embodiments, the junction surface BS of the source and drain region 50 is lower than the top surface TS of the second gate dielectric layer 26a, so that the source and drain region 50 overlaps with the second gate dielectric layer 26a in the laterally direction. Since the second gate dielectric layer 26a is made of a dielectric material with a higher dielectric constant, the coupling effect can be increased during operation, thereby increasing the width of the depletion layer and thereby increasing the on-current Ion.
[0027] In some embodiments, the dielectric constant of the first gate dielectric layer 24 is 3.9 and the thickness is 3nm; the dielectric constant of the second gate dielectric layer 26a is 25 and the thickness is 4nm, and the on-current Ion can be increased to 265% of the original. In other embodiments, the dielectric constant of the first gate dielectric layer 24 is 3.9 and the thickness is 2nm; the dielectric constant of the second gate dielectric layer 26a is 25 and the thickness is 5nm, and the on-current Ion can be increased to 331% of the original. In some other embodiments, the dielectric constant of the first gate dielectric layer 24 is 3.9 and the thickness is 1.5nm; the dielectric constant of the second gate dielectric layer 26a is 25 and the thickness is 5.5nm, and the on-current Ion can be increased to 364% of the original.
[0028] In an embodiment of the present invention, since the second gate dielectric layer 26a uses a dielectric material with a higher dielectric constant, it can be made thicker. Therefore, the problem of gate leakage current (GIDL) caused by reducing the thickness of the gate dielectric layer in order to increase the coupling effect can be improved and avoided. In some embodiments, the dielectric constant of the first gate dielectric layer 24 is 3.9 and the thickness is 3nm; the dielectric constant of the air gap AG is 1 and the thickness is 4nm, and the GIDL can be reduced by 50%. In other embodiments, the dielectric constant of the first gate dielectric layer 24 is 3.9 and the thickness is 2nm; the dielectric constant of the air gap AG is 1 and the thickness is 4nm, and the GIDL can be reduced by 62%. In some other embodiments, the dielectric constant of the first gate dielectric layer 24 is 3.9 and the thickness is 1.5nm; the dielectric constant of the air gap AG is 1 and the thickness is 5.5nm, and the GIDL can be reduced by 68%.
[0029] In the embodiment of the present invention, the source and drain regions 50 are laterally separated from the gate conductor layer 34a by an air gap AG. Since the dielectric constant of the air gap AG is only 1, the electric field can be reduced, thereby reducing the gate induced drain leakage (GIDL) and reducing the leakage current caused by the depletion layer generated in the substrate 10 near the source and drain regions 50 through the gate conductor layer 32a of the isolation structure 12.
[0030] In the embodiment of the present invention, the first gate dielectric layer 24 is first formed in the buried word line trench 20, and then the second gate dielectric layer 26 is formed. Compared with the second gate dielectric layer 26, the first gate dielectric layer 24 has better surface flatness, so it can avoid the electrical problems caused by poor surface flatness when the second gate dielectric layer 26 is directly formed in the buried word line trench 20. Therefore, the embodiment of the present invention can increase the reliability of the device.
[0031] Furthermore, in the embodiment of the present invention, the end of the second gate dielectric layer 26 is removed to form an air gap AG, thereby reducing the problem of leakage caused by the end of the gate dielectric layer being too thin, thereby increasing the reliability of the gate dielectric layer.
[0032] In addition, in the embodiment of the present invention, the material and thickness of the first gate dielectric layer 24 and the second gate dielectric layer 26 as well as the depth of the air gap AG can be flexibly adjusted according to the required electrical properties or characteristics of the device.
[0033] In the manufacturing process of the present invention, no additional photomask is needed to pattern the first gate dielectric layer 24 and / or the second gate dielectric layer 26 , and therefore, the manufacturing cost will not be excessively increased.
[0034] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A dynamic random access memory, characterized in that: include: substrate; An isolation structure, located in the substrate, wherein the isolation structure defines a plurality of active regions; A buried word line structure is located in a word line trench of the substrate, the word line trench passes through the plurality of active regions and the isolation structure, and the buried word line structure comprises: A gate conductor layer is located in the word line trench; A first gate dielectric layer is located on the sidewalls and bottom surface of the word line trench; and a second gate dielectric layer, located between the first gate dielectric layer and the gate conductor layer, and a top surface of the second gate dielectric layer is lower than a top surface of the gate conductor layer, wherein a first sidewall of the first gate dielectric layer of the buried word line structure passing through the isolation structure contacts the isolation structure, An air gap is formed between the sidewall of the gate conductor layer, the second sidewall of the first gate dielectric layer, and the top surface of the second gate dielectric layer, and is exposed in the air gap.
2. The dynamic random access memory of claim 1 , wherein the air gap comprises: A first air gap is located at a first side of the gate conductor layer; and A second air gap is provided at a second side of the gate conductor layer. 3 . The dynamic random access memory according to claim 1 , wherein the first gate dielectric layer and the second gate dielectric layer are dielectric materials with different dielectric constants. 4 . The dynamic random access memory according to claim 1 , wherein a dielectric constant of the second gate dielectric layer is greater than a dielectric constant of the first gate dielectric layer.
5. The dynamic random access memory according to claim 1, further comprising a plurality of source and drain regions located in the active area on both sides of the buried word line structure, and the junction depth of the source and drain regions is lower than the top surface of the second gate dielectric layer.
6. The dynamic random access memory according to claim 1, wherein the buried word line structure further comprises a capping layer located in the word line trench and covering the gate conductor layer and the second gate dielectric layer, and a bottom surface of the capping layer is exposed to the air gap.
7. The dynamic random access memory according to claim 6, wherein the buried word line structure further comprises a barrier layer located in the word line trench and between the gate conductor layer and the second gate dielectric layer, and a sidewall of the barrier layer is exposed in the air gap.
8. A method for manufacturing a dynamic random access memory, characterized in that: include: providing a substrate; forming an isolation structure in the substrate, wherein the isolation structure defines a plurality of active regions; forming a word line trench in the substrate and the isolation structure, the word line trench passing through the plurality of active regions and the isolation structure; as well as A buried word line structure is formed in the word line trench, comprising: forming a first gate dielectric layer, a second gate dielectric layer and a gate conductor layer over the substrate and in the word line trench, wherein the dielectric constant of the second gate dielectric layer is greater than the dielectric constant of the first gate dielectric layer; removing a portion of the gate conductor layer outside the word line trench and within the word line trench; removing a portion of the second gate dielectric layer outside the word line trench and in the word line trench, so that a top surface of the remaining second gate dielectric layer is lower than a top surface of the remaining gate conductor layer; and forming a cap layer in the word line trench to cover the top surface of the remaining gate conductor layer, wherein a first sidewall of the first gate dielectric layer of the buried word line structure passing through the isolation structure contacts the isolation structure, The top surface of the cap layer, the side wall of the gate conductor layer, the second side wall of the first gate dielectric layer and the top surface of the second gate dielectric layer jointly form an air gap and are exposed in the air gap. 9 . The method for manufacturing a dynamic random access memory according to claim 8 , wherein air gaps are formed on both sides of the gate conductor layer.
10. The method for manufacturing a dynamic random access memory according to claim 8, further comprising forming a plurality of source and drain regions in the active area on both sides of the buried word line structure, and the junction depth of the source and drain regions is lower than the top surface of the second gate dielectric layer.